Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 8
`
`and is optimized based on the memory needsofa specific program running on the reconfigurable
`
`processor.
`Asper claims 3 and 14, Paulraj teaches in paragraph 23 that a specific [cache]line size of
`contiguousdatais not retrieved since the data line size is optimizedbased on the memory needs
`
`of the program when executing on the reconfigurable processor. Refer also to paragraph 29.
`
`Further, it is therefore inherent that the second memory havea charactersitic line size since
`Paulraj teaches in §]22-23 that a best line size for the memory arrangementfor a particular
`
`program is determined andutilzied when that program is run. For example, a line-size
`
`characteristic would be ultized whentransferring data from the L2 cacheto the L1 cache.
`
`Asper claim 4, Paulraj teachesthat a load/store unit is used to access the caches (L1-L3)
`in order to Sitennin’ ifcache data is present in the cache hierarchy (paragraph 6). Since the
`
`functional unit 102 (figure 6) is responsible for accessing the programmable memory unit 104,
`
`the Examineris therefore considering the load/store unit logic of the programmable memory unit
`
`that is responsible for for accessing the L1 and L2 caches(first and second memorytypes)to be
`
`a memory controller. It can be seen that the memory controller, as defined by the Examiner,
`
`controls the transfer of data between the memory (assuming second memory L2) and the data
`
`prefetch unit, since the memory controller (load/store unit logic) is responsible for retrieving the
`
`data from the cache if a hit occurs (paragraph4).
`
`Asper claim 5, as taught in paragraph 1, an external memory (element18, figure 1) is
`generaly coupled to a microprocessor and holdsdata to be used by the saieioonivolléx during
`
`program execution. The Examineris considering the process of writing data back to the external
`
`memory from the FPGA memory 104 containing the caches (on-board memory), such as during
`
`151
`
`151
`
`

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`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 9
`
`a write-back scheme as knownintheart, to be performed by the data prefetch unit portion of the
`
`functional logic as defined above by the Examiner. The data prefetch logic, as defined above,is
`reaponsible for all ofthe transfer ofdata into, out of, and between the FPGA memory 104. |
`Asper claim 6, the Examineris regarding a --register-- in its broadest reasonable sense
`
`andit thus consideringit be to be a unit of logic. Therefore, the portion of the function logic that
`
`is responsible for the movementofdata (as defined aboveto be the data prefetch unit) is being
`considered by the Examineras containing a --register-- portion ofthe reconfigurable processor
`
`since, for instance, the blocking factor and line size of the programmable memory 112 can
`
`change,a --register-- or portion of the reconfigurable processor must be set in order to indicate
`
`the curmetline size and blocking factor when a given application is being run on the
`fecsntiwurable processor at a given point in time. Refer to paragraph 23.
`
`Asper claim 7, the Examineris considering the process of --disassembling the data
`
`prefetch unit-- as modifying the data prefetch unit logic of the fucntion logic 102 every time the
`
`program being executed by the reconfigurable processor changes.
`
`It can be seen that the data
`
`prefetch unit changes during these intervals since the cacheline size, blocking factor, and
`associativity ofthe FPGA changes when optimalfor the nie program to be executed (referto
`
`paragraph 23). Thusit can be seen thatthe data prefetch unit logic is --disassembled-- when
`
`another program is executed by the reconfigurable processor of Paulraj.
`Asper claim 8, as can be seen that the FPGA memory 112, that comprises the first and
`
`second memories (L1 and L2) and whichis accessed by the data prefetch unit of the functional
`unit 102 as discussed above,is a --processor memory-- (part of cpu 110). It can also be seen that: -
`
`the --second memory-- (L2) is also a --processor memory-- since it is contained within
`
`152
`
`152
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`

`" Application/Control Number: 10/869,200
`Art Unit: 2186
`
`:
`
`.
`
`Page 10
`
`eegurable processor 110. Therefore, since the data pretech unit can access the L2 cache as
`discussed abovein the rejection ofclaim 1, the data prefetch unit can retrive data from the L2
`portion of --processor memory--112.
`.
`
`Asper claim 9, as shown in figure 1 and taught in paragraph 1 of Paulraj, the system 10
`is actually a microprocessor, which contains a memory controller 14. The main difference
`
`between thepriorart of figure 1 and the invention of Paulraj in figure 6 is that the memroy
`
`hierarchy is configurable and accessed bya fucntional unit in lieu of a separate memory
`
`controller logic (paragraph 9). Therefore, since the memory controller logic for accessing the
`cachehierarchyis still contained within cpu 110 of figure 6, it can be seen that the Spt 110 is
`
`actually a microprocessor. It follows that the --processor memory-- 112 is therefore a
`
`--microprocessor memory--.
`
`Asper claim 10, since the cpu 110 offigure 6 is a reconfigurable processer(able to
`
`reconfigure its memoryheirarchy to match the needsof the application it is currently running),it
`
`can be seen that the cpu memory 112 is a reconfigurable processor memory.
`Asper claim 11, Paulraj depicts a reconfigurable hardware system in figure 6. Paulraj
`
`further teaches in paragraph 26 that whenaparticular applicationis to be run by the
`
`reconfigrable processor 110, a configuration vectoris retrieved to program the programmable
`
`memory 112 (figure 6). As shownin figure 6, the step of accesing the configuration vectoris
`
`executed outside of the reconfigurable processor 110. Therefore, the Examineris considering
`
`the memory that contains the configuration vectors to be a--common memory-- and a data
`
`prefetch unit (reconfiguration unit 106 executing on the reconfigurable processor 110) accessing
`
`the common memory in order to determine how to program the memory 112 (paragraph 29).
`
`153
`
`153
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`_
`
`Page 11
`
`The data prefetch unit106 is --configured-- by an application to be excuted on the sysem 110
`since whena new application is to be executed, the data prefetch unit is called upon (or
`configured) to access the configuration vectorfor the particular application.
`.
`
`|
`
`The reconfigurable processor of Paulraj has the ability to collect memory usagestatistics
`
`for a particular application and based onthosestatistics, create a configuration vector as taught in
`
`4123-24. This vector allows the programmable memory module 104 of Paulraj to be
`
`‘reconfigured to the most optimal memory configuration for that specific software program (126).
`
`As defined by the Applicant in 955 ofthe originally filed specification, a software programor
`application is a collection of“algorithms”; therefore, the configuration vector for a particular
`software program allows the system of Paulraj to instantiate a software program as hardware
`
`since the configuration vector represents optimal configuration of the hardware (programmable
`memory module 104 - element 112 offigure 6).
`|
`
`Asper claim 12, the Examiner is considering a --memory controller-- to be the system
`portion utilized when creating a new configuration vector for an application. Such a process
`
`occurs in figure 5 and taught in paragraghs 23-25 of Paulraj. When a new configuration vectoris
`
`created by analizing performance information that has been collected for the application. The
`Examiner is thereby considering the --memory controller-- to be the element ofthe
`
`reconfigurable hardware system thatis associated with storing the new configuration vector into
`the common memoryso that the vector can be accessed later when the same application is run
`
`again.
`
`Asper claim 15, the Examiner is considering the reconfiguration module 106 of the -
`
`reconfigurable processsor 110, as comprising two distinct elements: a --computational unit-- and
`
`154
`
`154
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 12
`
`a --data access unit--, The data access unit is the elementthat is responsible for accessing the
`
`configuration vector as taught in paragraph 29 of Paulraj; or in other words, the Examineris
`
`considering the --data access unit-- to be the same as the --memory controler-- defined in the
`
`rejection of claim 12. The Examineris further considering the --computational unit-- of the
`
`rconfiguration module 106 to be the elementthat sets up the programmable memory module 104
`
`using the configuration vector that was accessed by the --data access unit-- (paragraph 29).
`
`As per claim 16, as taught by Paulraj in paragraph 29, the --data access unit-- supplies the
`
`configuration vector to the --computational unit-- in order to set up the programmable memory
`104 as required by the application to be run a8 the reconfurable processor 110.
`
`Asper claim 17, the Examiner is considering a --data prefetch unit-- to be the
`
`reconfiguration unit 106 of reconfigurable processor 110 (figure 6). As taught in paragraph 26
`
`and 29 of Paulraj, the --data prefetch unit-- accesses a memoryin order to determineif a
`
`configuration vector is known for a given application, and if so, the vector is retrieved (from the
`
`memory). If this --data-- (configuration vector) is not knownthen a simulation is performed with
`
`the application in order to collect performance information. The Examineris considering the
`
`elementthat executes and collects the performancedata as being a --computational unit-- and the
`
`element of Paulraj that stores the configuration vector, once determined, to be a --data access
`
`unit-- since it stores the vector into the --memory-- from whichit can be later retrieved (step 212
`
`offigure 5).
`
`All of the computational, data access, and data prefetch units are configured by a
`
`program, as immediately discussed. As defined by the Exam iner, the “computational unit” of
`
`Paulraj is being considered to be the elementof the system of Paulraj that executes and collects
`
`155
`
`155
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`;
`
`Page 13
`
`the performance data regarding howa specific applicationutilizes memory in order to determine
`
`an optimal memory configuration as discusses in §27. Figure 5 of Paulraj shows a method for
`
`creating a configuration vector by using the --computational unit-- in steps 204-206. The
`
`Examineris considering the inherent programthat is being executed in order to perform the
`steps of figure 5 to be the program that configures the computational unit. Therefore, it can be
`
`seen that Paulraj suggests configuring the computational unit by a program. The program of
`
`figure 5 configures the computational unit to collect data for a specific application’s memory
`
`usage statistics in order to create a configuration vectorthat allows the system of Paulraj to
`
`optimally reconfigure the programmable memory module 104. Thus the computational unit can
`
`be configured to collect memory usagestatistics for a plurality of applications that are to be
`
`executed by the reconfigurable processor 100 of Paulraj (423).
`
`The same reasoning applies to the data access and data prefetch units. The program that
`
`is executing the steps offigure 5 (i.e. running on the system of Paulraj that implements the
`
`method) configures the data accessunitto retrieve/store a configuration vector (step 212) based
`
`on if anew configuration vector had to be created and further configures the data prefetch unit to
`
`search for a configuration vector and retrieve that vector if found (steps 200 and 212).
`
`Asper claim 18, the --data-- (configuration vector) is transferred from the
`
`--computational unit-- to the --data access unit-- when the configuration unit has createda_ .
`
`configuration vector (step 208 of figure 5). The --data-- is written to the memory --from-- the
`
`--data prefetch unit-- since the data prefetch unit (reconfiguration unit 106) is the elementthat
`
`executed the beginning of the configuration vectorcreation process (step 200offigure 5). Refer
`
`156
`
`156
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 14
`
`|
`
`to paragraph 26. Thus the Examineris considering the data as being written --from-- the data
`
`prefetch unit.
`
`Asper claim 19, as taught in paragraph 26,if the configuration vector is known,the
`vectoris retrieved from the memory to the data prefetch unit (reconfiguration unit 106). The
`
`data is read directly from the data prefetch unit when a request to create a configuration vectoris
`
`made for a new application as shownin figure 6 since the data prefetch unit is responsible for
`
`being the vector creation process. The data is directed from the data prefetch unit (reconfigure
`
`logic) to be read from the memoryby the data access unit tothe computational unit whereitis
`
`processed to produce a configuration vector.
`
`Asperclaim 20, as stated above, the configuration vector(--data--) is created by the
`
`computational unit via acquired simulation data. The configuration vectoris the resultant
`product that is transferred from the memoryto the data prefect unit whenit is determined that the
`
`configuration vector for the application is available (paragraph 26). Thus--all-- of the data that
`
`is transferred is processed by the computational unit (albeit before the transfer occurs) since the
`
`data prefetch unit required the entire configuration vectorin order to set up the programmable
`
`memory 112.
`
`As per claim 21, Paulraj shows in paragraph 26 that an explicit requestfor the
`
`configuration vector for the current application results in the data (if it exists) selected for the
`
`optimal configuration of the programmable memory 112 for that application.
`. Asper claim 22, the Examineris not considering the data (configuration vector) to be the
`
`size of a complete cache line since the data is used to create a cache hierarchy.
`
`In other words,
`
`the caches (L1-L3) of the programmable memory112 are not programmed whenthe datais |
`
`157
`
`157
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 15
`
`transferred from the memory to the data prefetch unit; therefore, the data cannot be a complete
`
`cacheline.
`
`As per claim 23, since the Examinerdefined the portion of the reconfiguration unit that
`accesses the configuration file (data) from the memory, the Examineris defining the logic that
`
`controls the actual transfer of that data to the data prefetch unit (portion of the reconfiguration
`
`unit that executes the fetch of theconfiguration vector and then programs the programmable
`
`memory 112) to be a --memory controller--. Thus the data access unit determines whether a
`configuration vector exists for an application and ifso, the memory controller sends that data to
`the data prefetch unit.
`|
`
`Asper claim 24, Paulraj shows a reconfigurable processorin figure 6 that comprises a
`
`computation unit 110 and a data access unit (elements 120 and 114, which comprise the
`
`reconfiguration unit 106 of figure 4 - 428). In figure 6, the data access unit can be seen as being
`oe to the computational unit. The data access unit retrieves data (configuration vector)
`from a memoryinternal to the data accessunit (i.e. recontigursiion unit) and supplies the data to
`
`the computation unit in the form of modifications to the cache FPGA module 112. Refer to 423.
`| The Examineris considering the inherentprogram that is being executed in orderto
`
`perform thesteps of figure 5 to be the program that configures the computationalunit.
`Therefore,it oii-be seenthat Paulraj suggests configuring the computational unit by a program.
`
`The program offigure 5 configures the computational unit to collect data for a specific
`
`application’s memory usagestatistics in order to create a configuration vector that allows the
`
`system of Paulraj to optimally reconfigure the programmable memory module 104. Thusthe
`
`158
`
`158
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 16
`
`|
`
`computational unit can be configured to collect memory usagestatistics for a plurality of
`
`applications that are to be executed by the reconfigurable processor 100 of Paulraj (23).
`The data access unit (specifically the memory portion used to store configuration profiles
`for the different application programs) is configured by the program thatis responsible for
`
`running the methodoffigure 5 of Paulraj as discussed supra. When a newapplication is to be
`
`run, [as a result] the program performsthe steps 204-206 to configure the reconfiguration unit to
`
`collectstatistics regarding the memory usages (caches L1, L2, and L3) of the application and a
`configuration vector is associated with the respective application andstored in the
`
`reconfiguration unit. Refer to §/23-24. When an application is known, the program executing
`
`the method offigure 5 [as a result] configures the data access unit (reconfiguration unit) to
`retrieve the associated configuration vector and apply it to the FPGA memory ofthe
`
`reconfigurable processor(429).
`
`In other words, once the software program has been loaded into the computationalunit, a
`
`variety of simulations are performed and memoryusagestatistics are gathered by the
`
`computational unit in order to create a configuration vector as taughtin {]23-24. This vector
`
`allows the programmable memory module 104 of Paulraj to be reconfigured to the most optimal
`
`memory configuration for that specific software program (26). As discussed supra, a software
`
`program or application is a collection of “algorithms”; therefore, the configuration vectorfor a
`
`particular software program allowsthe system of Paulraj to instantiate a software program as
`
`hardware since the configuration vector represents optimal configuration of the hardware
`
`(programmable memory module 104 - element 112 offigure 6).
`
`159
`
`159
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 17
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the
`smantiince should be directed to Shane M. Thomas whosetelephone numberis (571) 272-4188.
`
`The examiner can normally be reached on M-F 8:30 - 5:30.
`
`If attempts to reach the examinerby telephone are unsuccessful, the examiner’s
`
`supervisor, Matt M. Kim can be reached on (571) 272-4182. The fax phone numberfor the
`
`organization wherethis application or proceedingis assigned is 571-273-8300
`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished |
`
`applicationsis available through Private PAIR only. For more information about the PAIR
`
`system, see http://pair-direct.uspto.gov. Should you have questions on accessto the Private PAIR
`
`system, contact the Electronic Business Center (EBC)at 866-217-9197(toll-free).
`
`Ba— by (W_
`
`Shane M. Thomas
`
`.
`
`HONG CHONG Kil
`PRIMARY EXAMINER
`
`160
`
`160
`
`

`

`
`|_|aaPETTyTI_rETTTTTTTEETETTETETEEETEEEETEETTEEEEEETEEPtTTTTT%62|,PittttttitttetetETEETtH+naPEtTT|2BpaRaSleielil oadZzoe&c28|(alLtTTTTTtTeTTEEPEttTttaetyTETETETETETT=qsPTETETETTTTeTettTTetTEETEEPTTETET=90Ltt
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`NENIN[09]03909[909)0909]29/09/09S\|FVitissyoO
`
`
`
`Index of Claims
`
`
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`-i
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`Tc&2°
`ax
`2
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`aca38&oOm=Ee
`
`
`Date
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`feuly
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`
`
`yt|Tt
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`
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`
`
`
`||
`||
`If
`
`a
`
`
`
`
`
`
`
`¥ v|f
`
`
`
`
`v
`v
`eetvivivyty
`Laatviviy
`|2avv
`
`
`
`
`
`
`
`
`
`
`
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`
`U.S. Patent and Trademark Office
`
`Part of Paper No. 10152005
`
`161
`
`161
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`

`

`Search Notes
`
`Application/Control No.
`
`Applicant(s)/Patent under
`Reexamination
`
`10/869,200
`
`POZNANOVIC ET AL.
`
`Shane M. Thomas
`
`Date
`
`SEARCH NOTES
`(INCLUDING SEARCH STRATEGY)
`
`ce
`
`INTERFERENCE SEARCHED
`
`Updated East Search
`
`741/170-173 (text search only - see
`search printout)
`
`tt
`
`U.S. Patent and Trademark Office
`
`Part of Paper No. 10152005
`
`162
`
`162
`
`

`

`
`
`
`
`RECEIVED
`
`Jan-05-2006 From-HOGAN & HARTSON=CENTRAL FAX CENTER =P.001/008+F-08214:57 T-310
`JAN 05 2006
`
`
`
`Fax No. 719-448-5922
`
`PTO/SBV25 (06/03)
`Appraved for uso throvgh 07/31/2008. OMB 0854-0031
`a
`:
`etl
`Patent anc ‘Trademark Ontlea: US. DEPARTMENTOF SONERCE
`
`Certificate of Transmission under 37 CFR 1.8
`
`Serial No. 10/869,200
`Application of: Daniel Poznanovic, David E. Caliga, and Jeffrey Hammes
`Filed: June 16, 2004
`
`Art Unit: 2186
`
`Examiner: Thomas, Shane M.
`
`Attorney Docket No. SRC028
`.| For:
`SYSTEM AND METHOD OF ENHANCING EFFICIENCY AND UTILIZATION
`OF MEMORY BANDWIDTH IN RECONFIGURABLE HARDWARE
`Confirmation No.: 5929
`Customer No.: 25235
`
`5S25
`
`| hereby certify that this correspondence is being facsimile transmitted to the United
`States Patent and Trademark Office
`
`1. Amendmentin responseto the Office Action dated October 19, 2005.
`
`5
`
`ale
`
`Date
`
`9
`No. of Pages
`(incl. Geversheet)
`
`to centralized fax number: 571-273-8300
`
`Juli
`Typed or printed nameof person signing Certificate
`
`Note: Each paper must haveits own certificate of transmission,orits certificate must
`identify each submitted paper.
`
`Client Reference No. 80404,0033.001
`
`WCS « 77287 vi
`
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`163
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`

`

`-05-
`Jan-05~2006
`
`14:57
`5
`
`From-HOGAN & HARTSON
`rom
`
`+
`
`RECEIVED
`CENTRALFAX CENTER
`JAN 05 2006
`
`T-910
`
`P.002/008
`
`F-082
`
`Client Matter No. 80404.0033.001
`Via Facsimile
`
`IN THE UNITED STATES PATENT AND TRADEMARKOFFICE
`
`Serial No. 10/869,200
`_| Application of: Daniel Poznanovic, David E. Caliga,
`and Jeffrey Hammes
`Filed: June 16, 2004
`
`Confirmation No.: 5929
`CustomerNo.: 25235
`
`BANDWIDTH IN RECONFIGURABLE HARDWARE
`
`Art Unit: 2186
`
`Examiner: Thomas, Shane M.
`Attorney Docket No. SRC028
`For:
`SYSTEM AND METHOD OF ENHANCING
`EFFICIENCY AND UTILIZATION OF MEMORY
`
`AMENDME
`
`MAIL STOP AMENDMENT
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Sir:
`
`In response to the office communication mailed October 19, 2005, please
`
`amend the above-identified application as follows:
`
`Amendments to the Claims are reflected in the listing of claims which
`
`begins on page 2 of this paper.
`
`Remarks/Arguments begin on page6 of this paper.
`
`WOS - Przg7 wi
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`164
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`Jan-05-2006
`
`14:57
`
`From-HOGAN & HARTSON
`
`+
`
`T-910
`
`P.003/008
`
`F082
`
`Serial No. 10/869,200
`Reply to Office Action of Octaber 19, 2005
`
`
`Amendments to the Claims:
`
`This listing of claims will replace all prior versions andlistings of claims in the
`application:
`
`Listing of Claims:
`
`1.
`
`(Previously Presented) A reconfigurable processorthatinstantiates
`
`an algorithm as hardware comprising:
`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
`
`a data prefetch unit coupled to the first memory, wherein the data prefetch
`
`unit retrieves data from a second memory of second characteristic memory
`
`bandwidth and/or memory utilization and place the retrieved data in the first
`
`memory and wherein at
`
`least
`
`the first memory and data prefetch unit are
`
`configured by a program.
`
`2s
`
`3.
`
`(Cancelled)
`
`(Cancelled)
`
`(Previously Presented) The reconfigurable processor of claim 1,
`4,
`wherein the data prefetch unit is coupled to a memory controller that controls the
`
`transfer of the data between the second memory andthe data prefetch unit.
`
`(Previously Presented) The reconfigurable processor of claim 1,
`5,
`wherein the data prefetch unit receives processed data from on-processor
`memory and writes the processed data to an extemal off-processor memory.
`
`WICS - 77287 v1
`
`2
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`Jan-05-2006 =P.004/008+F-08214:57 From-HOGAN & HARTSON + T-910
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`
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`
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`
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`
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`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
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`(Original) The reconfigurable processor of claim 1, wherein the
`6.
`data prefetch unit comprises at
`least one register from the reconfigurable
`
`processor.
`
`(Original) The reconfigurable processor of claim 1, wherein the
`G
`data prefetch unit is disassembled when another program is executed on the
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`reconfigurable processor.
`
`(Previously Presented) The reconfigurable processor of claim 1
`8,
`wherein said second memory comprises a processor memory and said data
`
`prefetch unit is operative to retrieve data from the processor memory.
`
`9.
`
`(Original) The reconfigurable processor of claim 8 wherein said
`
`processor memory is a microprocessor memory.
`
`10.
`
`(Original) The reconfigurable processor of claim 8 wherein said
`
`processor memory is a reconfigurable processor memory.
`
`11.
`comprising:
`
`(Previously Presented)
`
`A reconfigurable hardware system,
`
`a common memory; and
`one or more reconfigurable processors that can instantiate an algorithm
`as hardware coupled to the common memory, wherein at least one of the
`
`reconfigurable processors includes a data prefetch unit to read and write data
`betweenthe data prefetch unit and the common memory, and wherein the data
`prefetch unit is configured by a program executed on the system.
`
`The reconfigurable hardware system of claim 11,
`(Original)
`12.
`comprising a memory controller coupled to the common memory and the data
`prefetch unit.
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`WOS » 77287 v1
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`Jan-05-2006
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`14:58
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`From-HOGAN & HARTSON
`
`+
`
`T-910
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`©P.005/008
`
`F-082
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
`
`13.
`
`(Cancelled)
`
`14.
`
`(Cancelled)
`
`(Previously Presented) The reconfigurable hardware system of
`15.
`claim 11, wherein the at least one of the reconfigurable processors also includes
`a computational unit coupled to a data access unit.
`
`16.
`
`(Original)
`
`The reconfigurable hardware system of claim 15,
`
`wherein the computational unit ts supplied the data by the data accessunit.
`
`(Previously Presented) A method oftransferring data comprising:
`17.
`transferring data between a memory and a data prefetch unit
`in a
`
`reconfigurable processor; and
`
`transferring the data between a computational unit and a data access unit,
`wherein the computational unit and the data access unit, and the data prefetch
`unit are configured by a program.
`
`18.
`(Original) The methed of claim 17, wherein the data is written to
`the memory, said method comprising:
`
`transferring the data from the computational unit to the data access unit;
`
`and
`
`writing the data to the memory from the data prefetch unit.
`
`19.
`
`(Previously Presented) The method of claim 17, wherein the data
`
`is read from the memory, said method comprising:
`
`transferring the data from the memory to the data prefetch unit; and
`reading the data directly from the data prefetch unit to the computational
`unit through the data access unit.
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`WS - 77287 v1
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`Jan-05-2006 14:58
`
`From-HOGAN & HARTSON
`
`+
`
`T-910
`
`P.006/009
`
`F082
`
`Serial No, 10/869,200
`Reply to Office Action of October 19, 2005
`
`20.
`
`(Original) The method of claim 19, wherein all the data transferred
`
`from the memory to the data prefetch unit is processed by the computational
`unit.
`
`(Original) The method of claim 19, wherein the data is selected by
`21.
`the data prefetch unit based on an explicit request from the computationalunit.
`
`22.
`
`(Original) The method of claim 17, wherein the data transferred
`
`between the memory and the data prefetch unit is not a complete cacheline.
`
`(Original) The method of claim 17, wherein a memory controller
`23.
`coupled to the memory and the data prefetch unit, controls the transfer of the
`
`data between the memory and the data prefetch unit.
`
`24.
`
`(Cancelled)
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`wG5 - T7287 v1
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`Jan-05-2006
`
`14:58
`
`From-HOGAN & HARTSON
`
`+
`
`T-910
`
`P.007/009
`
`F-082
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
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`REMARKS/ARGUMENTS
`
`Claims 1, 4-12, and 15-24 were presented for examination and are pending
`
`in this application.
`
`In an Official Office Action dated October 19, 2005, claims 1, 4-
`
`12, and 15-24 were rejected. Claim 24 is canceled without prejudice and no new
`
`claims are presently added. Claims 1, 4-12, and 15-23 remain pending. The
`
`Applicants thank the Examiner for his consideration and address the Examiner's
`
`comments concerning the claims pending in this application below.
`
`Rejection of the Claims under 35 U.S.C. §102(e)
`
`Claims 1, 3, 4, 7-10, and 12-18 were rejected under 35 U.S.C. §102(e) as
`
`being anticipated by U.S. Patent Application Publication No. 2003/0084244
`
`("Paulraj”). Applicants respectfully traverse these rejectionsin light of the following
`
`remarks.
`
`MPEP §2131provides:
`
`“A claim is anticipated only if each and every elementassetforth in
`
`the claim is found, either expressly or inherently described, in a
`
`single prior art reference.” Verdegall Bros. v. Union Oil Co. of
`Califomia, 814 F.2d 628, 631, 2 U.S.P.Q.2d 1051, 1053 (Fed.
`
`Cir.1987). “The identical invention must be shown in as complete
`
`detail as contained in the claim.” Richardson v. Suzuki Motor Co.,
`
`868 F.2d 1226, 1236, 9 U_S.P.Q.2d 1913, 1920 (Fed. Cir. 1989).
`
`Paulraj fails to disclose each and every limitation recited in the claims, The
`Examiner reasons that Paulraj discloses a system having a program that
`reconfigures computational units, data access units, and pre-fetch units. The
`Applicants disagree.
`The Examiner's logic in making the above assertion Is faulty. Assume for
`argument sake (as does the Examiner) that the computational unit is the element of
`the Paulraj system that executes and collects performance data regarding an
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`"—
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`Jan-05-2008
`
`14:88
`
`From-HOGAN & HARTSON
`
`+
`
`T-910
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`P.008/009
`
`F082
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
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`application to determine an optimal memory configuration. The program operating
`on the Paulra] system depicted in Figure 5 of Paulraj “configures” the collection
`
`process so as to ascertain information about a specific application.
`
`In this sense
`
`the Examiner uses the term configure to state that the program executed by the
`
`Paulraj system modifies, directs, and/or controls the collection means (the
`
`computational unit) to properly assess the target application so that the memory
`
`can be optimally configured.
`The Examiner then extends this argument to the data access units and pre-
`fetch units. While such an extension is perhaps conceivable today given the
`
`presentinvention,it is not, nonetheless, disclosed by Paulraj. Nor Is it reasonable
`
`to conclude that such an extension would be apparent to one skilled in the art at the
`
`time of the Applicants’ invention.
`
`As the Examinerpoints out, Paulraj discloses creating a “configuration vector
`
`containing data relating to the optimal configuration to the necessary instruction for
`programming the programmable memory module.” Paulraj [0024}. Paulraj also
`discloses a reconfiguration module that uses the vectorto configure the
`programmable memory module. Once the Paulraj system collects information
`about the target application and creates the configuration vector for optimal
`memory module configuration, “the configuration vectoris then retrieved (step 212),
`used to program the FPGA module (step 214), and the application is executed with
`the optimal memory configuration for that application (step 216).” Paulraj [0026].
`The “program” that the Examiner considers to configure the computational
`unit does not, according to Paulraj, “configure” the data access unit northe pre-
`fetch unit. The Examiner restates that he considers the reconfiguration unit of
`Paulraj to be a data pre-fetch unit. The Examiner also correctly states that Pautlraj
`
`discloses that the reconfiguration unit retrieves the configuration vector and sets up
`
`It is conceivable to argue that the "program” of
`a programmable memory module.
`Figure 5 of Paulraj configures the configuration vector to configure the
`
`WS - T7267 vi
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