IN THE UNITED STATES DISTRICT COURT
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELA WARE
`FOR THE DISTRICT OF DELAWARE
`
`FUNDAMENTAL INNOVATION SYSTEMS
`FUNDAMENTAL INNOVATION SYSTEMS
`INTERNATIONAL LLC,
`INTERNATIONAL LLC,
`
`Plaintiff,
`Plaintiff,
`
`V.
`V.
`
`TCT MOBILE (US), INC.; TCT MOBILE
`TCT MOBILE (US), INC.; TCT MOBILE
`(US) HOLDINGS, INC.; HUIZHOU TCL
`(US) HOLDINGS, INC.; HUIZHOU TCL
`MOBILE COMMUNICATION CO. LTD.;
`MOBILE COMMUNICATION CO. LTD.;
`and TCL COMMUNICATION, INC.,
`and TCL COMMUNICATION, INC.,
`
`Defendants.
`Defendants.
`
`C.A. No. 1:20-CV-00552-CFC
`C.A. No. 1:20-CV-00552-CFC
`
`EXPERT REPORT OF R. JACOB BAKER, PH.D., P.E., AS TO THE
`EXPERT REPORT OF R. JACOB BAKER, PH.D., P.E., AS TO THE
`
`INVALIDITY OF U.S. PATENTS
`INVALIDITY OF U.S. PATENTS
`
`For the reasons discussed in this Report, which expressly includes the Appendices and
`For the reasons discussed in this Report, which expressly includes the Appendices and
`
`Exhibits, in my opinion, all asserted claims of the Asserted Patents are invalid due to at least the
`Exhibits, in my opinion, all asserted claims of the Asserted Patents are invalid due to at least the
`
`reasons detailed in this Report. I declare under penalty of perjury under the laws of the United
`reasons detailed in this Report. I declare under penalty of perjury under the laws of the United
`
`States of America that the foregoing is true and correct.
`States of America that the foregoing is true and correct.
`
`R. JAC I B BAKER, PHD, PE
`
`/tcH I ,1 2?L
`Date
`Date
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`I.
`
`II.
`
`III.
`
`Table of Contents
`
`EXPERIENCE AND QUALIFICATIONS ....................................................................... 2
`A.
`Industry Experience ............................................................................................... 2
`B.
`Academic Experience ............................................................................................ 5
`C.
`Other Relevant Experience .................................................................................... 6
`LEGAL PRINCIPLES ....................................................................................................... 7
`A.
`Claim Construction ................................................................................................ 7
`B.
`Invalidity ................................................................................................................ 7
`1.
`Anticipation................................................................................................ 8
`2.
`Obviousness ............................................................................................... 9
`3.
`Written Description and Enhancement .................................................... 10
`4.
`Definiteness.............................................................................................. 12
`5.
`Patentable Subject Matter ........................................................................ 13
`The Level of Ordinary Skill in the Art................................................................. 13
`C.
`Priority Date ......................................................................................................... 14
`D.
`OVERVIEW OF THE TECHNOLOGY AND ASSERTED PATENTS ....................... 15
`A.
`General Overview of the Technology .................................................................. 15
`1.
`Configuration of a USB Network ............................................................ 16
`2.
`Configuration of USB Connectors ........................................................... 19
`3.
`USB Specification for Communicating Between Devices ...................... 20
`4.
`USB Specification for Supplying and Drawing Power............................ 27
`The ’936 Patent Overview ................................................................................... 31
`Prosecution History of the ’936 Patent ................................................................ 33
`The ’111 Patent Overview ................................................................................... 35
`Prosecution History of the ’111 Patent ................................................................ 38
`The ’550 Patent Overview ................................................................................... 39
`Prosecution History of the ’550 Patent ................................................................ 43
`The ’586 Patent Overview ................................................................................... 43
`Prosecution History of the ’586 Patent ................................................................ 44
`The ’766 Patent Overview ................................................................................... 45
`Prosecution History of the ’766 Patent ................................................................ 47
`
`A.
`B.
`C.
`D.
`E.
`F.
`G.
`H.
`I.
`J.
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`IV.
`
`V.
`
`The ’187 Patent Overview ................................................................................... 47
`K.
`Prosecution History of the ’187 Patent ................................................................ 51
`L.
`CLAIM CONSTRUCTION ............................................................................................. 52
`A.
`Agreed Constructions........................................................................................... 52
`B.
`Construction of Disputed Terms .......................................................................... 55
`C.
`Preambles ............................................................................................................. 57
`INVALIDITY OF THE ASSERTED PATENTS BASED ON 35 U.S.C. §§ 102
`AND 103 .......................................................................................................................... 57
`A.
`Overview of the Prior Art References ................................................................. 57
`1.
`Matsumoto (U.S. Patent No. 6,904,488) .................................................. 57
`2.
`Kerai (U.S. Patent No. 6,531,845) ........................................................... 60
`3.
`Dougherty (U.S. Patent No. 7,360,004 ) .................................................. 61
`4.
`Yang (CN2410806Y) ............................................................................... 62
`5.
`Shiga (U.S. Patent No. 6,625,738) ........................................................... 63
`6.
`Zyskowski (US Patent Application US20030135766) ............................ 65
`7.
`De Iuliis (U.S. Patent No. 7,766,698) ...................................................... 65
`8.
`Gilbert (U.S. Patent No. 6,357,011)......................................................... 66
`Summary of Obviousness Grounds under 35 U.S.C. § 103................................. 67
`B.
`It is my opinion that the claims in the chart below are invalid as obvious under 35 U.S.C.
`§ 103................................................................................................................................. 67
`C.
`Invalidity of the ’936 Patent ................................................................................ 68
`D.
`Invalidity of the ’111 Patent ................................................................................ 69
`E.
`Invalidity of the ’550 Patent ................................................................................ 69
`F.
`Invalidity of the ’586 Patent ................................................................................ 70
`G.
`Invalidity of the ’766 Patent ................................................................................ 71
`H.
`Invalidity of the ’187 Patent ................................................................................ 71
`INVALIDITY OF THE ASSERTED PATENTS BASED ON 35 U.S.C. § 112 ............ 72
`A.
`Indefiniteness ....................................................................................................... 72
`B.
`Written Description .............................................................................................. 80
`INVALIDITY OF THE ASSERTED PATENTS BASED ON 35 U.S.C. § 101 .......... 100
`VII.
`VIII. CONCLUSIONS............................................................................................................ 110
`
`VI.
`
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`APPENDIX A - List of Materials Considered
`
`APPENDIX B - CV
`
`APPENDIX C-1 – C-6 - Invalidity Analysis
`
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`1.
`
`I have been retained in this matter as an expert witness by Defendants TCT Mobile
`
`(US), Inc.; TCT Mobile (US) Holdings, Inc.; Huizhou TCL Mobile Communication Co. Ltd.; and
`
`TCL Communication, Inc. (collectively “Defendants” or “TCL”) as to validity of U.S. Patent Nos.
`
`6,936,936 (the “’936 Patent), 7,239,111 (the “’111 Patent”), 8,624,550 (the “’550 Patent”),
`
`7,834,586 (the “’586 Patent”), 8,232,766 (the “’766 Patent”) and 8,169,187 (“’187 Patent”).
`
`2.
`
`I am being compensated for my work in this matter at an hourly rate of $615, which
`
`has been my standard rate at the time I was retained. My compensation in no way depends upon
`
`the outcome of this proceeding.
`
`3.
`
`The opinions expressed in this Report are my own and are based on my personal
`
`knowledge, my education, experience, and training, and on my understanding of the information
`
`and documents referenced in this Report. In forming the opinions expressed herein, I have
`
`considered the materials listed in the attached Appendix A as well as my knowledge and
`
`experience based upon my work in this area as described below. I also considered, and incorporate
`
`here by reference to them, any other materials referenced in this report, the materials included in
`
`my List of Materials Considered that was attached to any of my previously served declarations
`
`related to any of the asserted patents addressed herein, and any other materials referenced in my
`
`declarations filed with petitions for inter partes review and requests for reexamination of the
`
`asserted patents.
`
`4.
`
`I reserve the right to supplement or amend this Report after the receipt of any
`
`additional information or documents that I may receive after the date of my Report, or may be
`
`produced by Plaintiff, their experts (including their opening reports, rebuttal reports, or
`
`depositions), or third parties, or any other information that affects my opinions, including, but not
`
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`limited to, rulings, documents, or guidance from any of the pending challenges to any of the
`
`asserted patents at the US Patent and Trademark Office and/or PTAB.
`
`I.
`
`EXPERIENCE AND QUALIFICATIONS
`
`5.
`
`I have been working as an Engineer since 1985 and I have been teaching Electrical
`
`and Computer Engineering courses since 1991. I am currently a Professor of Electrical and
`
`Computer Engineering at the University of Nevada, Las Vegas (“UNLV”). I am also currently an
`
`industry consultant for Freedom Photonics. I am the named inventor on over 150 U.S. patents
`
`resulting from my industry work.
`
`6.
`
`I received the B.S. and M.S. degrees in Electrical Engineering from UNLV in 1986
`
`and 1988, respectively. I received my Ph.D. in Electrical Engineering from the University of
`
`Nevada, Reno, in 1993.
`
`7.
`
`My doctoral research, culminating in the award of a Ph.D., investigated the use of
`
`power MOSFETs in the design of very high peak power, and high-speed, instrumentation. I
`
`developed techniques to reliably stack power MOSFETs to switch higher voltages, that is, greater
`
`than 1,000 V and 100 Amps of current with nanosecond switching times. This work was reported
`
`in the paper entitled “Transformerless Capacitive Coupling of Gate Signals for Series Operation
`
`of Power MOSFET Devices,” published in the IEEE Transactions on Power Electronics. The paper
`
`received the Best Paper Award in 2000.
`
`A.
`
`8.
`
`Industry Experience
`
`I have done technical and expert witness consulting for over 120 companies since
`
`I started working as an engineer in 1985. From 1985 to 1993 I worked for EG&G Energy
`
`Measurements and the Lawrence Livermore National Laboratory designing nuclear diagnostic
`
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`instrumentation for underground nuclear weapon tests at the Nevada test site. During this time, I
`
`designed, and oversaw the fabrication of, over 30 electronic and electro-optic instruments
`
`including high-speed cable and fiber-optic receiver/transmitters, PLLs, frame and bit-syncs, data
`
`converters, streak-camera sweep circuits, Pockel’s cell drivers, micro-channel plate gating circuits,
`
`charging circuits for battery backup of equipment for recording test data, and analog oscilloscope
`
`electronics.
`
`9.
`
`My work during this time, as one example, had a direct impact on my doctoral
`
`research work using power MOSFETs, subsequent publishing efforts, and industry designs. In
`
`addition to the 2000 Best Paper Award from the IEEE Power Electronics Society, I published several
`
`other papers in related areas while working in industry. I hold a patent, Patent No. 5,874,830, in
`
`the area of power supply design, titled, “Adaptively biased voltage regulator and operating
`
`method,” which was issued on February 23, 1999. I have designed dozens of linear and switching
`
`power supplies for commercial products and scientific instrumentation.
`
`10.
`
`I am a licensed Professional Engineer and have extensive industry experience in
`
`circuit design, fabrication, and manufacture of Dynamic Random Access Memory (DRAM)
`
`semiconductor integrated circuit chips, Phase-Change Random Access Memory (PCRAM) chips,
`
`and CMOS Image Sensors (CISs) at Micron Technology, Inc. (“Micron”) in Boise, Idaho. I spent
`
`considerable time working on the development of Flash memory chips while at Micron. My efforts
`
`resulted in more than a dozen patents relating to Flash memory. One of my projects at Micron
`
`included the development, design, and testing of circuit design techniques for a multi-level cell
`
`(MLC) Flash memory using signal processing. Another project focused on the design of buffers
`
`for high-speed double-data rate DRAM which resulted in around 10 US patents in buffer design.
`
`Among many other experiences, I led the development of the delay locked loop (DLL) in the late
`
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`1990s so that Micron DRAM products could transition to the DDR memory protocol for
`
`addressing and controlling accesses to memory via interprocess communications (IPC) with the
`
`memory controller (MC). I provided technical assistance with Micron’s acquisition of Photobit
`
`during 2001 and 2002, including transitioning the manufacture of CIS products into Micron’s
`
`process technology. Further, I did consulting work at Sun Microsystems and then Oracle on the
`
`design of memory modules during 2009 and 2010. This work entailed the design of low-power,
`
`high-speed, and wide interconnection methods with the goal of transmitting data to/from the
`
`memory module and the MC at higher speeds.
`
`11.
`
`I have extensive experience in the development of instrumentation and commercial
`
`products in a multitude of areas including: integrated electrical/biological circuits and systems,
`
`array (memory, imagers, and displays) circuit design, CMOS analog and digital circuit design,
`
`diagnostic electrical and electro-optic instrumentation for scientific research, CAD tool
`
`development and online tutorials, low-power interconnect and packaging techniques, design of
`
`communication/interface circuits (to meet commercial standards such as USB, firewire, DDR,
`
`PCIe, SPI, etc.), circuit design for the use and storage of renewable energy, and power electronics.
`
`For example, a part of my research at Boise State, for many years, focused on the use of Thru-
`
`Silicon-Vias (TSVs), aka Thru-Wafer Vias (TWVs), for high-density packaging. These packaging
`
`techniques were utilized in the memory module development work I did with Sun Microsystems
`
`and Oracle. As another example, I’ve designed circuitry for use in implementing Universal Serial
`
`Bus (USB) interfaces circuits while I did consulting at Tower Semiconductor. I designed PCI
`
`communication circuits for IPC between a Graphics Processor Unit (GPU) and memory while
`
`consulting for Rendition, Inc.
`
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`12. My current research work is focused in part on the design of integrated circuits for
`
`wireless sensing using LIDAR (LIght Detection And Ranging). I have worked with several
`
`companies in the development of these circuits and systems including Freedom Photonics, Aerius
`
`Photonics, and FLIR. In the early 1990s I worked on wireless systems for wideband impulse radar
`
`while at Lawrence Livermore Laboratory. Further, part of my research for several years focused
`
`on the digitization of wireless IQ channels using delta-sigma modulation. The knowledge and
`
`experience gained from this effort are reflected in my textbook CMOS Mixed-Signal Circuit
`
`Design and a presentation, http://cmosedu.com/jbaker/papers/talks/BP_DSM_talk.pdf, which I
`
`have presented at several universities and companies.
`
`B.
`
`13.
`
`Academic Experience
`
`I was an adjunct faculty member in the Electrical Engineering department of the
`
`University of Nevada, Las Vegas in 1991 and 1992. From 1993 to 2000, I served on the faculty
`
`at the University of Idaho as an Assistant Professor and then as a tenured Associate Professor of
`
`Electrical Engineering. In 2000, I joined a new Electrical and Computer Engineering program at
`
`Boise State University (“BSU”) where I served as department chair from 2004 to 2007. At BSU,
`
`I helped establish graduate programs in Electrical and Computer Engineering including, in 2006,
`
`the university’s second Ph.D. degree. In 2012, I re-joined the faculty at UNLV. Over the course
`
`of my career as a professor I have advised over 90 masters and doctoral students.
`
`14.
`
`I have been recognized for my contributions as an educator in the field. While at
`
`Boise State University, I received the President’s Research and Scholarship Award (2005),
`
`Honored Faculty Member recognition (2003), and Outstanding Department of Electrical
`
`Engineering Faculty recognition (2001). In 2007, I received the Frederick Emmons Terman Award
`
`(the “Father of Silicon Valley”). The Terman Award is bestowed annually upon an outstanding
`
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`young electrical/computer engineering educator in recognition of the educator’s contributions to
`
`the profession. In 2011 I received the IEEE Circuits and Systems Education Award. I received
`
`the Tau Beta Pi Outstanding Electrical and Computer Engineering Professor Award many of the
`
`years it was awarded while I have been back at UNLV.
`
`15.
`
`I have authored several books and papers in the electrical and computer engineering
`
`area. My published books include CMOS Circuit Design, Layout, and Simulation (Baker, R.J.,
`
`Wiley-IEEE, ISBN: 978-0470881323 (3rd ed., 2010)) and CMOS Mixed-Signal Circuit Design
`
`(Baker, R.J., Wiley-IEEE, ISBN: 978-0470290262 (2nded., 2009) and ISBN: 978-0471227540 (1st
`
`ed., 2002)). I co-authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth,
`
`B., Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 978-0-470-18475-2 (2008)), DRAM
`
`Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE, ISBN: 0-7803-6014-1 (2001)),
`
`and CMOS Circuit Design, Layout and Simulation (Baker, R.J., Li, H.W., and Boyce, D.E., Wiley-
`
`IEEE, ISBN: 978-0780334168 (1998)). I contributed as an editor and co-author on several other
`
`electrical and computer engineering books.
`
`C.
`
`16.
`
`Other Relevant Experience
`
`I have given more than 50 invited talks at conferences, companies, and Universities.
`
`Further, I am the author and co-author of more than 100 papers and presentations in the areas of
`
`electrical and computer engineering design, fabrication and packaging.
`
`17.
`
`I currently serve, or have served, as a volunteer on: the IEEE Press Editorial Board
`
`(1999-2004); as editor for the Wiley-IEEE Press Book Series on Microelectronic Systems (2010-
`
`2018); as the Technical Program Chair of the 2015 IEEE 58th International Midwest Symposium
`
`on Circuits and Systems (MWSCAS 2015); on the IEEE Solid-State Circuits Society (SSCS)
`
`Administrative Committee (2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015);
`
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`and as the Technology Editor (2012-2014) and Editor-in-Chief (2015-2020) for the IEEE Solid-
`
`State Circuits Magazine. These meetings, groups, and publications are intended to allow
`
`researchers to share and coordinate research. My active participation in these meetings, groups,
`
`and publications allowed me to see what other researchers in the field have been doing.
`
`18.
`
`In addition to the above, I am an IEEE Fellow for contributions to memory circuit
`
`design and a member of the honor societies Eta Kappa Nu and Tau Beta Pi.
`
`19. My CV is attached to this declaration as Appendix B.
`
`II.
`
`LEGAL PRINCIPLES
`
`A.
`
`20.
`
`Claim Construction
`
`I have been informed by Counsel that in performing my analysis and forming my
`
`opinions, I should apply the claim constructions adopted by the Court in this matter, as well as any
`
`constructions agreed to by the parties. For all other claim terms, I have been informed that I should
`
`apply the plain and ordinary meaning that one of ordinary skill in the art would have given to each
`
`claim term as of the respective priority date of each Asserted Patent.
`
`21.
`
`I have been informed and understand that the preamble of a Jepson claim—that
`
`portion before language preceding language such as “wherein the improvement comprises”—is
`
`admittedly prior art.
`
`B.
`
`22.
`
`Invalidity
`
`I have been informed by counsel that a patent issued by the U.S. Patent and
`
`Trademark Office is entitled to a presumption of validity, which may be overcome by clear and
`
`convincing evidence of facts that support the ultimate conclusion of invalidity. Counsel has also
`
`informed me that the standards described below are used to determine invalidity. I have applied
`
`these standards to guide my analysis.
`
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`23.
`
`Counsel has also informed me that, for purposes of this report, the publications,
`
`patents, and products cited herein qualify as prior art to the Asserted Patents.
`
`1.
`
`Anticipation
`
`24.
`
`I have been informed that a patent claim must be novel to be valid. A claim that
`
`lacks novelty is invalid.
`
`25.
`
`Counsel has informed me that because the patents-in-suit were filed prior to the
`
`effective date of the America Invents Act (AIA), pre-AIA 35 U.S.C. section 102 applies.
`
`26.
`
`Counsel has informed me that a patent claim is “anticipated” and therefore invalid
`
`under 35 U.S.C. section 102, if, among other things, (a) the alleged invention was known or used
`
`by others in this country, or patented or described in a printed publication in the United States or
`
`a foreign country, before the alleged invention thereof by the patent's applicant(s), or (b) the
`
`alleged invention was patented or described in a printed publication in this or a foreign country or
`
`in public use or on sale in this country, more than one year prior to the date of the application for
`
`patent in the United States, or (e) the invention was described in a patent granted on an application
`
`for patent by another filed in the United States before the invention by the applicant for patent. I
`
`understand that the date one year prior to the filing of a patent application is referred to as the
`
`“critical date.”
`
`27.
`
`Counsel has also informed me that a patent claim may be invalid under 35 U.S.C.
`
`section 102(g)(2) if, before the patentee’s invention thereof, the invention was made in the United
`
`States by another inventor who had not abandoned, suppressed, or concealed it.
`
`28.
`
`Counsel has also informed me that references or products that fall into one or more
`
`of these categories are called “prior art,” and that to anticipate a patent claim pursuant to 35 U.S.C.
`
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`section 102, a single reference must contain all of the elements and limitations described in the
`
`claim either expressly or inherently.
`
`29.
`
`Counsel has informed me that in deciding whether a single item of prior art
`
`anticipates a patent claim, one should consider what is expressly stated or present in the piece of
`
`prior art, and what is inherently present. I understand that something is inherent in an item of prior
`
`art if it is always present in the prior art or always results from the practice of the prior art. It is
`
`my understanding that one of ordinary skill in the art may not have recognized the inherent
`
`characteristics or functioning of the prior art at the time.
`
`2.
`
`Obviousness
`
`30.
`
`Counsel has informed me that because the patents-in-suit were filed prior to the
`
`effective date of the America Invents Act (AIA), pre-AIA 35 U.S.C. section 103 applies.
`
`31.
`
`Counsel has informed me that a patent claim is “obvious” and therefore invalid
`
`under 35 U.S.C. section 103 if the claimed subject matter would have been obvious to a person of
`
`ordinary skill in the art as of the priority date of the patent based upon one or more prior art
`
`references. I understand that an obviousness analysis must consider: (1) the scope and content of
`
`the prior art; (2) the differences between the claims and the prior art; (3) the level of ordinary skill
`
`in the pertinent art; and (4) secondary considerations, if any, of non- obviousness (such as
`
`unexpected results, commercial success, long-felt but unsolved needs, failure of others, copy by
`
`others, licensing, and skepticism of experts). Secondary indicia of non-obviousness may include
`
`a long felt but unmet need in the prior art that was satisfied by the invention of the patent;
`
`commercial success covered by the patent; unexpected results achieved by the invention; praise of
`
`the invention by others skilled in the art; taking of licenses under the patent by others; and
`
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`deliberate copying of the invention. Even assuming such indicia exists, it is my understanding that
`
`there must be a nexus between any such secondary indicia and the claimed invention.
`
`32.
`
`Counsel has informed me that a conclusion of obviousness may be based upon a
`
`combination of prior art references, particularly if the combination of elements does no more than
`
`yield predictable results. I understand that a patent composed of several elements is not proved
`
`obvious merely by demonstrating that each of its elements was, independently, known in the prior
`
`art. Moreover, I understand that it can be important to identify a reason that would have prompted
`
`a person of ordinary skill in the relevant field to combine the elements in a way the claimed new
`
`invention does. I further understand that to determine obviousness the courts look to the
`
`interrelated teachings of multiple patents, the effects of demands known to the design community
`
`or present in the marketplace, and the background knowledge possessed by a person having
`
`ordinary skill in the art.
`
`33.
`
`Counsel has informed me that in determining whether a combination of prior art
`
`references renders a claim obvious, it is helpful to consider whether there is some teaching,
`
`suggestion, or motivation to combine the references and a reasonable expectation of success in
`
`doing so. I understand, however, that the teaching, suggestion, or motivation to combine inquiry
`
`is not required and may not be relied upon in lieu of the four obviousness factors outlined above.
`
`3.
`
`Written Description and Enhancement
`
`34.
`
`I have been informed and understand that a patent application must describe the
`
`invention sufficiently to convey with reasonable clarity to those skilled in the art that, as of the
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`filing date sought, the applicant was in possession of the claimed invention. I understand that the
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`invention is, for purposes of the written description inquiry, defined by the claim. I am informed
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`that the subject matter of the claim need not be described using language identical to that in the
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`IPR2021-00599
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`claim in order for the disclosure to satisfy the description requirement, but the description must do
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`more than merely disclose that which would render the claimed invention obvious. I understand
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`that this is referred to as the "written description" requirement.
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`35.
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`I have been informed and understand that the test for determining compliance with
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`the written description requirement is whether or not the disclosure found within the four corners
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`of a patent's specification, (using words, structures, figures, diagrams and formulas) reasonably
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`conveys to those of ordinary skill in that art associated with the patent that the inventor(s) did, in
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`fact, have possession of the full scope of the invention at the time of the application. To do that,
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`the specification contained within an issued patent must describe each and every claimed
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`invention, doing so in detail sufficient to enable one of ordinary skill in the art to conclude that the
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`inventor(s) actually invented the claimed invention. Such a specification complies with the written
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`description requirement if it adequately and clearly describes such invention through the use of
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`descriptive means such as text and figures which set forth the fully claimed scope of each such
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`invention.
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`36.
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`I am informed that to satisfy the enablement requirement, the disclosure of the
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`specification must provide sufficient teaching such that one skilled in the art could make and use
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`the full scope of the invention as claimed without undue experimentation. I understand that a
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`patent claim is not necessarily invalid for lack of enablement if one must engage in some
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`experimentation. But, while a specification need not disclose what is well known in the art, simply
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`proposing an idea or a goal for future invention does not constitute an enabling disclosure. A
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`patentee cannot simply rely on the knowledge of a person of ordinary skill to serve as a substitute
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`for information missing from the specification.
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`37.
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`I am informed that the enablement requirement serves two functions: (1) ensuring
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`adequate disclosure of the claimed invention, and (2) preventing claims broader than the disclosed
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`invention. I understand that this doctrine prevents both inadequate disclosure of an invention and
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`overbroad claiming that might otherwise attempt to cover more than was actually invented.
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`Therefore, I am informed that a patentee chooses broad claim language at the peril of losing any
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`claim that cannot be enabled across its full scope of coverage. I understand that the purpose is so
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`that the scope of the claims is less than or equal to the scope of the enablement to ensure that the
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`public knowledge is enriched by the patent specification to a degree at least commensurate with
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`the scope of the claims.
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`4.
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`Definiteness
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`38.
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`I have been informed and understand that, to satisfy the "definiteness" requirement,
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`the patent statute requires that a claim particularly point out and distinctly claim the subject matter
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`which the applicant regards as his invention. I have been informed and understand that determining
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`whether a claim is definite requires an analysis of whether one of ordinary skill in the art—at the
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`time the patent was filed—would understand the bounds of the claim when read in light of the
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`specification and prosecution history.
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`39.
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`I understand that whether a claim is definite is to be evaluated from the perspective
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`of a person of ordinary skill in the art at the time of the alleged invention. I have been informed
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`and understand that the inquiry requires an analysis of how a person of ordinary skill understands
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`the claims, and even if it is difficult to discern and the conclusion may be one over which
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`reasonable people disagree, it may still be sufficiently clear. Further, I have been