(12) United States Patent
`Howard et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,708,278 B2
`Mar.16,2004
`
`I 1111111111111111 11111 111111111111111 1111111111 1111111111 111111111111111111
`US006708278B2
`
`(54) APPARATUS AND METHOD FOR
`AWAKENING BUS CIRCUITRY FROM A
`LOW POWER STATE
`
`(75)
`
`Inventors: Brian D. Howard, Portola Valley, CA
`(US); Michael F. Culbert, San Jose,
`CA (US); Robert Bailey, La Selva
`Beach, CA (US)
`
`(73) Assignee: Apple Computer, Inc., Cupertino, CA
`(US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 10/210,734
`
`(22) Filed:
`
`Jul. 31, 2002
`
`(65)
`
`Prior Publication Data
`
`US 2003/0014677 Al Jan. 16, 2003
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 09/340,762, filed on Jun.
`28, 1999, now Pat. No. 6,460,143.
`
`(51)
`Int. CI.7.................................................. G06F 1/26
`(52) U.S. Cl........................................................ 713/323
`(58) Field of Search.. ……..…………..……… 713/300, 310,
`713/320, 323, 324, 340
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,471,625 A * 11/1995 Mussemann et al. …….713/322
`
`5,557,777 A
`9/1996 Culbert
`2/1997 Culbert
`5,600,841 A
`1/1998 Culbert
`5,708,816 A
`9/1998 Broedner et al.
`5,812,796 A
`6,105,097 A * 8/2000 Larky et al. …………….713/324
`6,119,194 A * 9/2000 Miranda et al. ………… 713/310
`5/2001 Nakaoka et al.
`6,230,277 Bl
`6,272,644 Bl * 8/2001 Urade et al. …………….713/320
`6,308,278 Bl * 10/2001 Khouli et al.. ………..… 713/323
`6,460,143 Bl * 10/2002 Howard et al. ………….713/323
`6,567,921 Bl * 5/2003 Guziak. …………..…… ..713/322
`6,601,178 Bl * 7/2003 Gulick. …………..…… ..713/322
`OTHER PUBLICATIONS
`
`"Universal Serial Bus Specification", Revision 1.0, Jan. 15,
`1996.
`* cited by examiner
`Primary Examiner----Glenn A. Auve
`(74) Attorney, Agent, or Firm---Beyer Weaver & Thomas,
`LLP
`
`(57)
`
`ABSTRACT
`
`Apparatus and techni aratus and techniques for awakening bus circuitry from
`
`an inactive state as needed are described. The bus circuitry
`forms part of a computer system and is placed in the inactive
`state (i.e., shut down) when not needed so as to conserve
`power. The bus circuitry is associated with a bus and can be
`awakened out of the inactive state when certain bus events,
`including resume, connect or disconnect, occur on the bus.
`The invention is particularly advantageous for computing
`devices (e.g., portable computers, desktop computers, server
`computers) where it is desirous to shut down bus circuitry as
`well as other circuitry (e.g., microprocessor) when not
`needed so as to reduce power consumption.
`
`15 Claims, 10 Drawing Sheets
`
`200/
`
`USB
`PORT
`
`214_1
`
`Vbus
`
`VD+ rl
`
`212
`
`USB
`HOST
`CONTROLLER
`
`VD-
`
`GND
`
`PCIBUS
`216_1
`丿 NTROLLER
`
`口p
`
`I__J13Q
`
`USB
`WAKEUP
`CIRCUIT
`
`222
`
`MICROPROCESSOR
`
`POWER
`MANAGER
`
`INTERRUPT
`CONTROLLER
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 1 of 20
`
`

`

`B2
`
`6,708,278
`
`US
`
`10
`of
`1
`
`Sheet
`
`Mar.16,2004
`
`Patent
`
`U.S.
`
`1
`
`FIG.
`
`118
`
`CIRCUIT
`
`USB WAKEUP
`
`108
`
`MICROPROCESSOR
`
`104
`
`109
`
`12
`
`120
`
`CIRCUITRY
`PERIPHERAL
`
`INTERFACE
`BUS
`PERIPHERAL
`USB
`
`/ 100
`
`CNTLR
`HOST
`USB
`
`115
`
`116
`
`102
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 2 of 20
`
`

`

`B2
`8
`
`8,27
`
`6,70
`
`us
`
`10
`of
`2
`
`Sheet
`
`上
`
`Mar.16,200
`
`Patent
`
`U.S.
`
`CONTROLLER
`INTERRUPT
`
`MANAGER
`
`POWER
`
`MICROPROCESSOR
`
`200/
`
`FIG. 2
`
`PCI PORT
`
`CONTROLLER
`
`PCIBUS
`
`IRQ.
`
`WKUP
`
`222
`
`CIRCUIT
`WAKEUP
`
`USB
`
`CONTROLLER
`
`HOST
`USB
`
`212
`
`GND
`
`VD-
`
`VD+
`
`Vbus
`
`PORT
`USB
`
`214
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 3 of 20
`
`

`

`B2
`
`,708,278
`6
`
`us
`
`10
`of
`3
`
`Sheet
`
`04
`
`6,20
`1
`
`Mar.
`
`Patent
`.
`u.s
`
`324
`
`Register
`Wakeup
`
`Bit
`
`302
`
`3
`
`FIG.
`
`Register
`Enable
`
`Bit
`
`s
`
`IRQ
`
`\1)
`6 2erBrt
`
`3thSo
`
`OUp (\
`
`WKUP
`
`310
`
`300 \
`
`VD-
`
`VD+
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 4 of 20
`
`

`

`B2
`
`6,708,278
`
`US
`
`10
`of
`4
`
`Sheet
`
`Mar.16,2004
`
`Patent
`
`U.S.
`
`LINES
`READ
`EVENT
`
`LINES
`SELECT
`
`BIT
`
`REGISTER
`
`ENABLE
`
`ICS
`~04
`
`CIRCUIT
`
`DISCONNECT
`
`ENABLE
`
`FIG. 4
`
`STORAGE
`CONDITION
`INITIAL BUS
`
`GENERATOR
`
`SIGNAL
`WAKEUP
`
`418
`
`DES
`
`416
`
`CIRCUIT
`CONNECT
`ENABLE
`
`CES
`
`414
`
`CIRCUIT
`RESUME
`ENABLE
`
`RES
`
`400
`
`f
`
`412
`
`DETECTOR
`
`EVENT
`
`DISCONNECT
`
`DETECTOR
`
`EVENT
`
`CONNECT
`
`DETECTOR
`
`RESUME EVENT
`
`VD-
`
`VD+
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 5 of 20
`
`

`

`U.S. Patent
`
`Mar.16,2004
`
`Sheet 5 of 10
`
`US 6,708,278 B2
`
`;- -
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -...............-....-......- ·一．．．．．一．．．．．一．．一一一一一飞
`
`;
`:
`:
`
`I
`
`RES
`
`l
`
`502
`
`RESUME
`REGISTER
`BIT
`
`514
`
`:
`, :
`}
`!
`
`500
`~ : :
`(418)
`
`RESUME
`SELECT
`REGISTER
`
`I 508
`
`CES
`
`I 504
`
`CONNECT
`REGISTER
`BIT
`
`516
`
`CONNECT
`SELECT
`REGISTER
`
`DES
`
`DISCONNECT I 506
`REGISTER
`BIT
`
`518
`
`DISCONNECT
`SELECT
`REGISTER
`
`I S12
`
`(OTHER USB PORTS)
`524
`
`lWKUP-IRQ ;
`WKUP-PCI
`------····-----------------------------------·-------·-·•---·一一．．．．．．．．．．＿ _ _ ＿．．．一＇
`
`FIG. 5
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 6 of 20
`
`

`

`B2
`
`6,708,278
`
`US
`
`10
`of
`6
`
`Sheet
`
`Mar.16,2004
`
`Patent
`
`U.S.
`
`FIG. 6A
`
`616
`
`(412}
`
`/ 600
`
`VD
`
`VD+
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 7 of 20
`
`

`

`U.S. Patent
`
`Mar.16,2004
`
`Sheet 7 of 10
`
`US 6,708,278 B2
`
`ERS1
`
`ERS2 / 650
`
`(406)
`
`656
`
`DES
`
`IC+
`
`IC-
`
`ES
`
`FIG. 6B
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 8 of 20
`
`

`

`B2
`
`ES
`
`DES
`
`DS
`
`7B
`
`FIG.
`
`6,708,278
`
`US
`
`10
`of
`8
`
`Sheet
`
`Mar.16,2004
`
`Patent
`
`U.S.
`
`FIG. 7A
`
`ECS
`
`(408)
`
`/ 750
`
`718
`
`VD-
`
`VD+
`
`芯＼
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 9 of 20
`
`

`

`U.S. Patent
`
`Mar.16,2004
`
`Sheet 9 of 10
`
`US 6,708,278 B2
`
`8 0~
`
`VD+
`VD-
`
`Q I DES
`
`EDS
`
`FIG. BA
`
`850
`
`/
`
`ES
`
`IC+
`
`IC-
`
`FIG. BB
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 10 of 20
`
`

`

`B2
`
`6,708,278
`
`US
`
`10
`of
`10
`
`Sheet
`
`9
`
`FIG.
`
`ERS2
`
`D
`
`628
`
`624
`
`Mar.16,2004
`
`634
`
`/ 900
`
`Patent
`
`U.S.
`
`610
`
`614
`
`VD-
`
`VD+
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 11 of 20
`
`

`

`1
`
`US 6,708,278 B2
`
`2
`
`APPARATUS AND METHOD FOR
`AWAKENING BUS CIRCUITRY FROM A
`LOW POWER STATE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`BACKGROUND OF THE INVENTION
`
`This application is a continuation application which
`claims the benefit of priority from U.S. application Ser. No.
`09/340,762, filed Jun. 28, 1999 now U.S. Pat. No. 6,460,143
`and entitled "APPARATUS AND METHOD FOR AWAK- 10
`ENING BUS CIRCUITRY FROM A LOW POWER
`STATE," the content of which is hereby incorporated by
`reference in its entirety
`·
`-
`·
`
`logical devices, while other information is specific to the
`functionality provided by the device. Before a peripheral
`device can be used, it must be configured by the host. This
`configuration includes allocating USE bandwidth and
`s selecting function specific configuration options. Examples
`of functions provided by peripheral devices include: locator
`devices such as a mouse, tablet, or light pen; input devices
`such as a keyboard; output devices such as a printer or
`scanner; and telephony adapters such as an ISDN adapter
`The USE specification also covers power management
`aspects. Each USE segment provides a limited amount of
`~~)':'_er _over the_ cable. T~e h~st supplies ~ower_ for use ~y
`USE. devices_ thitt are. directly. connected to the host. In
`add山on, any USE device may have its own power supply
`15 USE devices that rely totally on the power from the cable are
`called bus-powered devices. In contrast, those USE devices
`1. Field of the Invention
`that have an alternate source of power are called self(cid:173)
`The p resent invention relates to computer systems and,
`powered devices.
`more particularly, to bus control for computer systems.
`A USE host has a power management system which is
`20 independent from that- of USE. The USE system software
`2. Description of the Related Art
`interacts with the host's power management system to
`Computer systems typically include a bus over which data
`handle system power events such as Suspend or Resume. In
`and control signals are exchanged with peripheral devices.
`particular, USE allows the host computer to command
`These buses are often categorized as either parallel buses or
`serial buses. Parallel buses include multiple data lines, _ _ connected USE devices to enter a low-power Suspend state.
`whereas serial buses include a single data line (or a differ- 25 A suspended full-speed device pulls th~ VD+ dat~ line high,
`ential pair of lines). Examples of parallel buses are Interface
`while the host's pull-down resistor to ground pulls the VD-
`Standard Association (ISA) and Peripheral Component
`data line low. S皿larly, a suspended low-speed device pulls
`Interface (PCI). Examples of serial buses are Apple Desktop
`the VD- line high, while the host's pull-down resistor to
`Eus (ADE), Access.bus, IEEE P1394, Concentration High-
`__ ground pulls the USE VD+ data line low. The state of the
`30 USE b us when a suspended device is connected is also
`way Interface (CHI), and GeoPort.
`Recently, a serial bus known as Universal Serial Eus
`called the Idle state. When a suspended device experiences
`(USB) has been developed USB lS an mdustry standard
`a wakeup event (such as a key press, modem nng detect,
`etc.), it generates a Resume event by driving the low data
`extension to the personal computer architecture with a focus
`on Computer Telephony Integration (CTI), consumer and 00 line high and driving the high data line low. Normally, the
`35
`productivity applications. The USE is described in a Uni-
`J J host computer's USE c订cuitry detects the Resume event,
`versal Serial Eus Specification, Revision 1.0, dated Jan. 15,
`and resumes normal USE communication with the device.
`1996, which is hereby incorporated by reference.
`When a device is unplugged from a USE port, the host
`USE is a cable bus that supports data exchange between
`computer's pull-down resistors cause both data lines to be
`a host computer and a wide range of simultaneously acces- 40 pulled low. The host computer's USE c订cuitry detects this
`· · as a disconnect event. If a device is later plugged into the
`sible peripherals. The USE bus is a four wire bus, with a
`power hne (Vbus), a ground hne (GND), and two data hnes
`port, the dewce pulls one of the data hnes hlgh The
`(VD+ and VD-). Data is transmitted over the data lines in
`particular one of the data lines pulled high depends on
`a differential manner. The peripherals attached to a USE
`whether it is a full-speed or a low-speed device. The host
`share the bandwidth of the USE through a host scheduled 45 computer's USE circuitry detects this connect event, and
`·· begins USE communication with the device.
`token based protocol. The USE specification allows periph-
`However, all of these operations require the host com-
`erals to be attached, configured, used and detached while the
`puter's USE c订cuitry to be awake (powered and clocked) at
`host and other peripherals are in operation. Such is often
`referred to as dynamic (or hot) attachment and removal.
`all times, in order to detect resume, disconnect or connect
`A USE bus connects USE devices with a USE host. A host so events. In many cases, especially in portable computers or
`controller interfaces the USE bus to the host computer
`other battery-powered devices, it is desirable to shut down
`system. The host controller may be implemented in a
`the USE circuitry (stop its clocks and possibly turn off its
`combination of hardware, firmware or software. The USE
`power) when it is not needed so as to reduce the host
`host interacts with the USE devices through the host con-
`computer's power consumption. For example, this might
`troller. The host and its associated host controller are respon- 55 occur when the host computer is in a sleep state, or when no
`sible for managing the use of the USE. Specifically, the host
`USE devices are presently connected to the host computer
`is responsible for detecting the attachment and removal of
`Although such power management advantageously reduces
`USE devices, managing control flow between the host and
`power consumption and thus extends battery life, a serious
`USE devices, managing data flow between the host and USE
`problem is presented because these bus events (resume,
`devices, collecting status and activity statistics, and provid- 60 connect and disconnect) are not able to be detected when the
`host computer's USE circuitry has been shut down. This
`ing a limited amount of power to attached USE devices.
`problem leads to improper operation of the host computer,
`USE devices are peripheral devices that add additional
`functionality to the host computer. The types of functionality
`namely, unresponsiveness to bus events, and thus user
`provided by the USE devices varies widely. To assist the
`dissatisfaction
`USE host in identifying and configuring USE devices, each 65
`Thus, there is a need for improved bus control such that
`US~ de"_ice can:i~s a~~ repor~s configur~t~on related info~:
`p~rip?era~ de~ic~s ca~ ut~lize _a bus ~ven though the host bus
`mation. Some of the information reported is common to all
`circuitry for the bus is shut down for power management
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 12 of 20
`
`

`

`3
`
`US 6,708,278 B2
`
`4
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`a current bus state of the bus using the bus monitor circuit
`SUMMARY OF THE INVENTION
`to detect certain bus events occurring on the bus, the certain
`Broadly speaking, the invention relates to apparatus and
`bus events being detected based on the initial bus state and
`;"""tiuP
`techniques for awakening bus circuitry from an inactive
`the current bus state; and awakening the bus controller when
`state as needed. The bus circuitry forms part of a computer
`system and is placed in the inactive state (i.e., shut down) s at least one of the certain bus events are detected.
`when not needed so as to conserve power. The bus circuitry
`The advantages of the invention are numerous. Different
`is associated with a bus and can be awakened out of the
`embodiments or implementations may have one or more of
`inactive state when certain bus events, including resume,
`the following advantages. One advantage of the invention is
`connect or disconnect, occur on the bus. The invention is
`that bus events invoked on a bus by a peripheral device are
`particularly advantageous for battery-powered computing 10 able to be noticed and responded to even though bus
`devices (e.g., portable computers) where it is desirous to
`circuitry is shut down (i.e., inactive state). Another advan-
`shut down bus circuitry as well as other circuitry (e.g.,
`tage of the invention is that power management can be had
`microprocessor) when not needed so as to reduce power
`for bus circuitry without loss of important bus events while
`the bus circuitry is shut down. Still another advantage of the
`consumption.
`The invention can be implemented in numerous ways, 15 invention is that resistance to noise present on the bus is
`provided so that bus events are not erroneously detected. Yet
`including as a system, a device, an apparatus, and a method
`another advantage of the invention is that the particular type
`;7,,.rl
`Several embodiments of the invention are summarized
`of event inducing the awakening of the bus circuitry can be
`below.
`made known to the computer system (e.g., operating
`As a computer system, one embodiment of the invention
`in~ludes: a me1:1ory for ~tori~g. at leas_t instruct~o_ns;. a 20 system).
`microprocessor for processing the instructions stored in the
`Other aspects and advantages of the invention will
`memory, the microprocessor having an active state and a
`become apparent from the following detailed description,
`sleep state; a peripheral bus; a bus host controller for
`taken in conjunction with the accompanying drawings,
`managing data transfer over the peripheral bus, the bus host "'illustrating by way of example the principles of the inven-
`25.
`controller having an operational mode and a shut-down ~" hon.
`mode, the shut-down mode providing power savings; and a
`wakeup circuit operatively connected to the peripheral bus,
`The present invention will be readily understood by the
`the wakeup circuit operates to detect bus events on the
`peripheral bus when the bus host controller is in the shut- 30 following detailed description in conjunction with the
`down mode and to initiate awakening of the host bus
`accompanying drawings, wherein like reference numerals
`controller to the operational mode when bus events have
`designate like structural elements, and in which
`been detected.
`FIG. 1 is a block diagram of a computer system according
`As a computer system, another embodiment of the inven-
`to one embodiment ofthe invention;
`tion includes: a memory for storing at least instructions; a
`FIG. 2 is a block diagram of a computer system according
`microprocessor for processing the instructions stored in the
`to another embodiment of the invention;
`memory; a power manager for managing power consump-
`FIG. 3 is a schematic diagram of a bus wakeup circuit
`tion of the computer system; a peripheral bus; a bus host
`according to one embodiment of the invention;
`controller for managing data transfer over the peripheral bus,
`FIG. 4 is a block diagram of a bus wakeup circuit
`the bus host controller being shut-down when the peripheral 40
`bus is not needed; and a wakeup circuit operatively con-
`·- according to another embodiment of the invention;
`nected to the peripheral bus, the wakeup circuit operates to
`FIG. 5 is a schematic diagram of a wakeup signal gen-
`detect bus events on the peripheral bus when the bus host
`erator according to one embodiment of the invention;
`controller is shut~down and to in山ate awakening of the host
`FIG. 6Ais a schematic diagram of a resume event detector
`bus controller when bus events have been detected.
`45 according to one embodime~t of the invention;
`As a wakeup circuit for awakening a bus controller from
`FIG. 6B is a schematic diagram of an enable resume
`a low-power mode, where the bus controller controls com-
`"ir"";
`circuit according to one embodiment of the invention;
`munications with a bus, an embodiment of the invention
`FIG. 7A is a schematic diagram of a connect event
`::;:~-·;
`includes: an initial bus condition store that stores in山al
`:_:::;:·;:
`detector according to one embodiment of the invention;
`conditions residing on the bus when the wakeup circuit is 50
`FIG. 7B is a schematic diagram of an enable connect
`activated; and event detection circuitry that detects at least
`circuit according to one embodiment of the invention;
`one type of bus event on the bus based on current bus
`conditions and the initial conditions stored in the initial bus
`FIG. SA is a schematic diagram of a disconnect event
`condition store.
`detector according to one embodiment of the invention;
`A wakeup circuit for awakening a bus controller from a 55
`FIG. SB is a schematic diagram of an enable disconnect
`low-power mode, where the bus controller controls commu-
`circuit according to one embodiment of the invention; and
`nications with a bus, another embodiment of the invention
`FIG. 9 is a block diagram of a schematic diagram of a
`includes: event detection circuitry that detects at least one
`resume event detector according to another embodiment of
`type of bus event on the bus based on current bus conditions;
`the invention.
`and a wakeup signal generator that operates to produce a bus 60
`DETAILED DESCRIPTION OF THE
`wakeup signal that is used in awakening the bus controller
`INVENTION
`As a method for monitoring bus activity on a bus of a
`computing device when a bus controller for the bus is
`The invention relates to apparatus and techniques for
`awakening bus circuitry from an inactive state as needed
`inactive, an embodiment of the invention includes the opera-
`tions of: activating a bus monitor circuit when the bus 65 The bus circuitry forms part of a computer system and is
`controller becomes inactive; saving an initial bus state when
`placed in the inactive state (i.e., shut down) when not needed
`so as to conserve power. The bus circuitry is associated with
`the bus monitor circuit is activated; subsequently monitoring
`
`35
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 13 of 20
`
`

`

`5
`
`US 6,708,278 B2
`
`6
`
`computer system 200 includes a microprocessor 202, a
`a bus and can be awakened out of the inactive state when
`random access memory (RAM) 204, and a read-only
`certain bus events, including resume, connect or disconnect,
`memory (ROM) 206. The RAM 204 and the ROM 206 are
`occur on the bus. The invention is preferably implemented
`coupled to the mlCroprocessor 202 through a system bus
`as an electncal c1rcuU, wh1ch can be a separate Clrcuu or
`s 208. The microprocessor 202 executes i:1~tru~tion~ t~ ~':rE)'.
`integrated within the bus circuitry. The invention is particu-
`out operations for the computer system 200. The RAM 204
`ino- -rl.,vice,,;
`larly advantageous for battery-powered computing devices
`provides temporary data storage for use by at least the
`(e.g., portable computers) where it is desirous to shut down
`microprocessor 108. The ROM 206 typically stores pro-
`irrnnrnrPs:s:nr°\
`bus circuitry as well as other circuitry (e.g., microprocessor)
`gramming ~nstructions for use ~ith the micr?proc_essor !0~.
`when not needed so as to reduce power consumption.
`An operating system (or at least a portion thereof) is
`Embodiments of the invention are discussed below with 10
`normally stored in the RAM 204 or the ROM 206. The
`reference to FIGS.1-9. However, those skilled in the art will
`computer system 200 also includes a power manager 210
`,::::, -~::~~:
`readily appreciate that the detailed description given herein
`that manages power consumption by the computer system
`with respect to these figures is for explanatory purposes as
`200. The power manager works with the operating system in
`the invention extends beyond these limited embodiments.
`15 managing the power consumption of the computer system
`FIG. 1 is a block diagram of a computer system 100
`200. The power manager 210 can be used to power manage
`according to one embodiment of the invention. The com-
`various components of the computer system 200, including
`puter system 100 includes a computer 102 that couples to a
`the microprocessor 202, various bus controllers, and other
`peripheral device 104 via a USE bus 106. The computer 102
`subsystems within the computer system 200. The computer
`includes a microprocessor 108 that executes instructions to 20 system 200 could also be a multiprocessor system in which
`carry out operations for the computer 102. The micropro-
`case the power manager 210 could power manage a plurality
`cessor 108 couples to a system bus 109. Also coupled to the
`of microprocessors.
`system bus 109 is a random-access memory (RAM) 110, a
`Still further, the computer system 200 includes a USE
`read-only memory (ROM) 112, and a USE host controller
`host controller 212 that controls interaction with a USE bus
`114. The RAM 110 provides temporary data storage for use 25 that couples to a USE port 214. The USE bus is a serial bus
`by at least the microprocessor 108. The ROM 112 typically
`that is able to support one or more peripheral devices that
`cl~c;
`stores programming instructions for use with the micropro-
`desire to communicate with the computer system 200. The
`cessor 108 (including at least a portion of an operating
`( )
`USE bus is a four wire bus, with a power line (Vbus), a
`system). The USE host controller 114 operates to manage
`ground line (GND), and two data lines (VD+ and VD-)
`the USB bus 106 in accordance with the USB specification.
`·
`30 Data is transmitted over the data lines in a differential
`More particularly, the USE host controller 114 is used to
`manner. Eesides the USE bus, the computer system 200 also
`transmit and receive data over the USE bus 106.
`supports a PCI bus. The PCI bus is supported by a PCI bus
`The computer 102 also includes a USE port 116 and a
`controller 216 and the PCI bus couples to a PCI port 218 of
`USE wakeup circuit 118. The USE port 116 is used to couple
`the computer system 200. The USE host controller 212 and
`an internal link 115 of the USE bus 106 from the USE host 35 the PCI bus controller 216 are coupled to the system bus 208
`controller 114 to a cable carrying the USE bus 106. Accord-
`-- of the computer system 200. The ~omputer system 200 also
`ing to the USE specification, the cable for the USE bus 106
`includes an interrupt controller 220- that, when needed,
`mcludesfourW1res, two ofwh1ch carrypowersupplySlgnals
`supphes mterrupt requests to the mlCroprocessor 202 The
`and the other two carry differential data. The USE wakeup
`inte-rrupt controller 220 can also supply an interrupt request
`circuit 118 is coupled to the internal link 115 of the USE bus 40 to the power manager 210 in cases where the computer
`· - system -200 is in a shutdown state (or sleep mode)
`106 so that bus events occurring on the USE bus 106 by the
`peripheral device 104 (or other peripheral devices) can be
`The operating system (or other software) controls the
`detected when the USE host controller is shut down. In other
`overall power consumption of the computer system 220 and
`words, when the USE host controller 114 shuts down,
`uses the power manager 210 (hardware) to perform some of
`typically for power conservation reasons, the USE wakeup 45 the shutdown operations such as stopping clocks, stopping
`circuit 188 is activated to monitor the USE bus 106 for
`power, and interrupt handling. In this regard, the operating
`certain bus events that should be serviced. When such of the
`system or the power manager 210 can place various com-
`certain bus events have been detected, the USE wakeup
`n:.n,,nts: i
`ponents in a shutdown state (or sleep mode) so as to
`circuit 118 causes the USE host controller 114 to awaken. In
`conserve power. Namely, the microprocessor 202 can be
`one embodiment, the USE wakeup circuit 118 notifies the so placed in a sleep mode when its processing capab山ties are
`microprocessor 108, and then the microprocessor 108
`not needed. The operating system or the power manager 210
`together W1th an operatmg system (res1dmg m ROM ll2 or
`can also place the USB host controller 2l2 (or the PCI bus
`the RAM 110) causes the USE host controller 114 to be
`controller 216) in an inactive state (i.e., shut down) or
`awakened. Once awakened, the USE host controller 114 is
`awaken the USE host controller 212 (or the PCI bus con-
`able to service the detected bus events.
`55 troller 216) from the inactive state to the active state. In one
`The peripheral device 104 includes a USE peripheral bus
`embodiment, when the computer system 200 is to be
`interface 120 that couples to the cable carrying the USE bus
`awakened, the power manager 210 can awaken other parts
`106. The USE peripheral bus interface 120 interacts with the
`of the computer system 200 (e.g., the microprocessor 202)
`USE host controller 114 to facilitate the transfer and recep-
`and thereafter the operating system (or other software) can
`tion of data over the USE bus 106. The peripheral device 60 activate the USE host controller 212. Alternatively, the
`104 also includes peripheral circuitry 122. The peripheral
`power manager 210 could activate the USE host controller
`circuitry 122 performs a variety of difference operations
`212 as the computer system 200 is being awakened
`depending on the type of the peripheral device 104. As
`Unfortunately, when the USE host controller 212 is in the
`examples, the peripheral device 104 could be a keyboard, a
`inacti
`inactive state, events occurring on the USE bus are not able
`g
`monitor, a modem, a camera, a scanner, etc.
`65 to be detected by the USE ho-st controller 212. As a result,
`FIG. 2 is a block diagram of a computer system 200
`the computer system 200 is not able to utilize the USE bus
`according to another embodiment of the invention. The
`when the USE host controller 212 is in the inactive state.
`
`Petitioners Ex. 1025
`IPR USP 7,834,586
`Page 14 of 20
`
`

`

`7
`
`US 6,708,278 B2
`
`8
`
`is then delayed by the delay element 316 to yield the clock
`This is problematic because often peripheral devices on the
`USE bus desire to initiate communications with the USE
`signal being supplied to the clock terminal of the flip-flop
`host controller 212, and are conventionally unable to do so.
`310. A clock signal for the clock terminal of the flip-flop 312
`However, to conserve power, it is desirable to retain the USE
`is provided by AND gate 318 and delay element 320. The
`host controller 212 in the inactive stat~-~~ as to conserve s AND gate 318 receives as inputs the negative data line
`power when there ~~~o. ac_tivi!y o~ th~ USE bus, :"hen. the
`(VD-)-and the output from th~ OR gate 308. The output
`co~p~ter s~stem 2~~~}_s,in _the shutdown st~te (~r ~l,e~g
`from the AND gate 318 is then delayed by the delay elem~nt
`mode), or when no USE devices are connected to the USE
`320 to yield the clock signal being supplied to the clock
`bus.
`terminal of the flip-flop 312.
`To allow the use of the USE bus even when the USE host
`The bus wakeup c订cuit 300 also includes an OR gate 322
`10
`controller 212 is in the inactive state, the computer system,L:·:=-:~
`that receives the output signals from the output terminals of
`200 further includes a USE wakeup circuit 222. The USE
`the flip-flops 310 and 312. The output of the OR gate 322
`wakeup circuit 222 couples to the differential data lines of
`indicates whether the bus wakeup circuit 300 has detected an
`the USB bus and monitors activity on these differential d a t a .
`event on the particular bus port being monitored. More
`lines to detect bus events that should wakeup the USE host
`15 particularly, when the output of the OR gate 322 is HIGH,
`controller 212 (as well as perhaps the microprocessor 2O2 i f .
`bus wakeup is requested; whereas, when the output of the
`sleeping). When the USE wakeup circuit 222 detects such a
`OR gate 322 is LOW, bus wakeup is not requested. A
`bus event on the differential data lines, the USE wakeup
`wakeup register bit 324 can be coupled to the output of the
`circuit 222 causes the USE host controller 212 to awaken for
`OR gate 322 to provide a software access point to the output
`servicing the detected bus event. When the computer system
`200 (including the microprocessor 202) is also in the shut- 20 from the OR gate 322, namely, a bit indicating whether or
`not a wakeup request is being made. A microprocessor or
`down state (or sleep mode), the USE wakeup c订cuit 222 can
`software (e.g., operating system) can then access the wakeup
`also cause the computer system 200 to wakeup from its sleep
`register bit 324 to determine whether the particular bus
`mode (often prior to awakening the USE host controller
`associated with the bus wakeup circuit 300 is requesting the
`212).
`25 wakeup. The microprocessor or software can also clear the
`In one embodiment, the USE wakeup circuit 222 issues
`wakeup register bit 324 and any bus wakeup event that has
`either a wakeup interrupt signal to the interrupt controller
`been detected by clearing the enable register bit 302
`220 or a wakeup signal to the power manager 210. The
`The output of the OR gate 322 is also supplied to NOR
`wakeup signal is used when the computer system 200 is in
`the shutdown state and operates to tell the power manager 30 gate 326. The NOR gate 326 also receives 1出e inputs from
`other bus ports that are supported by the computer system.
`210 to wakeup the computer system 200 (including the
`In other words, for each of the bus ports provided in the
`microprocessor 202) and then the operating system (or other
`computer system, the circuitry 302-324 is repeated. In any
`software) can awaken the USE host controller 212. When
`case, the output of the NOR gate 326 can serve as a wakeup
`the microprocessor 202 is already in an active mode, the
`wakeup interrupt signal is supplied to the interrupt controller 35 request which directs the computer system to awaken the
`host bus controller.
`220 which will interrupt the microprocessor 202 to initiate
`software that awakens the USE host controller 212 and
`In one embodiment, the wakeup request is a wakeup
`services the bus event.
`interrupt request (IRQ). Further, in one embodiment, the
`FIG. 3 is a schematic diagram of a bus wakeup c订cuit 300
`?u~~ut _<:_f- th~ _N_O_R gate 326 can ~e supplied to a.. tri.-sate
`according to one embodiment