(12) United States Patent
`Phelan
`
`USOO6651134B1
`(10) Patent No.:
`US 6,651,134 B1
`(45) Date of Patent:
`Nov. 18, 2003
`
`(54) MEMORY DEVICE WITH FIXEDLENGTH
`NON INTERRUPTIBLE BURST
`
`5.936.975 A * 8/1999 Okamura .................... 714/719
`5,966,724. A * 10/1999 Ryan .......................... 711/105
`6,085,261 A * 7/2000 McIntyre, Jr. et al. ........ 710/35
`6,289,138 B1 * 9/2001. Yip et al. ................... 382/307
`(75) Inventor: Cathal G. Phelan, Mountain View, CA
`OTHER PUBLICATIONS
`(US)
`Understanding Burst Modes in Synchronous SRAMs,
`(73) Assignee: Cypress Semiconductor Corp., San
`Cypress Semiconductor Corp., Jun. 30, 1999.
`Jose, CA (US)
`* cited by examiner
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`Primary Examiner Donald Sparks
`U.S.C. 154(b) by 0 days.
`ASSistant Examiner Medhi Namazi
`(74) Attorney, Agent, or Firm-Christopher P. Maiorana,
`(21) Appl. No.: 09/504,344
`P.C.; Robert M. Miller
`y
`- - -
`9
`(22) Filed:
`Feb. 14, 2000
`(57)
`ABSTRACT
`(51) Int. Cl. ................................................. C06F 12/00
`An integrated circuit comprising a memory and a logic
`(52) U.S. CI.
`711/104; 711/105: 711/167;
`circuit. The memory may comprise a plurality of Storage
`"71/169 710/35; 365,233. 365,238.5
`elements each configured to read and write data in response
`(58) Field of Search
`s
`s 711/104-105 169
`to an internal address Signal. The logic circuit may be
`711/167; 365/233,238.5; 710/35
`configured to generate a predetermined number of the inter
`nal address Signals in response to (i) an external address
`References Cited
`Signal, (ii) a clock signal and (iii) one or more control
`Signals. The generation of the predetermined number of
`U.S. PATENT DOCUMENTS
`5,651,138 A
`7/1997 Le et al. ..................... is internal address signals may be non-interruptible.
`5,729,504 A * 3/1998 Cowles ......
`... 365/236
`5,805,928 A
`9/1998 Lee ............................. 710/35
`21 Claims, 3 Drawing Sheets
`
`(*) Notice:
`
`(56)
`
`150
`
`4-FXED-BURST READ/WRITEREADMING
`15
`155
`15s
`
`s
`
`152
`
`
`
`
`
`
`
`3.
`
`IIT III
`READ
`WRE
`READ
`
`:
`
`:
`
`i
`
`Petitioner STMicroelectronics, Inc., Ex. 1001
`IPR2021-00355, Page 1
`
`

`

`U.S. Patent
`
`Nov. 18, 2003
`
`Sheet 1 of 3
`
`US 6,651,134 B1
`
`100
`
`BURST
`ADDRESS
`countER, ADDRN
`REGISTER
`118
`
`MEMORY
`
`124
`DATA OUT
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`114
`BURSTC
`
`BURST
`COUNTER
`
`ADDRESS
`COUNTER
`REGISTER
`
`116
`ADDRINT
`
`28
`BURST CLK
`
`Petitioner STMicroelectronics, Inc., Ex. 1001
`IPR2021-00355, Page 2
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`

`

`U.S. Patent
`
`Nov. 18, 2003
`
`Sheet 2 of 3
`
`US 6,651,134 B1
`
`102'
`- - - - - - - - - - - - - - - - - - - - - - - - - - 6. a -
`34
`
`ADDREXT
`
`OADo
`
`CK
`
`ADDR INT
`
`COUNTER
`
`BURSTO
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`
`
`
`
`
`FIRST
`ADDRESS
`
`
`
`SECONO
`ADORESS
`
`THERO
`ADDRESS
`
`NH
`ADDRESS
`
`ADW =
`CLK = 1
`
`CLK = 1
`
`CLK = 1
`
`CLK = 1
`
`CLK = 1
`FIG. 4
`
`Petitioner STMicroelectronics, Inc., Ex. 1001
`IPR2021-00355, Page 3
`
`

`

`U.S. Patent
`
`Nov. 18, 2003
`
`Sheet 3 of 3
`
`US 6,651,134 B1
`
`150
`
`4-FIXED-BURST REAWREARSAO MNG
`15
`56
`158
`
`150
`
`152
`
`READ
`
`Wr
`
`REA
`
`FIG. 5A
`
`8-FXED-BURS READ/WRITEREAD IMING
`
`
`
`
`Do --- III. He
`REA
`WRE
`READ
`
`
`
`F.G. 5B
`
`162
`
`ADOR
`Da
`"E'
`
`x OXXXXXXX)
`XX
`(
`XXXXXXXXXXXXXXXXXXXX
`(XXXXX Do Xd Xoz X DX D4 X Ds). Ds X d7)
`READ X write back )
`FIG. 6
`
`
`
`Petitioner STMicroelectronics, Inc., Ex. 1001
`IPR2021-00355, Page 4
`
`

`

`1
`MEMORY DEVICE WITH FIXEDLENGTH
`NON INTERRUPTIBLE BURST
`
`US 6,651,134 B1
`
`2
`BRIEF DESCRIPTION OF THE DRAWINGS
`These and other objects, features and advantages of the
`present invention will be apparent from the following
`detailed description and the appended claims and drawings
`in which:
`FIG. 1 is a block diagram illustrating a preferred embodi
`ment of the present invention;
`FIG. 2 is a detailed block diagram illustrating a circuit 102
`of FIG. 1;
`FIG. 3 is a detailed block diagram of a circuit 102
`illustrating an alternative embodiment of the circuit 102 of
`FIG. 1;
`FIG. 4 is a flow diagram illustrating an example burst
`address Sequence;
`FIGS.5A and 5B are diagrams illustrating example opera
`tions of a 4 word (FIG. 5A) and an 8 word (FIG. 5B) fixed
`burst acceSS in accordance with the present invention; and
`FIG. 6 is a diagram illustrating an example operation
`where a burst length may be long enough to include a
`writeback and a refresh cycle.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Referring to FIG. 1, a block diagram of a circuit 100 is
`shown in accordance with a preferred embodiment of the
`present invention. The circuit 100 may be implemented, in
`one example, as a fixed burst memory. The circuit 100 may
`be configured to transfer a fixed number of words of data
`with each access (e.g., read or write). A number of words
`transferred as a group is called a burst. The circuit 100
`generally comprises a circuit 102 and a memory array (or
`circuit) 104. The circuit 102 may be implemented, in one
`example, as a burst address counter/register. The memory
`array 104 may be implemented, in one example, as a Static
`random access memory (SRAM), a dynamic random access
`memory (DRAM), or other appropriate memory to meet the
`design criteria of a particular implementation.
`The circuit 102 may have an input 106 that may receive
`a signal (e.g., ADDR EXT), an input 108 that may receive
`a signal (e.g., LOAD), an input 110 that may receive a signal
`(e.g., CLK), an input 112 that may receive a signal (e.g.,
`ADV), and an input 114 that may receive a signal (e.g.,
`BURST). The circuit 102 may have an output 116 that may
`present a signal (e.g., ADDR INT) to an input 118 of the
`memory 104. The memory 104 may have an input 120 that
`may receive a signal (e.g., R/Wb), an input 122 that may
`receive a signal (e.g., DATA IN) and an output 122 that
`may present a signal (e.g., DATA OUT). The various
`Signals are generally “on” (e.g., a digital HIGH, or 1) or
`“off” (e.g., a digital LOW, or 0). However, the particular
`polarities of the on (e.g., asserted) and off (e.g., de-asserted)
`States of the signals may be adjusted (e.g., reversed) accord
`ingly to meet the design criteria of a particular implemen
`tation.
`The signal ADDR EXT may be, in one example, an
`external address signal. The signal ADDR EXT may be
`n-bits wide, where n is an integer. The Signal CLK may be
`a clock Signal. The Signal R/Wb may be a control Signal that
`may be in a first State or a Second State. When the Signal
`R/Wb is in the first state, the circuit 100 will generally read
`data from the memory circuit 104 for presentation as the
`signal DATA OUT. When the signal R/Wb is in the second
`state, the circuit 100 will generally store data received as the
`signal DATA IN.
`The Signal LOAD may be, in one example, an address
`load control signal. The circuit 100 may be configured to
`
`FIELD OF THE INVENTION
`The present invention relates to memory devices gener
`ally and, more particularly, to a memory device that transfers
`a fixed number of words of data with each access.
`
`BACKGROUND OF THE INVENTION
`A synchronous Static Random Access Memory (SRAM)
`can provide data from multiple address locations using a
`Single address. Accessing multiple locations in response to
`a single address is called a burst mode access. A memory
`device that provides a burst mode can reduce activity on the
`address and control buses. The burst mode of a conventional
`Synchronous SRAM can be Started and Stopped in response
`to a control signal.
`A conventional Dynamic Random Access Memory
`(DRAM) preserves data during periodic absences of power
`by implementing a memory cell as a capacitor and an acceSS
`transistor. Since the charge on the capacitor will slowly leak
`away, the cells need to be “refreshed' once every few
`milliseconds. Depending on the frequency of accesses, a
`conventional DRAM can need an interrupt to perform data
`refreshes. Using a DRAM in a burst application is difficult
`because of the need to refresh. Completely hiding refresh
`cycles (e.g., refreshing data without the need for interrupts)
`in a DRAM cannot happen with conventional memory
`devices due to architecture choices that have been made.
`Data word bursts can be interrupted while in progreSS Since
`conventional architectures Support both burst and Single
`access modes. Conventional DRAM access takes about 10
`nS to get data, but nearly 20 ns to complete writeback and
`equalization. The addition of another 20 ns for a refresh
`results in a total access of 40 ns.
`Since the data burst transferS of conventional memories
`can be interrupted and Single accesses made, the amount of
`time that the data, address and control buSSes are not in use
`can vary. The variability of bus availability complicates the
`design of Systems with Shared data, address and control
`busses.
`It would be desirable to have a memory device that has a
`fixed burst length.
`SUMMARY OF THE INVENTION
`The present invention concerns an integrated circuit com
`prising a memory and a logic circuit. The memory may
`comprise a plurality of Storage elements each configured to
`read and write data in response to an internal address Signal.
`The logic circuit may be configured to generate a predeter
`mined number of the internal address Signals in response to
`(i) an external address signal, (ii) a clock signal and (iii) one
`or more control Signals. The generation of the predetermined
`number of internal address signals may be non-interruptible.
`The objects, features and advantages of the present inven
`tion include providing a fixed burst memory that may (i)
`give network customers who typically burst large data
`lengths the ability to Set a fixed burst length that Suits
`particular needs; (ii) have non-interruptible bursts; (iii) free
`up the address bus and control bus for a number of cycles,
`(iv) provide programmability for Setting the burst length by
`using DC levels IVss or Vcc on external pins; (v) hide
`required DRAM refreshes inside a known fixed burst length
`of data words, and/or (vi) operate at higher frequencies
`without needing interrupts to perform refreshes of data.
`
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`Petitioner STMicroelectronics, Inc., Ex. 1001
`IPR2021-00355, Page 5
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`

`

`US 6,651,134 B1
`
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`load an initial address, presented by the signal ADDR EXT,
`in response to the Signal LOAD. The initial address may
`determine the initial location where data transferS to and
`from the memory 104 will generally begin.
`The Signal ADV may be, in one example, used as a control
`signal. The circuit 100 may be configured to transfer a fixed
`number of words to or from the memory 104 in response to
`the signals ADV, CLK and R/Wb. When the signal ADV is
`asserted, the circuit 100 will generally begin transferring a
`predetermined number of words. The transfer is generally
`non-interruptible. In one example, the Signal ADV may
`initiate the generation of a number of addresses for presen
`tation as the signal ADDR INT.
`The signals ADV and LOAD may be, in one example, a
`single signal (e.g., ADV/LDb). The signal ADV/LDb may
`be a control Signal that may be in a first State or a Second
`state. When the signal ADV/LDb is in the first state, the
`circuit 102 will generally load an address presented by the
`signal ADDR EXT as an initial address. When the signal
`ADV/LDb is in the second state, the circuit 102 may be
`configured to generate the signal ADDR INT as a fixed
`number of addresses in response to the Signal CLK. The
`signal ADDR INT may be, in one example, an internal
`address signal. The signal ADDR INT may be n-bits wide.
`Once the circuit 102 has started generating the fixed number
`of addresses, the circuit 102 will generally not stop until the
`fixed number of addresses has been generated (e.g., a
`non-interruptible burst).
`The Signal BURST may be, in one example, a configu
`ration signal for programming the fixed number of addresses
`that the circuit 102 may generate in response to the Signals
`CLK and ADV/LDb. The signal BURST may be generated,
`in one example, by (i) using bond options, (ii) Voltage levels
`applied to external pins, or (iii) other appropriate signal
`generation means.
`When the memory 104 is implemented as a DRAM, the
`circuit 100 may be configured to hide required DRAM
`refreshes (e.g., refreshes may occur without affecting exter
`nal environment) inside a known fixed burst length of data
`40
`words. The fixed burst length may allow the circuit 100 to
`operate at higher frequencies than a conventional DRAM
`without needing interrupts to perform refreshes of data. In
`one example, the fixed burst length may be four or eight
`words. However, the burst length may be set to whatever
`length is necessary to meet the design criteria of a particular
`application. For example, the burst length may be
`programmed, in one example, to allow both writeback and
`refresh to occur within a single access. The fixed burst
`length may be Set, in one example, longer or Shorter
`depending upon a frequency or technology to be used.
`The circuit 100 may be configured to provide a fixed burst
`length that may Suit the requirements of network customers
`who typically burst large data lengths. By providing a fixed
`burst length, the circuit 100 may allow shared usage of data,
`address and control busses. A fixed length non-interruptible
`burst generally frees up the address bus and control bus for
`a known number of cycles. The address and control busses
`may be shared by a number of memory devices. The circuit
`100 may provide a more reliable and/or accurate burst than
`is possible with multiple chips.
`Referring to FIG. 2, a detailed block diagram illustrating
`implementation of the circuit 102 is shown. The circuit 102
`may comprise an address counter register 126 and a burst
`counter 128. The address counter register 126 generally
`receives the signals ADDR EXT, LOAD, and CLK. The
`address counter register 126 may be configured to present
`
`4
`the signal ADDR INT. The signal ADV and the signal
`BURST may be presented to a burst counter 128. The signal
`CLK may be presented at an input 130 of the burst counter
`128. The burst counter 128 may have an output 132 that may
`present a signal (e.g., BURST CLK) at an input 134 of the
`circuit 126. An initial address may be loaded into the address
`counter register 126 by presenting the initial address in the
`signal ADDR EXT and asserting the signal LOAD. The
`circuit 126 may be configured to increment an address in
`response to the signal BURST CLK. When the signal ADV
`is asserted, the burst counter 128 will generally present the
`signal BURST CLK in response to the signal CLK. The
`signal BURST CLK generally contains a number of pulses
`that has been programmed by the signal BURST.
`Referring to FIG. 3, a detailed block diagram illustrating
`an alternative embodiment of the circuit 102 is shown. The
`circuit 102' may comprise a latch 134, a multiplexer 136 and
`a counter 138. The signals ADDR EXT, LOAD and CLK
`may be presented to the latch 134. The latch 134 may have
`an output 140 that may present a portion (e.g., m bits, where
`m is an integer smaller than n) of the signal ADDR EXT as
`a portion of the signal ADDR INT, an output 142 that may
`present a second portion (e.g., kbits, where k is an integer
`Smaller than n) of the signal ADDR EXT to a first input of
`the multiplexer 136, and an output 144 that may present the
`second portion of the signal ADDR EXT to an input 146 of
`the counter 138.
`The signals ADV, CLK and BURST may be presented to
`inputs of the counter 138. The counter 138 may be config
`ured to generate a number of addresses in response to the
`signals CLK, BURST and ADV. The number of addresses
`generated by the counter 138 may be programmed by the
`signal BURST
`The signal BURST may be presented to a control input of
`the multiplexer 136. The multiplexer 136 may select
`between a number of signals from the latch 134 and a
`number of signals from the counter 138 to be presented as
`a second portion of the signal ADDR INT in response to
`the signal BURST
`Referring to FIG. 4, a flow diagram illustrating an
`example burst address Sequence is shown. When the Signal
`ADV is asserted, the circuit 100 will generally generate a
`number of address signals, for example, N where N is an
`integer. The address Signals may be generated, in one
`example, on a rising edge of the Signal CLK. The address
`Signals will generally continue to be generated until the Nth
`address Signal is generated.
`Referring to FIGS. 5A and 5B, timing diagrams illustrat
`ing example operations for a four word (FIG. 5A) and an
`eight word (FIG. 5B) fixed burst memory in accordance with
`the present invention are shown. The timing diagrams gen
`erally illustrate externally measurable signals for four and
`eight word fixed burst read/write architectures. In general,
`an operation (e.g., read or write) of the circuit 100 begins
`with loading an initial address (e.g., portions 150, 154, and
`158 of FIG. 5A; portions 150', 154, and 158 of FIG. 5B).
`Starting with the initial address, a fixed number of words are
`generally transferred (e.g., line DQ of FIGS. 5A and 5B).
`During the transfer of the fixed number of words, the address
`and control buses (e.g., ADDR, CE, R/W, etc.) are generally
`available to other devices (e.g., portions 152, 156, and 160
`of FIG. 5A; portions 152', 156', and 160' of FIG. 5B). In one
`example, the control and address bus activity may be one
`fourth (FIG. 5A) or one-eighth (FIG. 5B) the data bus
`activity (e.g., compare line ADDR with line DQ of FIGS. 5A
`and 5B). The reduced bus activity may be an effect of the
`
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`Petitioner STMicroelectronics, Inc., Ex. 1001
`IPR2021-00355, Page 6
`
`

`

`US 6,651,134 B1
`
`S
`architecture. The data bus may be, in one example, active
`nearly 100% of the time (e.g., line DQ of FIGS.5A and 5B)
`In one example, there may be no inefficiencies Switching
`from read to write to read etcetera (e.g., see labels under line
`DQ of FIGS.5A and 5B).
`Referring to FIG. 6, a timing diagram illustrating a fixed
`burst length long enough to hide a writeback and a refresh
`cycle is shown. Internally the action being performed may
`completely hide DRAM refresh activity inside nominal
`external activities. A portion 162 illustrates that refresh
`activity (e.g., writeback, read for refresh, and writeback for
`refresh) may be completed within the time of the burst
`transfer. When a fixed burst long enough to completely hide
`refresh activity is provided, there may be no penalty for
`using DRAM instead of SRAM for the memory 104.
`While the invention has been particularly shown and
`described with reference to the preferred embodiments
`thereof, it will be understood by those skilled in the art that
`various changes in form and details may be made without
`departing from the Spirit and Scope of the invention.
`What is claimed is:
`1. A circuit comprising:
`a memory comprising a plurality of Storage elements each
`configured to read and write data in response to an
`internal address Signal; and
`a logic circuit configured to generate a predetermined
`number of Said internal address Signals in response to
`(i) an external address signal, (ii) a clock signal and (iii)
`one or more control Signals, wherein Said generation of
`Said predetermined number of internal address Signals
`is non-interruptible.
`2. The circuit according to claim 1, wherein Said prede
`termined number of internal address Signals is determined
`by a fixed burst length.
`3. The circuit according to claim 1, wherein Said prede
`termined number of internal address signals is at least 4.
`4. The circuit according to claim 1, wherein Said prede
`termined number of internal address signals is 8.
`5. The circuit according to claim 2, wherein Said fixed
`burst length is programmable.
`6. The circuit according to claim 5, wherein said fixed
`burst length is programmed by bond options.
`7. The circuit according to claim 5, wherein said fixed
`burst length is programmed by Voltage levels on external
`pins.
`8. The circuit according to claim 1, wherein Said memory
`comprises a Static random acceSS memory.
`9. The circuit according to claim 1, wherein Said memory
`comprises a dynamic random access memory.
`
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`10. The circuit according to claim 9, wherein said prede
`termined number of internal address Signals is chosen to
`provide time for at least one writeback or refresh cycle.
`11. The circuit according to claim 1, wherein Said prede
`termined number of internal address Signals is chosen to
`meet predetermined criteria for Sharing address and control
`buSSes.
`12. The circuit according to claim 1, wherein Said logic
`circuit comprises a counter configured to generate Said
`predetermined number of internal address signals.
`13. The circuit according to claim 1, wherein Said external
`address Signal comprises an initial address for data transfers
`to and from Said memory.
`14. A memory device according to claim 1, wherein Said
`circuit is an integrated circuit.
`15. The circuit according to claim 1, further comprising
`address and control buSSes configured to present Said exter
`nal address signal and Said one or more control Signals,
`wherein Said buSSes are freed up during the generation of
`Said predetermined number of internal address Signals.
`16. A circuit comprising:
`means for reading data from and writing data to a plurality
`of Storage elements in response to a plurality of internal
`address Signals, and
`means for generating a predetermined number of Said
`internal address signals in response to (i) an external
`address signal, (ii) a clock signal and (iii) one or more
`control Signals, wherein Said generation of Said prede
`termined number of internal address Signals is non
`interruptible.
`17. A method of providing a fixed burst length data
`transfer comprising the Steps of
`accessing a memory in response to a plurality of internal
`address Signals, and
`generating a predetermined number of Said internal
`address signals in response to (i) an external address
`Signal, (ii) a clock signal and (iii) a control Signal,
`wherein Said generation of Said predetermined number
`of internal address Signals is non-interruptible.
`18. The method according to claim 17, further comprising
`the Step of programming Said predetermined number.
`19. The method according to claim 18, wherein said
`programming Step is performed using bond options.
`20. The method according to claim 18, wherein said
`programming Step is performed using Voltage levels.
`21. The method according to claim 17, further comprising
`the Step of Selecting Said predetermined number to provide
`time for at least one writeback or refresh cycle.
`
`k
`
`k
`
`k
`
`k
`
`k
`
`Petitioner STMicroelectronics, Inc., Ex. 1001
`IPR2021-00355, Page 7
`
`