United States Patent [19J
`Miller et al.
`
`I 1111111111111111 11111 lllll lllll lllll lllll 111111111111111 111111111111111111
`5,465,360
`Nov. 7, 1995
`
`US005465360A
`[lll Patent Number:
`[45] Date of Patent:
`
`[54] METHOD AND APPARATUS FOR
`INDEPENDENTLY RESETTING
`PROCESSORS AND CACHE CONTROLLERS
`IN MULTIPLE PROCESSOR SYSTEMS
`
`[75]
`
`Inventors: David A. Miller, Houston; Kenneth A.
`Jansen, Spring; Paul R. Culley,
`Cypress; Mark Taylor; Javier F.
`Izquierdo, both of Houston, all of Tex.
`
`[73] Assignee: Compaq Computer Corp., Houston,
`Tex.
`
`[21] Appl. No.: 152,241
`
`[22] Filed:
`
`Nov. 12, 1993
`
`Related U.S. Application Data
`
`[63] Continuation of Ser. No. 15,314, Feb. 9, 1993, which is a
`continuation of Ser. No. 431,653, Nov. 3, 1989.
`Int. Cl.6
`•••••.•••••••••.•.••••..•••••••.•...•••••••••••..••.•... G06F 9/00
`[51]
`[52) U.S. Cl. ····································· 39Snoo; 364/DIG. 1;
`364/280.3; 364/280.2; 364/282
`[58) Field of Search ...................................... 395/700, 375
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,779,187 10/1988 Letwin .................................... 364/200
`4,787,032 11/1988 Culley ..................................... 364/200
`
`FOREIGN PATENT DOCUMENTS
`
`0191402
`0398995
`
`8/1986 European Pat. Off ..
`5/1989 European Pat. Off ..
`
`OTHER PUBLICATIONS
`
`Intel Corporation, Microprocessors 1990, pp. 4-170 to
`4-304.
`Intel Corporation, Microprocessors 1990, pp. 4-343 to
`4-409.
`Compaq Computer Corp., Compaq Deskpro 386/20 Tech(cid:173)
`nical Reference Guide, vol. 1, Oct., 1987, pp. 2-108 to
`2-122.
`Japan Abstract vol. 6 No. 206 (P-149) (1084) Oct. 9, 1982.
`
`Primary Examiner-Kevin A. Kriess
`Attorney, Agent, or Firm-Pravel, Hewitt, Kimball &
`Krieger
`
`[57]
`
`ABSTRACT
`
`A method and system for independently resetting primary
`and secondary processors 20 and 120 respectively under
`program control in a multiprocessor, cache memory system.
`Processors 20 and 120 are reset without causing cache
`memory controllers 24 and 124 to reset.
`
`4,679,166
`
`7 /1987 Berger et al ............................ 364/900
`
`6 Claims, 7 Drawing Sheets
`
`170 1---.---x,-,~'7~~.,.~-.;
`
`217 +-:::,____;W.:..:./.:..:.R-<
`Pl INT
`202
`164 1--~....-+--=E'°"l;~:-',-~i'='o~! -i
`
`CLK1
`
`214
`
`212
`
`217
`
`216
`
`230 ~-----,H-- P1 HOLD
`
`SHUTDOWN
`P1 HOLD A
`RESET
`CONTROL
`192 R STAR*
`LOGIC
`1661-lf-.-:19:-::-0--R;;-;;S:;-T-J---L__.,.._...J
`RESET --.-+--+'------+----'
`
`Pl PCL
`
`PI/P2 MODE
`
`CLK 2
`X DATA
`W/R
`PRS 0 .. 3
`EISACMD•
`
`202
`
`SHUTDOWN
`P2HOLD A
`RST
`
`190
`
`RESET
`
`218
`
`213
`
`230
`
`RESET
`CONTROL
`LOGIC
`
`186
`
`188
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 1
`
`

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`2s
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`
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`
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`
`38
`
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`
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`
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`
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`
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`
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`
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`
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`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 2
`
`

`

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`
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`
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`
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`
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`
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`
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`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 3
`
`

`

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`
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`
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`
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`
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`
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`
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`
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`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 4
`
`

`

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`
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`
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`
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`
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`
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`
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`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 5
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 5 of 7
`
`5,465,360
`
`162
`____ CONTROL
`MIO;CMD .---__,,_---.
`
`W/R
`
`A (31...0)
`
`ADDRESS
`DECODE
`
`DATA (7 ... 0)
`
`BUS
`INTERFACE
`
`186
`
`LA (31 .. 2)
`174
`SA (1 .. 0)
`176
`
`XDATA
`178 (l.O)
`El SA
`CONTROL
`180
`
`EISA CLK
`(BCLK)
`
`SYSTEM.__ __ __
`RESET
`160
`
`FUNCTION
`SELECT
`
`/
`
`150
`
`166
`
`RESTART
`
`PORT 092
`
`RSTAR*
`
`KEYBOARD
`CONTROLLER
`SELECT. W-R
`
`168
`
`170
`
`REAL TIME
`CLOCK
`
`CLK
`
`172
`
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`CONTROLLER
`•
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`
`TO ISP
`
`22
`
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`
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`
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`
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`
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`
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`
`PROCESSOR 2
`
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`
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`CONTROLLER
`
`24
`
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`PHOLD A 1
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`
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`
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`
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`
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`
`Fl6.15
`
`160
`
`PRS
`
`150
`
`302
`
`HOST BUS
`
`44
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 6
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 6 of 7
`
`5,465,360
`
`FIE,LJ
`•
`
`170
`
`217-
`1202
`
`CLK 2
`X DATA -
`W/R -
`~
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`PRS 0 .. 3
`EISA CMD*
`
`164
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`
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`1-- 219
`
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`
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`
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`
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`
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`
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`
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`CONTROL
`LOGIC
`
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`
`-
`
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`
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`
`crRST
`
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`P1 HOLD A
`I 192 R STAR*
`
`190
`
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`
`166
`
`RESET
`
`,
`
`l
`,, 202
`
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`X DATA
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`PRS 0 .. 3 _
`EISACMD ~
`
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`
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`
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`
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`
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`
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`I
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`
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`
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`
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`
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`
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`
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`
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`
`'219
`
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`
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`
`213
`
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`
`RESET
`CONTROL
`LOGIC
`
`r t
`
`\... 226
`
`220
`
`P2 INT
`
`~188
`
`P2 HOLD
`
`P2 PCL
`
`• • •
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 7
`
`

`

`0\. =
`~
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
`256
`
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`
`269
`
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`
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`
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`
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`268
`
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`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 8
`
`

`

`5,465,360
`
`1
`METHOD AND APPARATUS FOR
`INDEPENDENTLY RESETTING
`PROCESSORS AND CACHE CONTROLLERS
`IN MULTIPLE PROCESSOR SYSTEMS
`
`This continuation of application Ser. No. 08/015,314
`filed on Feb. 9, 1993, which is a continuation of application
`Ser. No. 07/431,653 filed on Nov. 3, 1989, now abandoned.
`
`BACKGROUND OF THE INVENTION
`
`lO
`
`2
`busses. Details of an example of such systems is set forth in
`the Intel system design handbooks for the 80386 family,
`such as the Microprocessor and Peripheral Handbook Vol(cid:173)
`ume 1, specifically pages 4-292 through 4-353 of the Octo-
`5 ber, 1988 reference manual.
`Further development of personal computer systems led to
`the design of systems including multiple processors, each
`having an associated cache memory and cache controller, as
`well as a coprocessor. In such sy,stems one of the processors
`is typically the primary processor which controls and utilizes
`the other secondary processors. The Intel Microprocessor
`and Peripheral Handbook at page 4-295 disclosed such a
`multiple processor system where each processor and asso(cid:173)
`ciated cache system were connected to a common local bus
`15 which is then connected to a system bus. In the Intel design,
`another device known as the Intel 82380 32-bit OMA
`controller was also connected to the local bus and utilized to
`provide direct memory access control, interrupt control,
`timing, wait state generation, dynamic (non-cache) memory
`refreshing and processor reset control. In the Intel system,
`both processors and cache controllers interface to the system
`bus via a common local bus interface. As designed, the cache
`controllers and associated processors were reset by a com-
`mon signal.
`Resets are utilized to interrupt all system activity and
`bring all elements of the system to a known initialization
`state. Resets are assigned the highest priority among system
`signals and when a reset signal is asserted, all activity
`ceases. In 80386 and earlier 80286 based systems reset
`30 signals can be generated by hardware such as a switch, by
`operator command via a keyboard or under program control.
`A hardware reset occurs when the system is first energized
`or turned on. Software or program controlled resets are
`utilized by programmers for a variety of reasons.
`One example of the use of a programmed reset relates to
`setting the mode of the processor. Both 80286 and 80386
`processors are initialized in a mode known as the Real
`Mode. Real Mode operation is typically only utilized as a
`prelude to system operation such as during a system initial(cid:173)
`ization sequence which occurs on power up. Real Mode
`operation utilizes a system addressing scheme which is
`limited and greatly restricts the ability of the processor to
`address large memory spaces. In the 80386 Real Mode
`45 operation limits the processor to one megabyte of address(cid:173)
`able memory space. Typically, once initialization is com(cid:173)
`pleted, the system transitions to Protected Mode. Protected
`Mode allows the processor to use virtual addressing to
`expand the addressable memory to four terabytes.
`In the design of the 80286 family it was not anticipated
`that after system initialization it would be desirable to revert
`from Protected Mode to Real Mode, and consequently no
`provision was made to accomplish this under program
`control. Software designed for the 80286 system frequently
`incorporated software initiated resets to cause the 80286 to
`reset in order to revert from Protected Mode to Real Mode.
`In order to maintain software compatibility with software
`designed for 80286 systems, it is necessary to accommodate
`software resets as a method of resetting the processor to Real
`60 Mode.
`In prior art systems using multiple processors and cache
`controllers connected via a common bus the utilization of a
`reset signal caused all processors and cache controllers to
`reset. On reset the 82385 cache controller clears the cache
`65 memory by executing a cache flush operation which invali(cid:173)
`dates all data stored in the cache. When 82385 controllers
`are utilized in master mode, a reset causes the controller to
`
`20
`
`35
`
`1. Field of the Invention
`This invention relates to a method and apparatus for
`independently controlling and implementing the reset of the
`processors and cache memory system controllers in multiple
`processor computer systems utilizing cache memory.
`2. Discussion of the Related Art
`Personal computer systems have developed from systems
`utilizing a single processing unit or CPU to systems which
`include multiple processors operating in parallel. One of the
`first developments was to include a second arithmetic copro(cid:173)
`cessor in parallel with the main CPU to perform time(cid:173)
`consuming and complex arithmetic tasks leaving the main
`CPU free to perform system control, input/output, memory
`operations and other less time-consuming code execution. 25
`Systems incorporating the Intel 80386 processor and 80387
`coprocessor are one common example of such more
`advanced systems.
`In addition to the development of arithmetic coprocessors,
`memory systems used by the processor have evolved from
`single units of read only memory for storing fixed system
`instructions and static random access integrated circuit
`memory to further include peripheral memory devices such
`as floppy-disk and fixed-disk memories and associated inter(cid:173)
`face and control circuity.
`As the speed of processors was enhanced, it became
`necessary to enhance the speed at which memory operations
`could be performed so as to take advantage of the newer
`high speed processors such as the Intel 80386. High speed 40
`static RAM devices were available, but to implement the
`entire memory requirement with high speed RAM was too
`expensive for personal computer systems. One solution to
`the problem was the implementation of what is known as a
`cache memory system.
`In a cache memory system a small amount of more
`expensive fast memory, typically static RAM devices, is
`used for high speed execution and slower, less expensive
`dynamic RAM and peripheral devices are used for the bulk
`memory requirements. Data or code contained in portions of 50
`the main memory is duplicated in the fast cache memory so
`that operations requiring only data or code in cache memory
`can be executed quickly. Idealized cache memory systems
`seek to match the upcoming processor code and data
`requests to code and data maintained in cache memory by 55
`changing the contents of the cache memory as the processor
`executes code or instructions to minimize the number of
`times slower memory has to be accessed by the processor.
`Updating and maintaining the directory to the cache
`memory is performed by a device known as a cache con(cid:173)
`troller. One such device is the Intel 82385 cache controller
`designed for use with the 80386 processor. The cache
`controller also determines whether the requested data or
`code is resident in cache or whether it is necessary to retrieve
`it for the processor from main memory. The cache controller
`therefore interfaces between the processor and the cache
`memory and the main memory via one or more system
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 9
`
`

`

`5,465,360
`
`4
`shown in FIGS. 1 and 2; and
`FIG. 4 is a schematic diagram of one portion of the reset
`control circuit which forms a part of the system shown in
`FIGS. 1 and 2.
`FIG. 5 is a schematic diagram of a second portion of the
`reset control circuitry which forms a part of the system
`shown in FIGS. 1 and 2.
`FIG. 6 is a schematic block diagram illustrating a portion
`of the system shown in FIGS. 1 and 2.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`3
`latch the 80386 reset values to the system bus interface by
`emitting a pulsed output signal on its address clock pulse
`(BACP) output pin. This results in the 82385 trying to
`acquire control of the system bus. In situations where the
`reset is a software reset intended only to reset one processor, 5
`as distinguished from a power up, hardware system reset, the
`prior art provided no simple and efficient way to avoid bus
`contention by the 82385 controllers which tried to acquire
`the bus while one of the non-reset processors was operating.
`In multiprocessor systems, it is desirable to independently
`reset each processor. The prior art provides no suitable
`mechanism to meet this need.
`The present invention addresses these shortcomings of
`prior art systems and provides a system wherein each
`processor may be reset independently under program control 15
`after system initialization. The present invention also pro(cid:173)
`vides a system for resetting each processor independently
`without introducing cache memory incoherency. A cache
`memory incoherency may occur when more than one device
`has access to common memory space. In such situations, one 20
`device may make an alteration to data in memory which is
`not also made to the duplicated data in the cache memory.
`
`10
`
`SUMMARY OF THE INVENTION
`
`Referring now to FIGS. 1 and 2, the letter C designates
`generally a computer system incorporating the present
`invention. For clarity, system C is shown in two portions,
`with the interconnections between FIGS. 1 and 2 designated
`by reference to the circled numbers one to ten. System C is
`comprised of a number of block clements interconnected via
`three busses. Throughout this specification in signal mncu-
`monics an asterisk following the signal descriptors indicates
`the signal is active at a logic low level.
`In FIG. 1, a dual processor cache memory computer
`25 system is depicted. A primary processing unit Pl comprises
`a processor 20, a numerical coprocessor 22 and a cache
`memory controller 24 and associated logic circuits con(cid:173)
`nected to a processor bus 26. Associated with cache con(cid:173)
`troller 24 is a high speed cache data random access memory
`30 28, cache memory map programmable logic circuit 30,
`non-cacheable cache memory map logic circuit 32, address
`exchange latch circuit 34 and data exchange transceiver 36.
`Associated with Pl also are local bus ready logic circuit 38,
`next address enable logic circuit 40 and bus request logic
`35 circuit 42.
`Processor 20 is preferably an Intel 80386 microprocessor.
`Processor 20 has its control, address and data lines inter(cid:173)
`faced to processor bus 26. Coprocessor 22 is preferably an
`Intel 80387 numeric coprocessor interfacing with processor
`bus 26 and processor 20 in the conventional manner. Cache
`ram 28 is preferably a suitable high-speed static random
`access memory circuit which interfaces with the address and
`data elements of bus 26 under control of cache controller 24
`to carry out required cache memory operations. Controller
`24 is preferably an Intel 82385 cache controller configured
`to operate in two-way set associative master mode. Address
`latch 34 and data transceiver 36 interface the cache control(cid:173)
`ler 24 with processor 20 and provide a local bus interface
`between processor bus 26 and a host bus 44.
`Circuit 38 is a logic circuit which provides a bus ready
`signal to control access to bus 26 and validate address
`information. Enable circuit 40 is utilized by processor 20 to
`enable the next address of data or code to be utilized by
`sub-system elements in pipelined address mode.
`Circuit 30 is a programmable logic circuit which is
`utilized by cache controller 24 to map data locations in cache
`ram 28. Non-cacheable map circuit 32 is utilized by pro(cid:173)
`cessor 20 to designate areas of cache ram that are non-
`60 cacheable to avoid any cache memory incoherency for data
`or code at specified main memory locations. Bus request
`logic circuit 42 is utilized by processor 20 and associated
`elements to request access to the system bus 46 in situations
`such as when requested data is not located in cache memory
`65 28 and access to system main memory is required. (FIG. 2).
`In the drawings, system C is configured having the
`processor bus 26, host bus 44 and extended industry stan-
`
`The present invention provides a system of independently
`res~tting processors in a multiprocessor cache memory
`environment. On power up, a hardware reset, all processors
`and cache memory devices are reset to initialization values.
`The cache controllers are reset only on hardware reset, and
`placed in a hold state after the processor reset signals are
`released. Since power up resets of the processors and cache
`controllers are synchronized, no bus contention results. After
`hardware reset, when the secondary processors acknowledge
`a hold request, the primary processor is given access to the
`common processor or host bus until system protocol deter(cid:173)
`mines one of the other processors or system elements, such
`as the extended industry standard (EISA) bus in EISA
`systems, requires the bus.
`Software or programmed resets cause only the selected 40
`processor(s) and not the cache controllers to be reset.
`Programmed resets are synchronized to hold acknowledge
`signals from the processors so that resets do not occur during
`program execution by one or more processors thereby
`avoiding any cache memory incoherency. The primary pro- 45
`cessor can be reset under program control consistent with
`existing software convention without effecting the operation
`of the cache controllers or the secondary processors. The
`primary processor may also be independently reset in
`response to a keyboard initiated instruction. The secondary 50
`processors can be program reset by setting a reset bit located
`in a designated secondary processor control register addres(cid:173)
`sable under program control, or via the user interface
`keyboard, or by the primary processor. All processors are
`reset in response to system shutdown signals.
`
`55
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A better understanding of the present invention can be
`obtained when the following detailed description of the
`preferred embodiment is considered in conjunction with the
`following drawings, in which:
`FIG. 1 is a schematic block diagram of a portion of a
`computer system incorporating the present invention;
`FIG. 2 is a schematic block diagram of a portion of a
`computer system incorporating the present invention;
`FIG. 3 is a schematic diagram of one portion of the system
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 10
`
`

`

`5,465,360
`
`5
`dard bus 46. The details of the portion of the system
`illustrated in FIG. 2, and not discussed in detail below are
`not significant to the present invention other than to illustrate
`an example of a fully configured dual processor cache
`memory system. The EISA specification Version 3.1 is 5
`provided in U.S. Pat. No. 5,101,492 filed Sep. 3, 1989,
`issued Mar. 31,, 1992, and entitled "Data Redundancy and
`Recovery Protection" by Schultz, et al., and fully explains
`the requirements of an EISA systems and is hereby incor(cid:173)
`porated by reference. The portion of system C illustrated in 10
`FIG. 2 is essentially a conventionally configured EISA
`system which includes the necessary bus 46, EISA bus
`controller 48, data transceiver 50 and address latch 52 to
`interface between bus 46 and host bus 44. Also illustrated in
`FIG. 2 is an integrated system peripheral 54, such as the Intel 15
`82380 DMA controller and integrated system support
`peripherals.
`Circuit 54 includes a direct memory access controller 56
`for controlling direct access to main memory 58 (FIG. 1) by
`system elements via bus 44. Memory array 58 comprises a 20
`memory circuit array of size suitable to accommodate the
`particular requirements of the system. Circuit 54 also
`includes interrupt controllers 70, non-maskable interrupt
`logic 72 and system timers 73 which allow control of
`interrupt signals and generate necessary timing signals and 25
`wait states in a conventional manner. In the preferred
`embodiment, processor generated interrupt requests are con(cid:173)
`trolled via dual interrupt control circuits emulating Intel
`8259 interrupt controllers resident in system integrated
`peripheral circuit 54. Circuit 54 also includes DMA arbitra- 30
`tion logic 76 which controls and arbitrates among system
`DMA requests.
`Memory array 58 (FIG. 1) is preferably dynamic random
`access memory. Memory 58 interfaces with bus 44 via data
`buffer circuit 60 and memory controller circuit 62 in a 35
`conventional manner. Buffer 60 performs data transceiving
`and parity checking functions. Controller 62 interfaces with
`memory 58 via an address multiplexer circuit which
`includes row address enable logic circuit 64 and column
`address circuit 66 in a conventional manner.
`Arbitration for busses .44 and 46 is controlled by arbi(cid:173)
`tration logic circuit 74.
`Bus 46 includes ISA and EISA control elements 75 and
`78 ISA and EISA data elements 80 and 82 and address
`el:ments 84, 86 and 88 in a standard EISA configuration. 45
`System peripherals are interfaced via X bus 90 in combi(cid:173)
`nation with the control element 75 from bus 46. Control and
`data/address transfer for X bus 90 are facilitated by X-bus
`control logic 92, data transceiver 94 and address latch 96.
`Attached to X bus 90 are various peripheral devices such
`as keyboard/mouse controller 98 which interfaces bus 90
`with a suitable keyboard and mouse via connectors 100 and
`102, respectively. Also attached to X bus 90 are real time
`clock circuit 104 and a read only memory circuit 106 which 55
`contains basic operations software for the system C and for
`system graphics. A serial communications port 108 is also
`connected to the system C via X-bus 90.
`External memory and control interface, parallel printer
`and communications ports, and video support circuits are 60
`provided in block circuit 110 in a conventional manner.
`Referring now back to FIG. 1, a secondary processor P2
`is illustrated. Processor P2 is a duplicate of processor Pl and
`consequently it is not necessary to describe the individual
`elements in detail. Elements of P2 are the same as corre- 65
`sponding elements of Pl and have been numbered so that
`elements of P2 bear numbers 120, 122, 124 etc. correspond-
`
`50
`
`6
`ing to elements 20, 22 and 24 in processor Pl.
`Arbitration logic circuit 74 arbitrates requests for access
`to host bus 44 among Pl, P2 and the EISA DMA controller.
`If one processor requires the host bus and the other processor
`has the host bus, but is inactive, arbitrater circuit 74 requests
`the inactive processor to relinquish the bus by asserting an
`active signal on the processor's HOLD input line. When the
`inactive processor asserts a HOLD ACKNOWLEDGE
`(HLDA) response, control of the host bus is granted to the
`requesting processor by deasserting its HOLD line. If one
`processor requests the host bus while it is controlled by the
`EISA bus master, a CPUMISS* signal is asserted to arbi(cid:173)
`trator 76 in ISP circuit 54. The EISA bus master maintains
`control until the ISP arbitrator deasserts its H HOLD signal
`whereupon arbitration circuit 74 deasserts its processor H
`HOLD signal and the requesting processors HOLD line. If
`both processors are requesting control of the bus and pri(cid:173)
`mary processor Pl is not asserting an interrupt, the processor
`least-recently on the bus is granted control. If both proces(cid:173)
`sors are requesting control and Pl is asserting an interrupt,
`Pl is granted control. If either processor .has control of host
`bus 44, it maintains control until a request from the other
`processor or the EISA bus 46 is received.
`Control of the host bus 44 by either processor Pl or P2 is
`protected from interruption by EISA bus controller 48 by an
`EISA arbitration inhibit timer resident in arbitration circuit
`74. When control of host bus 44 is transferred to either
`processor Pl or P2, the timer is started and remains active
`for a period of time as specified in a read/write, input/output
`arbitration register to accommodate processor operation. As
`long as the timer is active, the processor with control of the
`host bus 44 will not be interrupted by a H HOLD from the
`EISA controller or the other processor's bus request; pro-
`cessor P2 can still be interrupted by processor Pl if proces(cid:173)
`sor Pl is asserting its interrupt request.
`The period of the inhibit timer is set by multiplying the
`basic clock period of processor Pl by two and by the value
`set in the arbitration register under program control. At reset,
`the arbitration value is zero (no arbitration inhibit) and is
`.
`subsequently adjusted depending upon program reqmre-
`ments.
`EISA bus 46 requires access to host bus 44 during direct
`memory access operation and EISA bus master cycles. The
`EISA bus controller 48 initiates a request for access to host
`bus 44 by asserting a H HOLD signal to arbitration circuit
`74. If the EISA inhibit timer is not active, or when the
`processor which controls the bus deasserts its bus request,
`arbitration circuit 74 requests the bus by asserting its HOLD
`line to the controlling processor. When the controlling
`processor asserts its HOLD ACKNOWLEDGE signal,
`access to the host bus 44 is granted to the EISA bus 46 by
`the arbitration circuit asserting an active HHLDA acknowl(cid:173)
`edge signal. Control by EISA bus 46 is thereafter maintained
`until H HOLD is deasserted. The H HOLD signal is syn(cid:173)
`chronized to CLKl * (Pl primary clock signal, negative
`component). HHLDA is synchronized to CLKl * before
`being asserted.
`In the drawings, logic circuit 150 designates generally
`processor control and communication application specific
`integrated circuit which includes logic circuits necessary to
`generate a variety of interprocessor control and communi(cid:173)
`cations signals. Circuit 150 includes circuitry to accomplish
`processor reset requests and reset signal generation for the
`primary and secondary processors. Circuit 150 also includes
`a communication Input/Output register for facilitating inter(cid:173)
`processor communications and processor control. In the
`
`~
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1039, p. 11
`
`

`

`7
`preferred embodiment an eight-bit register is provided for
`each processor in the system. These registers are part of a
`processor control logic circuit for each processor. These
`registers can be either input/output or memory mapped and
`are decoded from four pseudo address lines designated 5
`PRS3 to PRS0.
`While circuit 150 is illustrated as a single block, it should
`be understood that functions performed in this logic circuit
`as well as other logic circuits described generally herein can
`be distributed to other single purpose or multipurpose inte-
`grated circuits without departing from the present invention.
`The distribution oflogic functions to one or more integrated
`circuits is largely a matter of design choice within the
`ordinary skill in the art. In the preferred embodiment, the
`functions described herein as within circuit 150 are physi(cid:173)
`cally located in portions of two separately packaged gate(cid:173)
`arrays which integrate a number of system control and
`cominunications functions. These two gate-arrays also inte(cid:173)
`grate a number of other functions for the system C shown
`herein as separate schematic blocks.
`
`15
`
`RESET AND PROGRAMMABLE RESET
`(RESTART)
`Referring now to FIG. 3, a schematic block diagram of a 25
`portion of logic circuit 150 is illustrated. This portion of
`circuit 150 includes a bus interface 160, an address decode
`circuit 162, processor control logic register sele