O
`
`United States Patent (19)
`Lysinger
`
`III USO05784331A
`11
`Patent Number:
`5,784,331
`45 Date of Patent:
`Jul. 21, 1998
`
`54 MULTIPLE ACCESS MEMORY DEVICE
`
`5,526,320 6/1996 Zagar et al. ......................... 365/233.5
`
`75) Inventor: Mark A. Lysinger. Carrollton, Tex.
`4
`8
`73) Assignee: SGSE; Microelectronics, Inc.,
`
`(21) Appl. No.: 775,664
`22 Filed:
`Dec. 31, 1996
`6
`I51)
`int. Cl. ..................................................... G11C 8/00
`52) U.S. Cl. ................................ 365/230.06; 365/189.05;
`d
`365/230.08
`58) Field of Search ......................... 365/230.06, 230.08,
`365/18905
`
`56)
`
`Primary Examiner-Son T. Dinh
`Attorney, Agent, or Firm-David V. Carlson; Theodore E.
`(Atly
`K. Jorgenson
`(57)
`ABSTRACT
`A memory circuit has a plurality of data storage locations
`and an address associated with each data storage location. A
`first decoded address storage circuit stores a first decoded
`memory address and outputs the stored first decoded
`memory address. A second decoded address storage circuit
`stores a second decoded memory address and outputs the
`stored second decoded memory address. An address access
`circuit is coupled to the output of the first decoded address
`storage circuit and accesses the data storage location asso
`ciated with the first decoded memory address in response to
`References Cited
`the first decoded memory address being output from the first
`U.S. PATENT DOCUMENTS
`decoded address storage circuit. A control circuit is coupled
`to the first decoded address storage circuit for controlling the
`6/1992 Slemmer et al. .................. 365/230.06
`5,124,951
`transfer of decoded memory address information from the
`5261,064 11/1993 Wyland...........................
`395/400
`3: E. E.
`ow 32:3: second decoded address storage circuit to the first decoded
`5315,759 61594 chan. ... address storage circuit.
`5.453,957
`9/1995 Norris et al.
`... 36.5/230.04
`5,469,391 11/1995 Haraguchi .......................... 36.5/230.06
`13 Claims, 22 Drawing Sheets
`
`27
`(
`
`0)
`
`
`
`69
`y 70
`DAA 1A DC
`INE,
`or
`BUFFER
`WDPC
`44 DPI
`46
`BAB
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`
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`FROM MEMORY BLC{0y>
`Cills
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`REC
`
`92
`so
`69 saw
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`93
`s 9i
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`MN
`CRCUIf
`SELECT
`CIRCUIT
`(FIG. 22)
`
`76
`RESET Bar &
`RESET
`CONTROL AESET
`COL. SEl.
`y
`861 130
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`RESE
`WRITES
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`SBI
`
`
`
`
`
`
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`
`BLOCK
`READ/WRITE
`CONTROL
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 1 of 22
`
`5,784.331
`
`
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`
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 2 of 22
`
`5,784,331
`
`L9S94
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`
`
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 3 of 22
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`5,784,331
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`NANYA TECHNOLOGYEXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`
`
`Jul. 21, 1998
`
`Sheet 4 of 22
`
`5,784,331
`
`8] [10
`
`3100
`00d
`NI
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 5 of 22
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`5,784,331
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`
`
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`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 6 of 22
`
`5,784,331
`
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 7 of 22
`
`5,784,331
`
`t
`
`Fig. 7 - 192
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 8 of 22 .
`
`5.784331
`
`700
`
`- 706
`
`706
`
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`
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`
`Fig. 9A
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`ROW ADDRESS.......
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`CLOCK -....
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`INPUT REGISTERS
`AND PRE-DECODER
`
`708
`
`INPUT REGISTERS
`AND DECODERS
`
`COLUMN AND
`BLOCK ADDRESSES
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`CLOCK 2-...-
`CLOCK 2.........
`
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`
`Fig. 9B
`SINGLE BLOCK - 128 COLUMNS - EIGHT I/O GROUPS
`BOCK SELECTED
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`COLUMN OF FOUR
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`SENSE AMPS AND
`STORACE REGISTERS
`
`BURST COUNTER
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`DATA INPUT AND OUTPUT
`
`DATA OUT
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 9 of 22
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`5,784.331
`
`
`
`(1 | 013)
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`
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 10 of 22
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`5,784,331
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 11 of 22
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`5,784,331
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 12 of 22
`
`5,784,331
`
`Fig. 13
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 13 of 22
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`5,784,331
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`Jul. 21, 1998
`
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`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 15 of 22
`
`5,784.331
`
`
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 16 of 22
`
`5,784,331
`
`130
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`X COLO
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`skLBAyC skUpC
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 17 of 22
`
`5,784.331
`
`:406-K
`40.
`
`4ff
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`K.
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`
`Fig. 19 “
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 18 of 22
`
`5,784,331
`
`:
`
`424
`
`430
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`
`20
`
`432
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`5,784,331
`
`
`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 20 of 22
`
`5,784,331
`
`WCC
`
`268
`
`
`
`C
`
`80
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`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 21 of 22
`
`5,784,331
`
`MEMORY
`
`
`
`
`
`
`
`COMPUTER 50
`SYSTEM
`
`
`
`566
`
`DATA
`STORAGE
`DEVICES
`
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`
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`DEVICES
`
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`INPUT
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`
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`
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`
`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 22 of 22
`
`5,784,331
`
`
`
`de C-d
`culvo Yr-cann
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`
`NANYA TECHNOLOGY EXHIBIT 1009
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`
`

`

`1.
`MULTIPLE ACCESS MEMORY DEVICE
`
`5,784.331
`
`10
`
`20
`
`25
`
`30
`
`5
`
`2
`data is provided to a user, it does not increase the speed of
`the cycle time nor shorten the overall time required to get
`data into or out of specific addresses within a memory array.
`One known technique for increasing the speed at which
`5 data is read out of a memory is to use a burst counter which
`increments the input and memory address under the control
`of a clock without requiring new address to be input. Prior
`artburst SRAMs used a burst counter which manipulated the
`address signal before it was input to the address decoder
`circuit. In these SRAMs, the output of the burst counter was
`then passed to an address decoder. This type of burst counter
`could also easily be attached to the front of existing syn
`chronous designs with no significant changes required to the
`memory core or to the synchronous decoder. Using this
`technique, the memory could use well known and reliable
`decoder circuits to select the rows and columns. One down
`side of this approach is that all address transitions must still
`propagate through the address decoder. The speed at which
`address signals can propagate through the address decoder
`may become a limiting factor at faster cycle times.
`SUMMARY OF THE INVENTION
`According to principles of the present invention, a
`memory circuit has a plurality of data storage locations and
`an address associated with each data storage location. A first
`decoded address storage circuit stores a first decoded
`memory address and holds it for accessing a particular
`memory address. A second decoded address storage circuit
`stores a second decoded memory address and holds it for
`accessing a second decoded memory address. A control
`circuit is coupled to the first decoded address storage circuit
`and operates to transfer decoded memory address informa
`tion from the second decoded address storage circuit to the
`first decoded address storage circuit.
`In one embodiment, a counter circuit is coupled to the
`output of the first decoded address storage circuit for access
`ing the data storage location associated with the first
`decoded memory address in response to the first decoded
`memory address being output from the first decoded
`memory circuit. The counter circuit includes a burst counter
`circuit which accesses the data storage location associated
`with the first decoded memory address and also accesses
`three additional data storage locations, the decoded memory
`addresses associated with these three additional data storage
`locations being generated by the burst counter circuit using
`the first decoded memory address.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a memory device in accor
`dance with the present invention.
`FIG. 2 is a block diagram of one embodiment of a
`read/write circuit of the memory device of FIG. 1.
`FIG. 3 is a block diagram of one embodiment of a row
`addressing circuit of the memory device of FIG. 1.
`FIG. 4 is a schematic of the address input buffer of FIG.
`3.
`F.G. 5 is a schematic of the even/odd row selector of FIG.
`3.
`FIG. 6 is a detailed schematic of the word line and block
`select circuit of FIG. 3.
`F.G. 7 is a detailed schematic of the word line select
`circuit of FIG. 3.
`FIG. 8 is a detailed schematic of the local word line drive
`circuit of FIG. 3.
`FIG. 9A is a block diagram of an SRAM in accordance
`with one embodiment of the present invention.
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`The following pending U.S. patent applications by David
`C. McClure entitled: "Architecture Redundancy." Ser. No.
`08/582.424 (Attorney's Docket No. 95-C-136), and "Redun
`dancy Control." Ser. No. 08/580,827 (Attorney's Docket
`No. 95-C-143). which were filed on Dec. 29, 1995, and have
`the same ownership as the present application, and to that
`extent are related to the present application, which are
`incorporated herein by reference; and entitled: "Test Mode
`Activation And Data Override,” Ser. No. 08/587.709
`(Attorney's Docket No. 95-C-137). "Pipelined Chip Enable
`Control Circuitry And Methodology,” Ser. No. 08/588,730
`(Attorney's Docket No. 95-C-138), "Output Driver Cir
`cuitry Having A Single Slew Rate Resistor." Ser. No.
`08/588.988 (Attorney's Docket No. 95-C-139). "Synchro
`nous Stress Test Control." Ser. No. 087589,015 (Attorney's
`Docket No. 95-C-142). “Write Pass Through Circuit." Ser.
`No. 08/588.662 (Attorney's Docket No. 95-C-144). "Data
`Input Device For Generating Test Signals On Bit And
`Bit-Complement Lines." Ser. No. 08/588.762 (Attorney's
`Docket No. 95-C-145), "Synchronous Output Circuit." Ser.
`No. 08/588.901 (Attorney's Docket No. 95-C-146). “Write
`Driver Having A Test Function." Ser. No. 08/589,141
`(Attorney's Docket No. 95-C-147), "Circuit And Method
`For Tracking The Start Of A Write To A Memory Cell." Ser.
`No. 08/589,139 (Attorney's Docket No. 95-C-148), "Circuit
`And Method For Terminating A Write To A Memory Cell."
`Ser. No. 08/588.737 (Attorney's Docket No. 95-C-149),
`"Clocked Sense Amplifier With Word Line Tracking." Ser.
`No. 08/587,782 (Attorney's Docket No. 95-C-150).
`"Memory-Row Selector Having A Test Function.” Ser. No.
`08/589,140 (Attorney's Docket No. 95-C-151). "Synchro
`nous Test Mode Initialization.” Ser. No. 08/588.729
`(Attorney's Docket No. 95-C-153). "Device And Method
`For Isolating Bit Lines From A Data Line." Ser. No. 08/588,
`740 (Attorney's Docket No. 95-C-154), "Circuit And
`Method For Setting The Time Duration Of A Write To A
`Memory Cell." Ser. No. 08/587,711 (Attorney's Docket No.
`95-C-156). “Low-Power Read Circuit And Method For
`Controlling A Sense Amplifier." Ser. No. 08/589,024
`(Attorney's Docket No. 95-C-168), "Device And Method
`For Driving A Conductive Path. With A Signal." Ser. No.
`08/587,708 (Attorney's Docket No. 95-C-169), and the
`following pending U.S. patent application by Mark A.
`Lysinger entitled: "Burst Counter Circuit And Method of
`Operation Thereof." Ser. No. 08/589,023 (Attorney's
`Docket No. 95-C-141A), all of which have the same effec
`tive filing date and ownership as the present application, and
`to that extent are related to the present application, which are
`incorporated herein by reference.
`FIELD OF THE INVENTION
`This invention is related generally to a burst counter
`circuit and more specifically to a pipelined address scheme
`for storing a second decoded memory address while the
`burst counter circuit is accessing memory locations associ
`ated with a first decoded memory address.
`BACKGROUND OF THE INVENTION
`As synchronous burst SRAMs become more popular,
`market pressure to improve performance is increased. Part of
`the increased performance has been obtained by pipelining
`data. While pipelining data increases the speed at which the
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`FIG.9B is a detailed block diagram of one of the blocks
`of the SRAM of FIG. 9A.
`FIG. 10 is a block diagram of the pipelined column
`address burst counter circuit in accordance with one embodi
`ment of the present invention.
`FIG. 11 is a more detailed block diagram of one embodi
`ment of the pipelined column address burst counter circuit of
`the present invention.
`FIG. 12 is a schematic of the column address input buffer
`and master latch circuit of FIG. 11.
`FIG. 13 is a schematic of the column address driver circuit
`of FIG. 11.
`FIG. 14 is a schematic of the column address predecoder
`circuit of FIG. 11.
`FIG. 15 is a schematic of one embodiment of the column
`address decoder circuit and slave latch circuit of FIG. 11.
`FIG. 16 is a schematic of another embodiment of the
`column address decoder circuit and slave latch circuit of
`F.G. 11.
`FIG. 17 is a schematic of still another embodiment of the
`column address decoder circuit and slave latch circuit of
`F.G. 11.
`FIG. 18 is a functional block diagram of one embodiment
`of the burst counter circuit of FIG. 10.
`FIG. 19 is a functional block diagram of another embodi
`ment of the burst counter circuit of FIG. 10 comprising a
`plurality of latches.
`FIG. 20 is a functional block diagram of still another
`30
`embodiment of the burst counter circuit of FIG. 10 com
`prising a plurality of latches.
`FG. 21 is a schematic of the burst controller of FIG. 10.
`FIG. 22 is a schematic of the column select circuit of FIG.
`10
`FIG. 23 is a block diagram of a computer system includ
`ing a memory device according to the present invention.
`FIGS. 24 and 25 are block diagrams of alternative
`embodiments of computer systems using a memory device
`of the present invention.
`DETALED DESCRIPTION OF THE
`NVENTION
`FIG. 1 shows a memory device 50 having a memory array
`52 thereon.
`The memory array 52 is subdivided into a plurality of
`memory array blocks 54. The memory array 52 is subdi
`vided into as many memory array blocks 54 as desired,
`according to the design. For example, eight blocks, nine
`blocks, or 16 blocks are rather common numbers of array
`blocks 54. In one embodiment, 32 memory array blocks 54
`are formed as shown in FIG. 1. The 32 blocks are grouped
`into four quadrants, each quadrant having eight blocks.
`There are four quadrants on the memory device 50.
`Associated with each memory array block 54 is a respec
`tive block input/output (I/O) circuit 56 and word line drive
`circuit 58. In one embodiment, the word line drive circuit 58
`for two adjacent memory array blocks 54 is positioned in a
`single region between the two adjacent memory array
`blocks. Alternatively, the word line drive circuit 58 can be
`located in the central or peripheral regions of the memory
`device 50. Other circuitry for accessing a memory cell in the
`memory array 52, such as row and address decoders, input/
`output buffers and sense amplifiers are located in the block
`I/O circuitry 56, central regions 60 and 62 and other posi
`tions on the memory device 50 as needed. A plurality of
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`bonding pads 64 are provided in the peripheral region of the
`memory device 50 for connecting to data input/output pins,
`voltage supply lines, address lines and other electrical con
`nections as needed.
`FIGS. 2 and 3 illustrate an embodiment of a read/write
`circuit 69 and a row address circuit 105, respectively, of the
`memory device 50. Each memory array block 54 is provided
`with circuitry for providing data to and from for that
`individual block. In one embodiment, the circuitry of FIGS.
`2 and 3 will be provided for each memory array block 54 so
`that there are 32 such circuits on a single memory device 50.
`Alternatively, for that circuitry which can be shared between
`two memory array blocks 54, only 16 such circuits will be
`needed, as will be apparent to those of skill in the art. In one
`embodiment, the memory device 50 is capable of receiving
`32 bits of data simultaneously and outputting 32 bits of data
`simultaneously. Therefore, all circuitry required to input and
`output 32 bits of data simultaneously is provided, such as 32
`input/output buffers, and the like. The 32 bits can be
`provided by simultaneously accessing one memory cell in
`each of the 32 memory array blocks 54 or, alternatively, by
`accessing 8 memory cells in one memory array block within
`one quadrant and accessing four blocks one within each
`quadrant simultaneously. The circuits shown in FIGS. 2 and
`3 are thus provided for each individual block of the memory
`array 52 and can have a 1 bit bus, an 8 bit bus, a 4 bit bus
`or the like.
`As shown in FIG.2, a data signal line 27 receives data and
`provides the data to a conventional data input buffer 68. The
`data input buffer 68 outputs the data complement DC, on a
`signal line 70 and the data true DT, on a signal line 72. A
`write driver 75 receives the data from the data input buffer
`68 and outputs the data on a pair of signal lines write bit
`complement, WBC74 and write bit true. WBT 76. The data
`input buffer 68 also outputs the data to an output buffer 98
`on line 97. The signal lines WBC 74 and WBT 76 are input
`to a column select circuit 78. The column select circuit 78
`outputs the data on bit line complement BLC 80 and bit line
`true BLT 82 for writing to the memory array blocks 54. A
`burst counter 40 outputs column select signals 130 directly
`to the column select circuit 78 for addressing specific bit
`lines within the memory array block 54. The BLC line 80
`and BLT line 82 are connected to the memory array block.54
`as shown in FIG. 3. The WBC and WBT signal lines 74 and
`76 are also connected to a reset control circuit 84 which
`outputs signal lines RESET 86 and reset bar (RESETB) 88.
`The column select circuit 78 also receives additional input
`signals to control reading and writing data to and from the
`memory array block 54 as explained in more detail with
`respect to FIG. 19. A read bit complement RBC 90 and a
`read bit true RBT92 signal are output by the column select
`circuit 78 and carry the read bit data when the circuitry of the
`memory device 50 is in the read mode. The signals RBC 90
`and RBT 92 are input to a sense amp circuit 94 which
`operates to sense read data in a manner well known in the
`art.
`Referring to FIG. 3, the row address circuit 105 includes
`an address decoder 107 which receives address information
`and outputs decoded address information to a word line and
`block select circuit 104. Additional address decode circuitry
`including an input buffer 106. an even/odd row selector 108
`and a word line select circuit 110 are part of the address
`decode circuitry. The word line select circuit 110 provides
`signals to a local word line driver circuit 112 which outputs
`signals LWL1 and LWL0 to drive individual word lines of
`the memory array block 54. As will be appreciated, the
`appropriate address decoder circuitry for the column address
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`5
`is also provided so that individual memory cells are acces
`sible. Test mode logic 114 is also provided to permit testing
`of the memory device 50.
`FIG. 4 is a schematic diagram of one embodiment of the
`address input buffer 106 of FIG. 3. The address input buffer
`106 receives the odd/even address bit on an input terminal
`600 and provides the buffered odd/even address bit on an
`output terminal 602.
`FIG. 5 is a schematic diagram of one embodiment of the
`even/odd row selector 108 of FIG. 3. A first stage 606
`includes an even number (here 4) inverters that are serially
`coupled between the address input terminal 604 and a row
`address even terminal RA. A mode selection stage 608
`has a number of mode select input terminals coupled to the
`mode terminals FONB, AOPED, AONEO, and FOFFEO, an
`input terminal coupled to the input terminal 604, and an
`output terminal 610. The mode selection stage 608 includes
`switches 612, 614, and 616, which are coupled as shown. A
`second stage 618 includes an odd number (here 3) of
`inverters that are serially coupled between the output ter
`minal 610 and the row address odd terminal RA.
`In operation during a read or write cycle, the switch 612
`is conducting, thus coupling the address bit at the terminal
`604 to the stage 618. The switches 614 and 616 are non
`conducting. If the address bit at the input terminal 604
`indicates that an even row is to be accessed, i.e., the address
`bit is a logic 0, then the stage 606 generates an active logic
`0 for RA and the stage 618 generates an inactive logic
`1 for RA. Thus, the addressed even row is selected, and
`all the remaining even rows and all the odd rows of memory
`cells in the memory blocks 54 are unselected. Conversely, if
`the address bit at the input terminal 604 is a logic 1 to
`indicate that an odd row is to be accessed, then the stage 606
`drives RA to an inactive logic 1. and the stage 618 drives
`RA to an active logic 0. Thus, the addressed odd row is
`selected and the remaining odd rows and all the even rows
`of memory cells in the blocks 54 are unselected.
`FIG. 6 is a schematic diagram of the word line and block
`select circuit 104 of FIG. 3. Only the portion that generates
`the EO signal is shown, it being understood that the
`portion generating the EO signalis similar in construction
`and in operation. In operation, the circuit 104 receives
`RA and generates EO.
`The circuit 104 also receives
`three block address signals BAO. BA1, and BA2 and gen
`erates therefrom a block select signal BS. In one embodi
`ment of the invention, there is one circuit 104 for every two
`memory blocks 54. The signals EO
`and EO are
`common to all the memory blocks 54, and are generated by
`multiple circuits 104 in order to prevent problems such as
`excessive fan-out. Furthermore, in the embodiment of the
`memory device 50 where four (out of 32) memory blocks54
`are accessed at a time, only eight BS signals need be
`generated. Thus, each of these eight BS signals are coupled
`to a corresponding memory block 54 in each of the quad
`rants of the memory device 50.
`FIG. 7 is a schematic diagram of one embodiment of the
`word line select circuit 110 of FIG. 3. In operation, the word
`line select circuit 110 generates RDL from EO
`RDL, from EO, and BS from BS. The signals BS from
`two circuits 110 are coupled to the block read/write control
`circuit 125 (FIG. 2) as block select left BSL and block select
`right BSR, respectively.
`FIG. 8 is a schematic diagram of one embodiment of the
`local word line driver circuit 112 of FIG. 3. The circuit 112
`generates an active logic 1 for LWL, when RDL is a
`logic 0 and MWL and ENABLE are logic 1 and 0, respec
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`tively. Likewise, the circuit 112 generates an active logic 1
`for LWL when RDL is a logic 0 and MWL and
`ENABLE are logic 1 and 0, respectively. In one embodiment
`of the invention, each memory block 54 has 260 rows of
`memory cells and in such an embodiment there are 130 of
`the local word line driver circuits 112 per memory block 54.
`The detailed circuits for each of the blocks shown in
`FIGS. 4 to 8 can be implemented using conventional cir
`cuitry now available for performing such functions. As will
`be appreciated, specific embodiments for such circuitry are
`shown and described in the related applications mentioned
`on page 1 of the present application. However, such detailed
`circuits do not form a part of this present invention and, for
`purposes of this invention, any currently available circuitry
`for carrying out the functions described in the blocks is
`acceptable.
`FIG. 10 is a block diagram of one embodiment of a
`pipelined column address burst counter circuit according to
`principles of the present invention. A column address input
`buffer and master latch circuit 104 receives a column address
`101 directly from input pins of the memory device 50. The
`circuit 104 outputs the column address data on line 12
`labeled OUTC which is input to a column address driver
`106. The column address driver 106 generates true and
`complement address signals corresponding to each address
`provided on the line 12. These include the true column
`address x on line 18, labeled CAxT. and the complement
`column address x on line 16, labeled CAxC. In the present
`embodiment, x is a number from 0 to 13 because there are
`4 addresses that are decoded to selected 16 columns in a
`group. The column address signals, CAxT and CAxC, are
`input to a column predecoder 110. The true column address
`CAxT is also input on a line 28 to a burst controller 30. In
`a preferred embodiment, x=0 on the particular signal line 18
`which is provided to the burst controller 30 so that the burst
`controller receives the least significant address bit from the
`current column address from the column address driver 106.
`The burst controller 30 outputs numerous control signals on
`multiple lines, labeled 38 as a group, to control a column
`address burst counter circuit 40. The details of this imple
`mentation of the burst controller 30 will be described in
`more detail later with respect to FIG. 21.
`The column predecoder 110 receives the signals on lines
`18 and 16 and outputs partially decoded address
`information, labeled Yx on line 22. The partially decoded
`column address information Yx is input to a column address
`decoder circuit 100. The decoded column address data is
`output by the column address decoder circuit 100 on line 26
`and input to the burst counter 40. The burst counter 40
`outputs a column select signal COL. SEL. on line 130 which
`is input to the column select circuit 78. The column select
`circuit 78 shown in FIG. 10 is the same as that shown in FIG.
`2. FIG. 10 depicts the path which the column address
`follows for either writing data to or reading data from the
`memory array 52 via lines 80 and 82 also shown in FIG. 2.
`When data is read from the memory array 52. it is output on
`a read bit true (RBT) line 92 and a read bit complement
`(RBC) line 90 for sensing by a sense amp 94. As shown in
`FIG. 10, the burst controller 30 is coupled to directly receive
`the column address information CAxT from the column
`address driver 106 simultaneously with the column address
`predecoder 110 receiving such information. The burst con
`troller 30 remains coupled to the burst counter 40 to generate
`control signals on line 38 to control the burst counter 40.
`Rather than receiving the decoded column address informa
`tion on line 26, the burst controller 30 receives the column
`address information directly on line 28. According to a
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`NANYA TECHNOLOGY EXHIBIT 1009
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`further alternative embodiment, the burst controller 30 is
`coupled to receive the output on line 26 from the column
`decoder 100 and reencode this output to determine the
`interleaved direction in the event it is operating in the
`interleaved mode.
`FIG. 11 is a more detailed block diagram of another
`embodiment of the present invention. This embodiment is
`similar to that previously described with reference to FIG.
`10. In this embodiment, however, the burst controller 30 is
`coupled to the column address predecoder 110 and receives
`the first stage predecoded address information on line 22.
`The burst controller 30 in this embodiment contains an
`encoder circuit for reestablishing the original column
`address signal from the predecoded column address infor
`mation Yx received on line 22. The burst controller 30
`outputs signals on line 38 to control the burst counter 40 as
`explained in more detail herein.
`The column address signal 101 is input to the column
`address input buffer and master latch circuit 104 o