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`IPR2021-00167
`Nanya Technology Corp. v. Monterey Research, LLC
`Monterey Research LLC Exhibit 2002
`Ex. 2002, Page 1
`
`

`

`
`5,729,504
`
` Page 2
`
`U.S. PATENT DOCUMENTS
`
`
`
`sescesssesssenscasenseavscsess 365/230
`tensy oes yanot AD.
`
`
`
`
`
`
`
`
`
`
`
`
`
`4,685.089
`965/233
`8/1987 Patel tal
`
`
`
`
`
`
`-. 365/239
`11/1987 Takemae etal.
`.
`4,707,811
`
`
`
`
`
`
`
`
`
`
`
`4,788,667
`11/1988 Nakano.........
`w 365/193
`
`
`
`
`
`
`9/1989 Ariaetal. .....
`4,870,622
`w+ 365/230
`
`
`
`
`Snes joyoe Matsumoto “
`meerreye
`
`
`
`
`
`
`
`6/1992 Handy et al.
`wensee 365/230
`5,126,975
`
`
`
`
`
`
`
`
`
`
`
`5,257,200 10/1993 Tobita ......
`a 365/189
`
`
`
`
`
`5,268,865 12/1993 Takasugi
`........sssccssesserrssoseseees 365/189
`3305284 Wiood voung et al. .
`3650385
`
`
`
`
`
`
`
`
`
`6/1994 Morgan5657189.08
`5325330
`
`
`
`
`
`
`
`
`6/1994 MeLauiry
`csscssssccsssssssessssesseesees 395/425
`5,325,502
`
`
`
`
`
`5,349,566
`9/1994 Merritt et al
`365/233.5
`
`
`
`
`
`
`5,357,469 10/1994 Sommeret al
`a» 365/193
`
`
`
`
`
`
`3,373,227 12/1994 Keeth ...........
`a 323/313
`
`
`
`
`
`
`1/1995 Jones,Jr. «2...
`- 365/230
`5,379,261
`
`
`
`
`
`
`Sas 4/1008 eet
`~ 0ios
`2/1995 M
`wo 365/18
`5,392,239
`is
`et al
`
`
`
`
`
`
`
`
`
`
`9/1995 Chung et al
`.. 365/233
`5,452,261
`
`
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`
`
`
`3,457,659 10/1995 Schaefer
`see 365/222
`
`
`
`
`
`
`5,526,320
`6/1996 Zagar etal.
` 365/233.5
`
`
`
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`“Hyper Page Mode DRAM”, 8029 Electronic Engineering,
`
`
`
`
`
`
`
`66, No. 813, Woolwich, London, GB, pp. 47-48, (Sep.
`
`
`
`
`
`
`
`
`1994).
`
`
`
`
`“Mosel—Vitelic V53C8257H DRAM Specification Sheet, 20
`
`
`
`pages, Jul. 2, 1994”,
`
`
`
`
`
`
`“Pipelined Burst DRAM”, Toshiba, JEDECJC42.3Hawaii,
`
`
`(Dec. 1994).
`;
`.
`
`
`
`
`
`Samsung Synchronous DRAM”, Samsung Electronics, pp.
`
`
`
`1—16, (Mar. 1993).
`SYBchronous DRAM 2 MEG x 8 SDRAM”,MicronSemi-
`
`
`
`
`
`
`conductor, Inc., pp. 2-43 through 2-8.
`
`
`
`
`
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`
`
`
`
`
`Dave Bursky, “Novel I/O Options and Innovative Architec-
`
`
`
`
`
`
`
`tures Let DRAMs Achieve SRAM Performance; Fast
`
`
`
`
`
`
`DRAMScan be swapped for SRAM Caches”, Electronics
`
`
`
`
`
`
`
`
`
`Design, vol. 41, No. 15, Cleveland, Ohio, pp. 55-67, (Jul.
`
`
`29, 1993).
`Shiva P. Gowni, et al., “A 9NS, 32K X 9, BICMOS TTL
`:
`:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Synchronous Cache RAM With Burst Mode Access”, [EEE,
`
`
`
`
`
`
`
`Custom Integrated Circuits Conference, pp. 781-786, (Mar.
`
`
`3, 1992).
`
`
`
`
`
`Ex. 2002, Page 2
`
`Ex. 2002, Page 2
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 17, 1998
`
`
`
`
`Sheet 1 of 7
`
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`5,729,504
`
`
`
`
`
`|_| CONTROL
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`
`RAS*
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`
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`(PRIOR ART)
`
`
`
`Ex. 2002, Page 3
`
`Ex. 2002, Page 3
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`

`

`
`U.S. Patent
`
`
`
`
`Mar. 17, 1998
`
`
`
`
`Sheet 2 of 7
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`5,729,504
`
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`Ex. 2002, Page 4
`
`Ex. 2002, Page 4
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`

`

`
`U.S. Patent
`
`
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`
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`
`
`Mar. 17, 1998
`
`
`
`
`Sheet 3 of 7
`
`
`
`€“Old
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`5,729,504
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`
`
`
`Ex. 2002, Page 5
`
`Ex. 2002, Page 5
`
`

`

`
`U.S. Patent
`
`
`
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`
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`Sheet 4 of 7
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`5,729,504
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`
`
`
`
`Mar. 17, 1998
`
`(avuoldd)b“Ol
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`
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`Ex. 2002, Page 6
`
`Ex. 2002, Page 6
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`

`

`U.S. Patent
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`Mar.17, 1998
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`Sheet 5 of 7
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`5,729,504
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`141
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`112
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`Ex. 2002, Page 7
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`Ex. 2002, Page 7
`
`

`

`Mar. 17, 1998
`
`Sheet 6 of 7
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`U.S. Patent
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`g9‘Old
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`5,729,504
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`Ex. 2002, Page 8
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`Ex. 2002, Page 8
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`

`

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`U.S. Patent
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`Mar. 17, 1998
`
`
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`Sheet 7 of 7
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`5,729,504
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`Ex. 2002, Page 9
`
`

`

`5,729,504
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`65
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`
`1
`CONTINUOUS BURST EDO MEMORY
`
`
`
`DEVICE
`
`TECHNICAL FIELD OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`The present invention relates generally to integrated cir-
`
`
`
`
`
`
`
`cuit memories and in particular the presentinvention relates
`to burst access memories.
`
`
`
`
`BACKGROUND OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`A wide variety of integrated circuit memories are avail-
`
`
`
`
`
`
`
`
`
`able for storing data. One type of memory is the dynamic
`
`
`
`
`
`
`random access memory (DRAM). A DRAM is designed to
`
`
`
`
`
`
`
`
`store data in memory cells formed as capacitors. The data is
`
`
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`
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`
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`stored in a binary format; a logical “one” is stored as a
`
`
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`
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`charge on a capacitor, and a logical “zero” is stored as a
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`
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`
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`discharged capacitor. The typical DRAM is arranged in a
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`
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`plurality of addressable rows and columns. To access a
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`
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`memory cell, a row is first addressed so that all memory cells
`
`
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`coupled with that row are available for accessing. After a
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`least ome column can be
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`addressed to pinpoint at least one specific memory cell for
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`either reading data from, or writing data to via external data
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`communication lines. The data stored in the memory cells is,
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`therefore, accessible via the columns.
`
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`
`
`With the constant development of faster computer and
`
`
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`
`
`communication applications,
`the data rates in which a
`
`
`
`
`
`
`
`
`memory circuit must operate continue to increase. To
`
`
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`
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`address the need for increased data rates, a variety of
`
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`DRAMsare commercially available. These memories are
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`produced in a variety of designs which provide different
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`methods of reading from and writing to the dynamic
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`memory cells of the memory. One such method is page
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`mode operation. Page mode operations in a DRAM are
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`defined by the method of accessing a row of a memory cell
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`array and randomly accessing different columnsofthearray.
`Data stored at the row and column intersection can be read.
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`and output while that column is accessed. Page mode
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`DRAMsrequire access steps which limit the communication
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`speed of the memory circuit.
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`An alternate type of memory circuit is the extended data
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`output (EDO) memory which allows data stored at a
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`memory array address to be available as output after the
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`addressed column has been closed. This memory circuit can
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`increase some communication speeds by allowing shorter
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`access signals without reducing the time in which memory
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`output data is available on the communication lines. Column
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`access times are,
`therefore, “masked” by providing the
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`extended data output. A more detailed description of a
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`DRAM having EDO features is provided in the “1995
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`DRAM Data Book” pages 1—1 to 1-30 available from
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`
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`Micron Technology, Inc. Boise, Id., which is incorporated
`
`
`herein by reference.
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`Yet another type of memory circuit is a burst access
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`memory which receives one address of a memory array on
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`external address lines and automatically addresses a
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`sequence of columns without the need for additional column
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`addresses to be provided on the external address lines. By
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`reducing the external address input signals, burst EDO
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`memory circuits (BEDO) are capable of outputting data at
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`significantly faster communication rates than the above
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`described memory circuits.
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`Although BEDO memories can operate at significantly
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`faster data rates than non-burst memories, bursts of output
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`data are terminated when changing from one memory row to
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`another. The alternative to terminating a data burst is to wait
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`until a data burst is complete until the memory row is
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`2
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`changed. Changing memory rows is time consuming and
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`because data is interrupted during the transition between
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`rows, the data rate of the memory circuits is slowed.
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`For the reasons stated above, and for other reasonsstated
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`below which will become apparentto those skilled in the art
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`upon reading and understanding the present specification,
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`there is a need in the art for a burst access memory which
`
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`allows a data burst to continue while receiving and address-
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`ing a new memory row address.
`SUMMARY OF THE INVENTION
`
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`The above mentioned problems with integrated memory
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`circuits and other problems are addressed by the present
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`invention and which will be understood by reading and
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`studying the following specification. A burst access memory
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`device is described which allows a new memory array row
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`to be accessed while continually bursting data out from a
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`In particular, the present invention describes a memory
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`device comprising addressable memory elements, external
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`address inputs, and an address counter for receiving an
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`address on the external address inputs. The address counter
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`also generates a sequence of addresses. The memory further
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`comprises an output buffer adapted to drive a sequence of
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`data from the memory device. The output buffer circuitry
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`can drive the sequence of data from the memory device
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`while a new address is received by the address counter.
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`In one embodiment, the memory includes a write enable
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`signal input for receiving an enable signal, and termination
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`circuitry for terminating an output of the sequence of data.
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`In another embodiment, a memory device is described
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`which comprises addressable memory elements arranged in
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`rows and columns, external address inputs, and address
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`circuitry for receiving row addresses and column addresses
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`from the external address inputs. Counter circuitry is
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`included for generating a sequence of column addresses in
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`response to a first received column address. The memory
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`also includes row access circuitry for accessing a row of
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`memory elements in responseto a received first row address,
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`the memory device. The sequence of data being stored in the
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`addressable memory elements having addresses correspond-
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`ing to the sequence of addresses and the first row address.
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`The memory further includes control circuitry for control-
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`ling the output buffer circuitry and the access circuitry,
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`wherein a second row of memory elements can be accessed
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`without interrupting the output sequence of data from the
`first row address.
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`In yet another embodiment, a method of burst reading
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`data from a memory device having addressable memory
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`elements arranged in rows and columns is described. The
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`method comprisesthe steps of receiving a first row address,
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`receiving a first column address, and accessing a row of
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`memory elements having the first row address. The method
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`also includes the steps of generating a sequence of column
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`addresses starting at the first column address, outputting data
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`stored at the sequence of column addresses, receiving a
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`second row address, and accessing a row of memory ele-
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`ments having the second row address while outputting the
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`data stored at the sequence of column addresses.
`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a block diagram of a memory device incorpo-
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`rating burst access;
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`FIG. 2 illustrates linear and interleaved addressing
`sequences;
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`Ex. 2002, Page 10
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`Ex. 2002, Page 10
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`

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`5,729,504
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`FIG. 3 is a timing diagram of a burst read followed by a
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`burst write of the device of FIG. 1;
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`FIG. 4 is a timing diagram of a burst write followed by a
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`burst read of the device of FIG. 1;
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`FIG.5 is a block diagram of a memary device incorpo-
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`rating the features of the present invention;
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`FIG. 6a is a timing diagram ofthe operation of the device
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`of FIG. 5;
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`FIG. 6d is a continuation of the timing diagram of FIG.
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`6a;
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`FIG.7a is a timing diagram ofa series of continuousburst
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`read operations; and
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`FIG. 7b is a timing diagram of a series of burst read
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`operations.
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`DETAILED DESCRIPTION OF THE
`INVENTION
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`In the following detailed description of the preferred
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`embodiments, reference is made to the accompanying draw-
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`ings which form a part hereof, and in which is shown by way
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`of illustration specific preferred embodiments in which the
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`inventions may be practiced. These embodiments are
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`described in sufficient detail to enable those skilled in the art
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`to practice the invention,andit is to be understood that other
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`embodiments may be utilized and that logical, mechanical
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`and electrical changes may be made without departing from
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`the spirit and scope of the present inventions. The following
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`detailed descriptionis, therefore, not to be takenin a limiting
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`sense, and the scope of the present inventionsis defined only
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`by the appended claims.
`BEDO Memories
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`invention, a detailed
`To fully understand the present
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`description is provided of a burst extended data output
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`memory circuit (BEDO). FIG. 1 is a schematic representa-
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`tion of a sixteen megabit device designed to operate in a
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`burst access mode. The device is organized as a 2 Megx8
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`burst EDO DRAM having an eightbit data input/output path
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`10 providing data storage for 2,097,152 bytes of information
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`in the memory array 12. An active-low row address strobe
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`(RAS*) signal 14 is used to latch a first portion of a
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`multiplexed memory address, from address inputs AO
`45
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`through A1@ 16, in latch 18. The latched row address 20 is
`decoded in row decoder 22. The decoded row addressis used
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`to select a row of the memory array 12. An active-low
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`column address strobe (CAS*) signal 24 is used to latch a
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`second portion of a memory address from address inputs 16
`into column address counter 26. The latched column address
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`28 is decoded in column address decoder 30. The decoded
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`column address is used to select a column of the memory
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`array 12.
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`In a burst read cycle, data within the memory array
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`located at the row and column address selected by the row
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`and column address decoders is read out of the memory
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`array and sent along data path 32 to output latches 34. Data
`10 driven from the burst EDO DRAM maybe latched
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`external to the device with a CAS* signal after a predeter-
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`mined number of CAS* cycle delays (latency). For a two
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`cycle latency design, the first CAS* failing edge during a
`RAS*cycle is used to latch the initial address for the burst
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`access. Thefirst burst data from the memory is driven from
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`the memory after the second CAS*falling edge, and remains
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`valid through the third CAS* failing edge. Once the memory
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`device begins to output data in a burst read cycle, the output
`drivers 34 will continue to drive the data lines without
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`4
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`tri-stating the data outputs during CAS* high intervals
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`dependent on the state of the output enable 42 and write
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`enable 36 (OE* and WE*) control lines, thus allowing
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`additional time for the system to latch the output data. Once
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`a row and a column address are selected, additional transi-
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`tions of the CAS* signal are used to advance the column
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`address within the column address counter in a predeter-
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`mined sequence. The time at which data will be valid at the
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`outputs of the burst EDO DRAM is dependent only on the
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`timing of the CAS* signal provided that OE* is maintained
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`low, and WE* remains high. The output data signal levels
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`may be driven in accordance with standard CMOS, TTL,
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`LVTTL, GTL, or HSTL output level specifications.
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`The address may be advanced linearly, or in an inter-
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`leaved fashion for maximum compatibility with the overall
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`system requirements. FIG. 2 is a table which shows linear
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`andinterleaved addressing sequences for burst lengths of 2,
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`4 and 8 cycles, The “V” for starting addresses A1 and A2 in
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`the table represent address values that remain unaltered
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`through the burst sequence. The column address may be
`advanced with each CAS* transition. When the address is
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`advanced with each transition of the CAS* signal, data is
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`also driven from the part after each transition following the
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`device latency which is then referenced to each edge of the
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`CAS* signal. This allows for a burst access cycle where
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`CAS*toggles only once (high to low or low to high) for each
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`memory cycle. This is in contrast to standard DRAMswhich
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`require CAS* to go low and then high for each cycle, and
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`synchronous DRAMswhich require a full CAS* cycle (high
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`and low transitions) for each memory cycle.
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`In the burst access memory device, each new column
`address from the column address counter is decoded and is
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`used to access additional data within the memory array
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`without the requirement of additional column addresses
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`being specified on the address inputs 16. This burst sequence
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`of data will continue for each CAS* failing edge until a
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`predetermined number of data accesses equal to the burst
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`length has occurred. A CAS*falling edge received after the
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`last burst address has been generated will latch another
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`column address from the address inputs 16 and a new burst
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`sequence will begin. Read data is latched and output with
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`each falling edge of CAS*after the first CAS* latency. For
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`a burst write cycle, data 10 is latched in input data latches
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`34. Data targeted at the first address specified by the row and
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`column addressesis latched with the CAS* signal when the
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`first column address is latched (write cycle data latency is
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`zero). Other write cycle data latency values are possible;
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`however. for today’s memory systems, zero is preferred.
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`Additional input data words for storage at incremented
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`column address locations are latched by CAS* on successive
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`CAS*pulses. Input data from the inputlatches 34 is passed
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`along data path 32 to the memory array where itis stored at
`the location selected by the row and column address decod-
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`ers. As in the burst read cycle previously described, a
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`predetermined number of burst access writes will occur
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`without the requirement of additional column addresses
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`being provided on the address lines 16. After the predeter-
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`mined number of burst writes has occurred, a subsequent
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`CAS* will latch a new beginning column address, and
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`another burst read or write access will begin.
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`Control circuitry 38, in addition to performing standard
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`DRAM control functions, controls the I/O circuitry 34 and
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`the column address counter/latch 26. The control circuity
`determines when a current data burst should be terminated
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`based uponthestate of RAS* 14, CAS* 24 andWE* 36. The
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`write enable signal is used in burst access cycles to select
`read or write burst accesses whentheinitial column address
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`25
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`30
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`50
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`55
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`65
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`Ex. 2002, Page 11
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`Ex. 2002, Page 11
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`

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`5
`6
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`for a burst cycle is latched by CAS*. WE* low at the column
`either an interleaved or sequential manner. On the fifth
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`address latch time selects a burst write access. WE* high at
`CAS* falling edge a new column address and associated
`the column address latch time selects a burst read access.
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`write data are latched. The burst write access cycles continue
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`Thelevel of the WE* signal must remain high for read and
`until the WE* signal goes high in the sixth—CAS* cycle.
`5
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`low for write burst accesses throughout the burst access. A
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`Thetransition of the WE* signal terminates the burst write
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`low to high transition within a burst write access will
`access. The seventh CAS* low transition latches a new
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`terminate the burst access, preventing further writes from
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`column address and begins a burst read access (WE* is
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`occurring. A high to low transition on WE* within a burst
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`high). The burst read continues until RAS* rises terminating
`tread access will likewise terminate the burst read access and
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`the burst cycles.
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`will place the data output 10 in a high impedance state.
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`Continuous BEDO (CBEDO)
`Transitions of the WE* signal may be locked out during
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`critical timing periods within an access cycle in order to
`FIG. 5 illustrates a continuous memory circuit which
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`reduce the possibility of triggering a false write cycle. After
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`includes all of the features of the standard BEDO memory
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`the critical timing period, the state of WE* will determine
`as described above. The continuous memory circuit,
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`whether a burst access continues, is initiated, or is termi-
`however, operates differently than the previously described
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`nated. Termination of a burst access resets the burst length
`BEDO memory when the row access signal (RAS*) is
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`counter and places the DRAM inastate to receive another
`inactive. That is, as explained above, a burst access opera-
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`burst access command.In the case of burst reads, WE* will
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`tion is terminated when the RAS* and the CAS* signals go
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`transition from high to low to terminatea first burst read, and
`high in a standard BEDOcircuit. Time specifications for the
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`then WE* will transition back high prior to the next falling
`BEDO circuitry dictates that the RAS* signal remain high
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`edge of CAS* in order to specify a new burst read cycle. For
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`for a minimum time of Tpp (precharge time). Further, a
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`burst writes, WE* would transition high to terminate a
`minimum access time T,;,4-, measured from the falling edge
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`current burst write access, then back low prior to the next
`of RAS*, is required to access the new row. Asa result, a
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`falling edge of CAS*to initiate another burst write access.
`new memory row cannotbe accessed until a minimum time
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`Both RAS* and CAS* going high during a burst access will
`Of TractTgp has passed following the rising edge of RAS*.
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`also terminate the burst access cycle placing the data drivers
`Typical times for Te,c and Trp are 60 ns and 40 ns,
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`in a high impedance output state, and resetting the burst
`respectively. To eliminate this 100 ns time period in which
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`length counter.
`data is not being provided as output, circuitry is provided in
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`A basic implementation of the device of FIG. 1 may
`control 139 of the memory circuit.
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`include a fixed burst length of 4, a fixed CAS* latency of 2
`FIG.5 is a schematic representation of a sixteen megabit
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`and a fixed interleaved sequence of burst addresses. Further,
`device designed to operate in a burst access mode and
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`just as fast page mode DRAMs and EDO DRAMsare
`incorporating the features of present invention. The device is
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`available in numerous configurations including x1, x4, x8
`organized as a 2 Megx8 burst EDO DRAM having an eight
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`and x16 data widths, and 1 Megabit, 4 Megabit, 16 Megabit
`bit data input/output path 11@ providing data storage for
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`and 64 Megabit densities; the burst access memory device of
`2,097,152 bytes of information in the memory array 112. An
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`FIG. 1 may take the form of many different memory
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`active-low row address strobe (RAS*) signal 114 is used to
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`organizations.
`latch a first portion of a multiplexed memory address, from
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`FIG. 3 is a timing diagram for performing a burst read
`address inputs AO through A10 116,
`in latch 118. The
`latched row address 120 is decoded in row decoder 122. The
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`followed by a burst write of the device of FIG. 1. In FIG. 3,
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`a row address is latched by the RAS* signal. WE* is low
`decoded row address is used to select a row of the memory
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`when RAS*falls for an embodimentof the design where the
`array 112. An active-low column address strobe (CAS*)
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`state of the WE* pin is used to specify a burst access cycle
`signal 124 is used to latch a second portion of a memory
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`at RAS* time. Next, CAS* is driven low with WE* high to
`address from address inputs 116 into column address counter
`126. The latched column address 128 is decoded in column
`initiate a burst read access, and the column address is
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`address decoder 130. The decoded column address is used to
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`latched. The data out signals (DQ’s) are not driven in the
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`first CAS* cycle. On the second falling edge of the CAS*
`select a column of the memory array 112.
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`signal, the internal address generation circuitry advances the
`In a burst read cycle, data within the memory array
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`column address and begins another access of the array, and
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`located at the row and column address selected by the row
`the first data out is driven from the device after a CAS* to
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`and column address decoders is read out of the memory
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`data access time (Tc,4c)- Additional burst access cycles
`array and sent along data path 132 to output latches 134.
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`continue, for a device with a specified burst length of four,
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`Data 110 driven from the burst EDO DRAM maybelatched
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`until the fifth failing edge of CAS* which latches a new
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`external to the device with a CAS* signal after a predeter-
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`column address for a new burst read access. WE*falling in
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`mined number of CAS* cycle delays (latency). Once the
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`the fifth CAS* cycle terminates the burst access, and ini-
`memory device begins to output data in a burst read cycle,
`tializes the device for additional burst accesses. The sixth
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`the output drivers 134 will continue to drive the data lines
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`falling edge of CAS* with WE* low is used to latch a new
`without tri-stating the data outputs during CAS* high inter-
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`burst address, latch input data and begin a burst write access
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`vals dependent on the state of the output enable and write
`of the device. Additional data values are latched on succes-
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`enable (OR* and WE*) control lines, thus allowing addi-
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`sive CAS* failing edges until RAS* rises to terminate the
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`tional time for the system to latch the output data. Once a
`burst access.
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`row and a column address are selected, additional transitions
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`FIG. 4 is a timing diagram depicting burst write access
`of the CAS* signal are used to advance the column address
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`cycles followed by burst read cycles. As in FIG.3, the RAS*
`within the column address counter in a predetermined
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`signal is used to l