ERIK CHMELAR, PhD, PE, MBA, JD, PMP, PMI-ACP
`(650) 533-7952 | echmelar@yahoo.com
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`I am a technology expert with over 20 years of industry experience in semiconductor electronics,
`including digital circuitry, programmable devices, microcontrollers, and telecommunications.
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`CREDENTIALS
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`EDUCATION —
`  PhD, Electrical Engineering, Stanford University, Stanford, CA
` Dissertation: “Test and Diagnosis of Field-programmable Gate Arrays,” advised by E. J. McCluskey.
`  MS, Electrical Engineering, Stanford University, Stanford, CA
`  BS, Electrical Engineering, Michigan Technological University, Houghton, MI
`  BS, Chemical Physics, Saginaw Valley State University, University Center, MI
`  MBA, Management, Western Michigan University, Kalamazoo, MI
`  JD, Intellectual Property, University of Michigan Law School, Ann Arbor, MI
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`LICENSES AND CERTIFICATIONS —
`  Licensed Professional Engineer (PE, State of Michigan)
`  Certified Project Management Professional (PMP)
`  Agile Certified Practitioner (PMI-ACP)
`  Licensed Patent Attorney (State Bar of Michigan, USPTO)
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`Jan. 2020 – Jun. 2020
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`EXPERIENCE
`Aug. 2007 – present
`Independent Consultant, Midland, MI (part time)
`  Provide expert IP services to practicing companies and non-practicing entities (NPEs).
`  Draft and prosecute patent applications, mine patent portfolios, and create infringement/use charts.
`  Recent technology areas include programmable hardware, microcontrollers, and smart-card systems.
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`Murphy, Bilak & Homiller, PLLC., Cary, NC
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`Senior Associate, Patent Prosecution
`  Prosecuted patent applications for industry-leading wireless and semiconductor corporations.
`  Drafted approx. 100 office-action responses for complex 5G technologies.
`  Analyzed ETSI 3GPP specifications for prosecution of standard essential patents (SEPs).
`
`InterDigital Communications, Inc., Wilmington, DE
`Sr. Manager, Innovation Partners
`  Created patent portfolios for 5G, IoT, connected/autonomous vehicles, and augmented/virtual reality.
`  Managed scientists and engineers to create over 100 new invention disclosures / patent applications.
`  Forged research partnerships with commercial and academic organizations to develop patent portfolios.
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`Dera Industries LLC., Midland, MI
`Co-founder, Managing Member
`  Developed and productized the award-winning One-TieTM re-usable tie strap.
`  Achieved $1 million in annual sales prior to licensing the intellectual property.
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`Stryker Corp., Kalamazoo, MI
`Sr. Principal Engineer, Advanced Development
`  Supervised R&D of disruptive medical instruments and surgical technologies.
`  Formalized new business opportunities, developed budgets and timelines, and staffed project teams.
`  Collaborated with several top-tier universities to bring necessary expertise into the organization.
`  Delivered working prototypes for biophotonic devices and boundary-constraint surgical robotics.
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`Feb. 2012 – Mar. 2015
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`Sep. 2015 – Oct. 2018
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`May 2016 – Jul. 2017
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`NANYA TECHNOLOGY EXHIBIT 1004
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`Jul. 2004 – Jan. 2012
`LSI Corp. (Broadcom), Milpitas, CA
`Staff Software Engineer, Advanced Technology Development
`  Conducted R&D for very large scale integrated (VLSI) and serializer-deserializer (SerDes) circuits.
`  Granted approx. 20 patents for physical (PHY) interfaces, SerDes, and VLSI test architectures.
`  Made cutting-edge contributions in SerDes and test that were implemented in customer designs.
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`Saginaw Valley State University, University Center, MI (part time)
`Adjunct Professor, Electrical and Computer Engineering
`  Taught courses in digital circuits, computer architecture and organization, and data communications.
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`Stanford University, Stanford, CA (part time)
`Consulting Assistant Professor, Electrical Engineering
`  Advised PhD students on the test and reliability of VLSI circuits.
`  Taught a PhD-level course on clock and data recovery (CDR) for high-speed serial communications.
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`Xilinx, Inc., Los Gatos, CA (PhD. Intern, two summers)
`Product Test Engineer
`  Engineered tools to detect and diagnose defects in FPGAs, which reduced diagnosis time by 75%.
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`Cisco Systems, Inc., San Jose, CA
`Manufacturing Engineer
`  Oversaw functional testing of layer-2/3 network switches and determined root-cause failures.
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`Jan. 2009 – Jan. 2012
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`Sep. 2006 – Aug. 2008
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`Jun. 2002 – Sep. 2003
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`Nov. 1999 – Apr. 2002
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`SERVICE AND MENTORING
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`University of Michigan Law School, Ann Arbor, MI
`Admissions Representative
`  Advised prospective law students at 30 law fairs and forums.
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`National Science Foundation, Western Michigan University I-Corps, Kalamazoo, MI
`Instructor
`  Taught Lean Startup and Business Canvas fundamentals to a cohort of 30 entrepreneurs.
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`Accreditation Board of Engineering and Technology (ABET), Baltimore, MD
`Engineering Program Evaluator
`  Evaluated electrical computer engineering educational programs.
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`National Science Foundation, University of Michigan I-Corps, Ann Arbor, MI
`Industry Mentor
`  Mentored teams of medical-device entrepreneurs participating in the I-Corps program.
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`Western Michigan University, Starting Gate Accelerator, Kalamazoo, MI
`Industry Mentor
`  Mentored entrepreneurs participating in the university startup-accelerator program.
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`2018
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`2015
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`2013 – 2014
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`2013
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`2013
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`PROFICIENCIES
`  Hardware – Verilog, VHDL, ASICs, FPGAs
` Software – C/C++, Objective-C, Java, MatLab
`  Engineering – COMSOL, ANSYS
` CAD – SolidWorks, AutoCAD, Blender
`  Legal research– Lexis, Westlaw, Innography
` Legal Productivity – Foundation IP, Anaqua, Clio
`  Creativity – Illustrator, Photoshop, Premiere
` Foreign languages – German, Czech
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`Page 2 of 2
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`NANYA TECHNOLOGY EXHIBIT 1004
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`List Publications by Erik Chmelar
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`E. Chmelar, “Error signature analysis (ESA) receiver architecture for data communication,”
`DesignCon, 2012.
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`E. Chmelar and C. Ito, “Mostly digital SerDes (MDS): a comprehensive low power receiver
`architecture,” DesignCon, 2012.
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`I. Park, D. Lee, E. Chmelar, and E. McCluskey, “Inconsistent fails due to limited tester timing
`accuracy,” Proc. 26th VLSI Test Symp., 2008.
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`A. Al-Yamani, N. Devta-Prasanna, E. Chmelar, M. Grinchuk, and A. Gunda, “Scan test cost and
`power reduction through systematic scan reconfiguration,” IEEE Trans. Computer-Aided
`Design of Integrated Circuits and Systems, vol. 26, pp. 907–918, 2007.
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`A. Al-Yamani, E. Chmelar, and M. Grinchuk, “Segmented addressable scan architecture,” Proc.
`23rd VLSI Test Symp., 2005.
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`E. Chmelar, “Minimizing the number of test configurations for FPGAs,” Int. Conf. Computer
`Aided Design, 2004.
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`E. Chmelar, “The test and diagnosis of FPGAs,” Ph.D. thesis, Stanford University, 2004.
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`E. Chmelar and S. Toutounchi, “FPGA bridging fault detection and location via differential
`IDDQ,” Proc. 22nd VLSI Test Symp., 2004.
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`E. Chmelar, “Subframe multiplexing: FPGA manufacturing test time reduction,” CRC TR-04-01,
`2004.
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`E. Chmelar, “Subframe multiplexing for FPGA manufacturing test,” Proc. Int. Symp. FPGAs,
`2004.
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`E. Chmelar, “FPGA interconnect delay fault testing,” Proc. Int. Test Conf., pp. 1239–1247,
`2003.
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`Page 1 of 3
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`NANYA TECHNOLOGY EXHIBIT 1004
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`List of US Patents by Erik Chmelar
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`US6920621B1 , “Methods of testing for shorts in programmable logic devices using relative
`quiescent current measurements,” issued 2005-07-19.
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`US6979142B1, “Retractable tip mechanical pencil assembly,” issued 2005-12-27.
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`US7093842B2, “Skateboard truck assembly, “issued 2006-08-22.
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`US7206983B2, “Segmented addressable scan architecture and method for implementing scan-
`based testing of integrated circuits,” issued 2007-04-17.
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`US7210083B2, “System and method for implementing postponed quasi-masking test output
`compression in integrated circuit,” issued 2007-04-24.
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`US7293312B2, “Multipurpose skateboard tool,” issued 2007-11-13.
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`US7328386B2, “Methods for using checksums in X-tolerant test response compaction in scan-
`based testing of integrated circuits,” issued 2008-02-05.
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`US7656339B2, “Systems and methods for analog to digital conversion,” issued 2010-02-02.
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`US7656340B2, “Systems and methods for pipelined analog to digital conversion,” issued 2010-
`02-02.
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`US7696915B2, “Analog-to-digital converter having reduced number of activated comparators,”
`issued 2010-04-13.
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`US7779320B2, “Low power scan shifting with random-like test patterns,” issued 2010-08-17.
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`US7973692B2, “Systems and methods for synchronous, retimed analog to digital conversion,”
`issued 2011-06-07.
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`US7956790B2, “Systems and methods for synchronous, retimed analog to digital conversion,”
`issued 2011-07-05.
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`US8121186B2, “Systems and methods for speculative signal equalization,” issued 2012-02-21.
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`US8432250B2, “Process variation based microchip identification,” issued 2013-04-30.
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`US8527912B2, “Digitally obtaining contours of fabricated polygons,” issued 2013-09-03.
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`US8615062B2, “Adaptation using error signature analysis in a communication system,” issued
`2013-12-24.
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`US8923382B2, “Tap adaptation with a fully unrolled decision feedback equalizer,” issued 2014-
`12-30.
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`US8929497B2, “Dynamic deskew for bang-bang timing recovery in a communication system,”
`issued 2015-01-06.
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`NANYA TECHNOLOGY EXHIBIT 1004
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`US8982941B2, “Predictive selection in a fully unrolled decision feedback equalizer,” issued
`2015-03-17.
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`US9014313B2, “Error signature analysis for data and clock recovery in a communication
`system,” issued 2015-04-21.
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`US9087157B2, “Low-loss transmission line TDM communication link and system,” issued
`2015-07-21.
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`US9292644B2, “Row based analog standard cell layout design and methodology,” issued 2016-
`03-22.
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`US10258706B2, “Sterilization container capable of providing an indication regarding whether or
`not surgical instruments sterilized in the container were properly sterilized,” issued 2019-04-
`16.
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`US10604317B2, “Reusable tie strap with multiple apertures,” issued 2020-03-31.
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`US10731698B2, “Hook device with rotatable opposing jaws,” issued 2020-08-04.
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`NANYA TECHNOLOGY EXHIBIT 1004
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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