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`
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`March 11, 2020
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`THIS IS TO CERTIFY THAT ANNEXED IS A TRUE COPY FROM THE
`
`RECORDS OF THIS OFFICE OF THE FILE WRAPPER AND CONTENTS
`
`OF:
`
`APPLICATION NUMBER: 09/504,344
`
`FILING DATE: February 14, 2000
`
`PATENT NUMBER: 6,651,134
`
`ISSUE DATE: November 18, 2003
`
`
`
`
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`
`
`‘ THE UNITED STATES OFARIERICA f \
`'
`.- mmemmmwnmmass mmma
`UNITED STATES DEPARTMENT OF COMMERCE
`
`United States Patent and Trademark Office
`
`
`
`
`By Authority of the
`
`Under Secretary of Commerce for Intellectual Property
`and Director of the United States Patent and Trademark Office
`
`“Wilt/[0%TG
`
`Certifying Officer
`
`
`
`nn'lrrmmmnrrrrrrrmmflnfllfl'lml'l]|]llll_l1'lll1lllll1|l'||'l|"Irlllll'flflfll'l'lll'l'fllllm'l'lflllflll'lmm
`
`
`
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`
`
`1002 —-I
`V I =
`V
`I V . .
`-
`‘A V V
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`0325.00309 5
`CD99073
`
`,//
`
`FIXED BU ST MEMORIES
`
`
`
`\/
`Field of the Invention
`
`The present invention relates to memory devices generally
`
`and, more particularly,
`
`to a memory device that transfers a fixed
`
`number of words of data with each access.
`
`
`
`
`
`ii13
`
`
`
`Background of the Invention
`
`A synchronous Static Random Access Memory
`
`(SRAM)
`
`can
`
`provide data from multiple address
`
`locations using a
`
`single
`
`address. Accessing multiple locations in response to a single
`
`address is called a hmrst mode access.
`
`.A memory device that
`
`provides a burst mode can reduce activity‘ on the address and
`
`control buses.
`
`The burst mode of a conventional synchronous SRAM
`
`can be started and stopped in response to a control signal.
`
`A conventional Dynamic Random Access Memory
`
`(DRAM)
`
`preserves data during periodic absences of power by implementing a
`
`memory cell as a capacitor and an access transistor.
`
`Since the
`
`charge on the capacitor will slowly leak away,
`
`the cells need to be
`
`20
`
`“refreshed”
`
`once
`
`every few milliseconds.
`
`Depending on
`
`the
`
`frequency of accesses, a conventional DRAM can need an interrupt to
`
`l
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`4/
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
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`perform data refreshes. Using a DRAM in a burst application is
`
`difficult because of
`
`the need to refresh.
`
`Completely' hiding
`
`refresh cycles
`
`(e.g.,
`
`refreshing data without
`
`the need for
`
`interrupts)
`
`in.
`
`a DRAM cannot happen with conventional memory
`
`5
`
`devices due to architecture choices that have been made. Data word
`
`bursts can be interrupted while in progress since conventional
`
`architectures
`
`support
`
`both burst
`
`and
`
`single
`
`access modes.
`
`Conventional DRAM access takes about
`
`lOns to get data, but nearly
`
`20ns
`
`to complete writeback and equalization.
`
`The addition of
`
`another 20ns for a refresh results in a total access of 40ns.
`
`Since the data burst transfers of conventional memories
`
`can be interrupted and single accesses made,
`
`the amount of time
`
`that the data, address and control busses are not in use can vary.
`
`The variability' of bus availability' complicates the design. of
`
`
`
`15
`
`systems with shared data, address and control busses.
`
`It would be desirable to have a memory device that has a
`
`fixed burst length.
`WV/‘Vm
`
`Summary of the Invention
`
`20
`
`The present
`
`invention concerns an integrated circuit
`
`comprising a memory and a logic circuit.
`
`The memory may comprise
`
`2
`
`I”!
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`3/
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
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`a plurality of storage elements each configured to read and write
`
`data in response to an internal address signal.
`
`The logic circuit
`
`m.r,/««\\
`may’ be configured to generate a predetermined number of
`
`the
`
`internal address signals in response to (i)
`
`an external address
`
`signal,
`
`(ii) a clock signal and (iii) one or more control signals.
`
`The generation of
`
`the predetermined number of
`
`internal address
`
`signals may be non—interruptible.
`\/k//oflw
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`
`
`1Q.11!)
`
`mum
`
`
`
`15
`
`The objects,
`
`features and advantages of
`
`the present
`
`invention include providing a fixed burst memory that may (i) give
`
`network customers who
`
`typically’ burst
`
`large data lengths the
`
`ability to set a fixed burst
`
`length that suits particular needs;
`
`(ii) have non-interruptible bursts;
`
`(iii) free up the address bus
`
`and
`
`control
`
`bus
`
`for
`
`a
`
`number
`
`of
`
`cycles;
`
`(iv)
`
`provide
`
`programmability for setting the burst
`
`length by using DC levels
`
`[Vss or Vcc] on external pins;
`
`(v) hide required DRAM refreshes
`
`inside a known fixed. burst
`
`length. of data words;
`
`and/or‘
`
`(vi)
`
`operate at higher frequencies without needing interrupts to perform
`
`refreshes of data.
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYATECHNOLOGYCORP.V.MONTEREYRESEARCHJLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`Brief Description of the Drawings
`
`These and other objects, features and advantages of the
`
`present
`
`invention will be apparent
`
`from the following detailed
`
`description and the appended claims and drawings in which:
`
`5
`
`FIG.
`
`I
`
`is a block diagram illustrating a preferred
`
`embodiment of the present
`
`invention;
`
`FIG. 2 is a detailed block diagram illustrating a circuit
`
`
`25““0u11;;H11
`
`’_|
`
`
`
`1;.
`
`102 of FIG. 1;
`
`FIG.
`
`3
`
`is a detailed block diagram of a circuit 102’
`
`illustrating an alternative embodiment of the circuit 102 of FIG.
`
`1,-
`
`FIG.
`
`4
`
`is a flow diagram illustrating an example burst
`
`address sequence;
`
`FIGS.
`5A and
`5B are diagrams
`illustrating example
`operations of a 4 word (FIG.
`5A)
`and an 8 word (FIG.
`5B)
`fixed
`
`burst access in accordance with the present
`
`invention; and
`
`FIG.
`
`6
`
`is a diagram illustrating an example operation
`
`where a burst length may be long enough to include a writeback and
`
`a refresh cycle.
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`0325 . 00309
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`Detailed Description of the Preferred Embodiments
`
`Referring to FIG. 1, a block diagram of a circuit 100 is
`
`shown in accordance with a preferred embodiment of
`
`the present
`
`invention.
`
`The circuit 100 may be implemented,
`
`in one example, as
`
`5
`
`a
`
`fixed burst memory.
`
`‘The circuit
`
`100 may' be configured to
`
`iiI)
`
`
`
`
`transfer a fixed number of words of data with each access (e.g ,
`
`read or write).
`
`A number of words transferred as a group is called
`
`a burst.
`
`The circuit 100 generally comprises a circuit 102 and a
`
`memory array (or circuit) 104. The circuit 102 may be implemented,
`
`in one example, as a burst address counter/register.
`
`The memory
`
`array 104 may be implemented,
`
`in one example, as a static random
`
`access memory (SRAM),
`
`a dynamic random access memory (DRAM), or
`
`other appropriate memory
`
`to meet
`
`the design criteria of
`
`a
`
`particular implementation.
`
`The circuit 102 may have an input 106 that may receive a
`
`signal
`
`(e.g., ADDR_EXT),
`
`an input 108 that may receive a signal
`
`(e.g., LOAD), an input 110 that may receive a signal
`
`(e.g , CLK),
`
`an input 112 that may receive a signal
`
`(e.g., ADV), and an input
`
`114 that may receive a signal
`
`(e.g., BURST).
`
`The circuit 102 may
`
`20
`
`have an output 116 that may present a signal
`
`(e g., ADDR_INT)
`
`to an
`
`input 118 of the memory 104.
`
`The memory 104 may have an input 120
`
`5A
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`0325 . 00309
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`that may receive a signal
`
`(e.g., R/Wb),
`
`an input 122 that may
`
`receive a signal (e.g., DATA_IN§ and an output 122 that may present
`
`a signal (e.g., DATA_OUT).
`
`The various signals are generally “on”
`
`(e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or O).
`
`5
`
`However,
`
`the particular polarities of the on (e.g., asserted) and
`
`off
`
`(e.g., de—asserted)
`
`states of
`
`the signals may be adjusted
`
`(e.g.,
`
`reversed)
`
`accordingly to meet
`
`the design criteria of
`
`a
`
`
`ii1;ii3ii;;;..
`
`I;H
`
`10
`
`
`
`
`
`particular implementation.
`
`The signal ADDR_EXT may be,
`
`in one example, an external
`
`address signal. The signal ADDR_EXT may be n—bits wide, where n is
`
`an integer.
`
`The signal CLK may be a clock signal. The signal R/Wb
`
`may be a control signal that may be in a first state or a second
`
`state. When the signal R/Wb is in the first state,
`
`the circuit 100
`
`will generally read data
`
`from the memory circuit
`
`104
`
`for
`
`15
`
`presentation as the signal DATA_OUT. When the signal R/Wb is in
`
`the second state,
`
`the circuit
`
`100 will generally' store data
`
`received as the signal DATA_IN.
`
`The signal LOAD may be,
`
`in one example, an address load
`
`control signal.
`
`The circuit 100 may be configured to load an
`
`20
`
`initial address, presented by the signal ADDR_EXT,
`
`in response to
`
`the signal LOAD.
`
`The initial address may determine the initial
`
`6
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`0325.00309
`CD99073
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`location where data transfers to and from the memory 104 will
`
`generally begin.
`
`The signal ADV may be,
`
`in one example, used as a control
`
`signal.
`
`The circuit 100 may be configured to transfer a fixed
`
`number of words
`
`to or
`
`from the memory 104
`
`in response to the
`
`signals ADV, CLK and R/Wb. When the signal ADV is asserted,
`
`the
`
`circuit
`
`100 will generally‘ begin.
`
`transferring a predetermined
`
`number of words.
`
`The transfer is generally non—interruptible.
`p/”\//WV/N
`
`In
`
`one example,
`
`the signal ADV may initiate the generation of a number
`
`of addresses for presentation as the signal ADDR_INT.
`
`The signals ADV and LOAD may be,
`
`in one example, a single
`
`signal (e.g., ADV/LDb). The signal ADV/LDb may be a control signal
`
`that may be in a first state or a second state. When the signal
`
`ADV/LDb is in the first state,
`
`the circuit 102 will generally load
`
`an address presented by the signal ADDR_EXT as an initial address.
`
`When the signal ADV/LDb is in the second state,
`
`the circuit 102 may
`
`be configured to generate the signal ADDR_INT as a fixed number of
`
`addresses in response to the signal CLK.
`
`The signal ADDR*INT may
`
`
`
`be,
`
`in one
`
`example,
`
`an internal address signal.
`
`The
`
`signal
`
`2O
`
`ADDR_INT may be n—bits wide.
`
`Once the circuit 102 has started
`
`generating the fixed number of addresses,
`
`the circuit 102 will
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`0325.00309
`CD99073
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`generally not stop until
`,w
`__// K/
`
`the fixed number of addresses has been
`
`generated (e.g., a non—interruptible burst).
`
`_.J
`
`The signal BURST may be,
`
`in one example, a configuration
`
`signal
`
`for programming the fixed number of addresses that
`
`the
`
`circuit
`
`102 may generate in response to the signals CLK and
`
`ADV/LDb. The signal BURST may be generated,
`
`in one example, by (i)
`
`using bond options,
`
`(ii) voltage levels applied to external pins,
`
`or (iii) other appropriate signal generation means.
`
`When the memory 104 is implemented as a DRAM,
`
`the circuit
`
`100 may' be configured to hide required DRAM refreshes
`
`(e.g ,
`
`refreshes may occur without affecting external environment)
`
`inside.
`
`a known fixed burst length of data words.
`
`The fixed burst length
`
`may allow the circuit 100 to operate at higher frequencies than a
`
`conventional DRAM without needing interrupts to perform refreshes
`
`of data.
`
`In one example,
`
`the fixed burst
`
`length may be four or
`
`eight words.
`
`However,
`
`the burst
`
`length may be set
`
`to whatever
`
`length is necessary to meet
`
`the design criteria of a particular
`
`application.
`
`For example,
`
`the burst length may be programmed,
`
`in
`
`
`
`one example,
`
`to allow both writeback and refresh to occur within a
`
`20
`
`single access.
`
`The fixed burst length may be set,
`
`in one example,
`
`All?
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`0325.00309
`CD99073
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`longer or shorter depending upon a frequency or technology to be
`
`used.
`
`The circuit 100 may be configured to provide a fixed
`
`burst
`
`length that may suit the requirements of network customers
`
`who typically burst large data lengths. By providing a fixed burst
`
`length,
`
`the circuit 100 may allow shared usage of data, address and
`
`control busses.
`
`A fixed length non—interruptible burst generally
`
`
`
`15
`
`cycles.
`
`The address and control busses may be shared by a number
`
`of memory devices. The circuit 100 may provide a more reliable and
`
`/or accurate burst than is possible with multiple chips.
`
`Referring
`
`to
`
`FIG.
`
`2,
`
`a
`
`detailed
`
`block
`
`diagram
`
`illustrating implementation of
`
`the circuit 102
`
`is shown.
`
`The
`
`circuit 102 may comprise an address counter register 126 and a
`
`burst counter 128.
`
`The address counter register 126 generally
`
`receives the signals ADDR_EXT, LOAD, and CLK.
`
`The address counter
`
`register 126 may be configured to present the signal ADDR“INT. The
`
`signal ADV and the signal BURST may be presented to a burst counter
`
`128.
`
`The signal CLK may be presented at an input 130 of the burst
`
`20
`
`counter 128. The burst counter 128 may have an output 132 that may
`
`present a signal
`
`(e.g., BURST_CLK) at an input 134 of the circuit
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`0325.00309
`CD99073
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`126.
`
`An initial address may be loaded into the address counter
`
`register‘ 126 by presenting the initial address
`
`in the signal
`
`ADDR_EXT and asserting the signal LOAD.
`
`The circuit 126 may be
`
`configured.
`
`to increment
`
`an address
`
`in response to the signal
`
`5
`
`BURST_CLK. When the signal ADV is asserted,
`
`the burst counter 128
`
`will generally present
`
`the signal BURST_CLK in response to the
`
`signal CLK.
`
`The signal BURST_CLK generally contains a number of
`
`
`
`
`
`1;
`
`pulses that has been programmed by the signal BURST.
`
`Referring
`
`to
`
`FIG.
`
`'3,
`
`a
`
`detailed block
`
`diagram
`
`illustrating an alternative embodiment of the circuit 102 is shown.
`
`The circuit 102' may comprise a latch 134, a multiplexer 136 and a
`
`counter 138.
`
`The signals ADDR_EXT, LOAD and CLK may be presented
`
`to the latch 134.
`
`The latch 134 may have an output 140 that may
`
`present a portion (e.g., m bits, where m is an integer smaller than
`n) of the signal ADDR_EXT as a portion of the signal ADDR_INT, an
`
`output 142 that may present a second portion (e.g., k bits, where
`
`k is an integer smaller than n) of the signal ADDR_EXT to a first
`
`input of the multiplexer 136, and an output 144 that may present
`
`the second portion of the signal ADDR_EXT to an input 146 of the
`
`20
`
`counter 138.
`
`10
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

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`0325.00309
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`The signals ADV, CLK and BURST may be presented to inputs
`
`of the counter 138.
`
`The counter 138 may be configured to generate
`
`a number of addresses in response to the signals CLK, BURST and
`
`ADV.
`
`The number of addresses generated by the counter 138 may be
`
`5
`
`programmed by the signal BURST.
`
`
`
`iifiu
`
`
`
`15
`
`The signal BURST may be presented to a control
`
`input of
`
`the multiplexer 136.
`
`The multiplexer 136 may select between a
`
`number of signals from the latch 134 and a number of signals from
`
`the counter 138 to be presented as a second portion of the signal
`
`ADDR_INT in response to the signal BURST.
`
`Referring to FIG.
`
`4,
`
`a
`
`flow diagranl
`
`illustrating an
`
`example burst address sequence is shown. When the signal ADV is
`
`asserted,
`
`the circuit 100 will generally generate a number of
`
`address signals, for example, N where N is an integer. The address
`
`signals may be generated,
`
`in one example, on a rising edge of the
`
`signal CLK.
`
`The address signals will generally continue to be
`
`generated until the Nth address signal is generated.
`
`Referring
`
`to
`
`FIGS.
`
`5A
`
`and
`
`5B,
`
`timing
`
`diagrams
`
`illustrating example operations for a four word (FIG.
`
`5A) and an
`
`20
`
`eight word (FIG.
`
`5B)
`
`fixed burst memory in accordance with the
`
`present
`
`invention are shown.
`
`The
`
`timing diagrams generally
`
`11
`
`ng l
`
`T L/
`3
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
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`

`

`.13,,
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`
`,,Subclass,
`
`APPLICATION No.
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`,
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`09/504344
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`APPLICANTS
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`._l
`I: ,
`1..
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`
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`; DConti’nued _
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`NANYA TECHNOLOGY EXHI
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH LL
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

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`file:///cz/APPS/preexam/correspondence/ 1 .htm
`
`lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`Bib Data Sheet ‘
`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`Patent and Trademark Office
`Address: COMMISSIONER OF PATENTS AND TRADEMARKS
`’ Washington, DC. 20231
`
`
`
`
`: SERIAL NUMBER
`
`09/504,344
`.
`
`
`
`34 PPLicANTé
`' ”
`
`RUFE.
`
`—
`
`‘
`
`Cathal G. Phelan, Mountain View, CA;
`
`
`FILING DATE
`' GROUP ART UN”
`CLASS
`02/14/2000
`_
`-
`365
`‘ 2824
`71/
`.2237 ,,
`
`
`
`* CONTINUING DATA ********************i**** n on a m /
`
`i * FOREIGN APPLICATIONS ******************** m I
`
`A/
`
`ATTORNEY
`DOCKET NO.
`0325 000309
`_
`
`,
`
`lF REQUIRED, FOREIGN FILING LICENSEGRANTED H
`05/02/2000
`.,
`
`Foreign Priority claimed
`D yes mo
`' STATE OR ‘K/SHEETS
`TOTAL ZINDEPENDEN :
`DRAWING VI CLAIMS ,
`CLAIMS
`COLglgR
`35 USC 119 (a-d) conditions I yes [210 [2| Metafiefix
`
`met
`llwance
`
` i erified and L4 ‘3 _
`
`1.519 ___ ..X"T_’”.. li’ai .,.-
`,
`DDRESS
`
`
`
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`
`I
`
`,5
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`
`,.
`
`0.21363
`
`
`
`
`
`FILING FEE FEES: Authority has been given in Paper
`RECEIVED
`NO.
`to charge/credit DEPOSIT ACCOUNT
`690
`.
`for following:
`
`'
`
`I D 1.17 Fees ( Processing Ext. of
`:tlme )
`
`
`
`
`
`
`
`
`Iofrl
`
`5/2/00 11:39 AM
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`PATENT APPLICATION SERIAL No.
`
`US. DEPARTMENT OF COMMERCE
`
`PATENT AND TRADEMARK OFFICE
`
`FEE RECORD SHEET
`
`iEEfEL’I/EDOG SEQRWIEH fifiOOflOiE 633504344
`
`{‘11 F35101
`
`690.00 DP
`
`PTO-1556
`
`(5/87)
`'U.S. GPO: 1999-459-082/19144
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`OZ‘ tS~OO
`
`
`
`CHRISTOPHER P. MAIORANA, P.C.
`24025 Greater Mack, Suite 200
`St. Clair Shores, Michigan 48080
`
`Utility Patent Application Transmittal
`(Only for new non-provisional applications Under 37 CFR 1.53(b))
`
`
`
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`02/
`LOO
`Case Docket No.0325.000303
`Date: February l4= 2000
`
`ASSISTANT COMMISSIONER FOR PATENTS
`Washington, D. C. 20231
`
`Sir:
`
`Transmitted herewith for filing is a patent application of:
`
`Inventor(s) :
`
`Cathal G. Phelan
`
`For:
`
`FIXED BURST MEMORIES
`
`
`
`
`
`Enclosed are:
`
`1
`
`2
`
`3
`
`X
`
`X
`
`X
`
`Specification (13 pages); Claims (4 pages); Abstract (1 page)
`
`_5_ sheets of formal drawings.
`
`Total Pages ____2__
`Oath or Declaration
`a. l Newly executed (original or copy)
`b. __
`Copy from a prior application (37 CFR 1.63(d))
`(for continuation/divisional with Item 5 completed)
`c. __ Copy of Revocation of Previous Power
`
`4.
`
`__
`
`Incorporation By Reference (usable if Item 3b is checked)
`The entire disclosure of the prior application, from which a copy of the oath or
`declaration is supplied under Item 3b, is considered as being part of the disclosure
`of the accompanying application and is hereby incorporated by reference therein.
`
`5.
`
`__
`
`If 3 Continuing Application, check appropriate box and supply the requisite
`information below and in a preliminary amendment:
`
`Continuation
`of prior application no.:
`
`Divisional
`
`Continuation—in-part (CIP)
`
`6
`
`X.
`
`An assignment to CYPRESS SEMICONDUCTOR CORP. along with PTO form
`1595.
`
`__
`
`X
`
`7.
`
`8
`
`9.
`
`A PTO Form 1449 with a copy of the references not previously cited.
`
`Return Receipt Postcard
`
`Other:
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
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`
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`
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`
`
`
`Page 2 of2
`
`The filin- fee has been calculated as shown below:
`
`$18.00
`Total Claims -— x
`$78.00
`Indep. Claims -— X
`Mult.Dep. Claims -- $260.00
`
`
`SUB-TOTAL .................. $690.00
`
`SMALL ENTITY STATUS (divide SUB—TOTAL by two) ...... $
`_
`L Assignment Recordal Fee ($40.00) ......................... $ 40.00
`TOTAL ....................... $730.00
`
`$ 0.00
`$ 0.00
`$ 0.00
`
`
`
`
`
`
`
`
`Q
`
`:
`gD
`
`h
`
`.09/504344lllllltllllllllllllllllIlllllllllllllllll
`2/14/00.
`
`_X_
`
`A check in the amount of $730.00 to cover the filing fee is enclosed.
`
`X
`
`The Commissioner is hereby authorized to charge any fees under 37 CFR 1.16 and 1.17
`which may be required by this paper or associated with this filing to Deposit Account No.
`50-0541. A duplicate copy of this sheet is enclosed.
`
`
`Correspondence Address:
`
`
`Customer Number or Bar Code Label:
`
`021363
`
`PATENT mm MICE
`
`
`CERTIFICATE OF EXPRESS MAILING
`
`I hereby certify that this paper (along with any paper referred to as being attached or enclosed) is being deposited with the
`United States Postal Service via Express Mail Label No. EL417953316US in an envelope addressed to: BOX PATENT
`APPLICATION, Assistant Commissioner for Patents, Washington, DC. 20231, 0 Februa
`14 2000.
`
` :mMM
`
`
`ii:4u.“
`:4
`
`
`
`I
`
`CHRISTOPHER P. MAIORANA, PO
`24025 Greater Mack, Suite 200
`St. Clair Shores, Michigan 48080
`(810) 498—0670
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`Date: February 14, 2000
`
`Attorney Docket No.: 0325.00309
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
`
`0325.00309
`CD99073
`
`illustrate externally measurable signals for four and eight word
`
`fixed burst read/write architectures.
`
`In general, an operation
`
`(e.g.,
`
`read or write) of the circuit 100 begins with loading an
`
`initial address
`
`(e.g., portions 150,
`
`154,
`
`and 158 of FIG.
`
`5A;
`
`_portions 150’, 154’,
`
`and 158’ of FIG. 5B).
`
`Starting with the
`
`initial address, a fixed number of words are generally transferred
`
`(e.g.,
`
`line DQ of FIGS.
`
`5A and 5B). During the transfer of the
`
`fixed number of words,
`
`the address and control buses (e.g., ADDR,
`
`CE, R/W, etc.) are generally available to other devices
`
`(e.g.,
`
`portions 152, 156, and 160 of FIG.
`
`5A; portions 152’, 156’, and
`
`160’ of FIG. 5B).
`
`In one example,
`
`the control and address bus
`
`activity may be one—fourth (FIG.
`
`5A) or one—eighth (FIG.
`
`5B)
`
`the
`
`data bus activity (e.g., compare line ADDR with line DQ of FIGS. 5A
`
`and 5B).
`
`The
`
`reduced. bus activity' may' be an effect of
`
`the
`
`architecture.
`
`The data bus may be,
`
`in one example, active nearly
`
`100% of the time (e.g.,
`
`line DQ of FIGS. 5A and 5B)
`
`In one example,
`
`there may be no inefficiencies switching from read to write to read
`
`
`
`l5
`
`etcetera (e.g., see labels under line DQ of FIGS. 5A and 5B).
`
`Referring to FIG.
`
`6,
`
`a timing diagram illustrating a
`
`20
`
`fixed burst
`
`length long enough to hide a writeback and a refresh
`
`cycle
`
`is shown.
`
`Internally the action being performed may
`
`12
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
`
`0325.00309
`CD99073
`
`completely' hide DRAM refresh. activity‘
`
`inside nominal external
`
`activities. A.portion 162 illustrates that refresh activity (e.g.,
`
`writeback,
`
`read for refresh,
`
`and writeback for refresh) may be
`
`completed within the time of
`
`the burst
`
`transfer. When a fixed
`
`burst long enough to completely hide refresh activity is provided,
`
`there may be no penalty for using DRAM instead of SRAM for the
`
`memory 104.
`
`While
`
`the invention. has been. particularly'
`
`shown. and
`
`described with reference to the preferred embodiments thereof, it
`
`will be understood by those skilled in the art that various changes
`
`in form and details may be made without departing from the spirit
`
`and scope of the invention.
`
`
`
`13
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
`
`0325 . 00309
`
`CD99073
`
`CIS
`
`E
`
`1.
`
`An integrated cir
`
`it comprising:
`
`a memory comprising a p urality of storage elements each
`
`configured.
`
`to read.
`
`and. write d ta in response to an internal
`
`address signal; and
`
`
`
`
`
`
`
`external address signal,
`
`(ii) a cl ck signal and (iii) one or more
`
`control signals, wherein said ge eration of said predetermined
`
`number of internal address signals is non~interruptible.
`
`
`
`2.
`
`The integrated circuit according to Claiflll, wherein
`
`said predetermine number of internal address signals is determined
`
`by a fixed burst
`
`length.
`
`
`
`3.
`
`The integrated circuit according to clainll, wherein
`
`said predetermined number of interna address signals is 4.
`
`
`
`The integrated circuit ccording to clainll, wherein
`
`
`
`4.
`
`said predetermined number of internal address signals is 8.
`
`
`l4
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
`
`0325.00309
`
`C 99073
`
`9 \
`
`5.
`
`The integrated cirLuit according to clain12, wherein
`
`said fixed burst length is progr mmable.
`
` 35
`
`ii2:i}1:£232..
`
`
`
`6.
`
`The integrated ci cuit according to ClaiHIS, wherein
`
`said fixed burst length is pro rammed by bond options.
`
`7.
`
`The integrated c rcuit according to clain15, wherein
`
`said fixed burst
`
`length is
`
`programmed by 'voltage levels on
`
`external pins.
`
`8.
`
`The integrated c rcuit according to clainll, wherein
`
`said memory comprises a static random access memory.
`
`9.
`
`The integrated c rcuit according to clainll, wherein
`
`said memory comprises a dynamic random access memory.
`
`10.
`
`The integrated ci cuit according to clain19, wherein
`
`said predetermined number of int rnal address signals is chosen to
`
`provide time for writeback and efresh cycles.
`
`15
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
`
`\
`
`0325.00309
`CD99073
`
`C}/
`
`I
`The integrated circuit/according to clainll, wherein
`
`11.
`
`said predetermined number of internal address signals is chosen to
`I
`
`meet predetermined criteria for sharing address and control busses.
`
`comprising:
`
`l
`
`12.
`
`An integrated circui
`
`means
`
`for reading and w iting data in response to an
`
`internal address signal; and
`
`
`
`means
`
`for generating a predetermined number of said
`
`internal address signals in resp nse to (i)
`
`an external address
`
`signal,
`
`(ii) a clock signal and ('ii) one or more control signals,
`
`wherein said generation of said redetermined number of internal
`
`address signals is non—interrupt'ble.
`
`
`
`
`
`
`
`ii:1
`
`13.
`
`A method of prov ding a
`
`fixed burst
`
`length data
`
`transfer comprising the steps of
`
`
`
`reading from and writi g data to a memory in response to
`
`an internal address signal; and
`
`
`
`5
`
`generating a predete mined number of
`
`said internal
`
`address signals in response to (i
`
`an external address signal,
`
`(ii)
`
`a clock signal and (iii) a contro signal, wherein said generation
`
`
`
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
`
`0325.00309
`
`03
`
`cn99o73
`
`of said predeterminedIumnber of interna address signals is non—interruptible.
`
`14.
`
`The method accordidg to claim 13, further comprising
`
`the step of programming said pred termined number.
`
`15.
`
`The method accor ing to clainl 14, wherein. said
`
`programming step is performed us'ng bond options.
`
`16.
`
`The method acco ding to clainl 14, wherein. said
`
`programming step is performed u ing voltage levels.
`
`
`
`
`
`
`
`
`17.
`
`The method accor ing to claim 13, further comprising
`
`the step of selecting said pred termined number to provide time for
`
`writeback and refresh cycles.
`
`
`
`
`17
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`
`
`
`
`0325.00309
`CD99073
`
`ABSTRACT OF THE DISCLOSURE
`
`An integrated circuit comprising a memory and a logic
`
`circuit.
`
`The memory may comprise a plurality of storage elements
`
`each configured to read and write data in response to an internal
`
`5
`
`address signal.
`
`The logic circuit may be configured to generate a
`
`i?
`
`
`
`
`
`:5
`
`:3:
`
`
`
`fin
`ii
`
`
`
`predetermined number of the internal address signals in response to
`
`(i) an external address signal,
`
`(ii) a clock signal and (iii) one
`
`(n: more control signals.
`
`The generation of
`
`the predetermined
`
`number of internal address signals may be non-interruptible.
`
`18
`
`(”Evan-V»,
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`e
`
`’ 02711/00
`
`FRI 11:22 FAX 810 498 0673
`
`CHRISTOPHER MAIORANA PC
`
`[@008
`
`
`
`Docket No. 0325.003 09
`
`
`
`DECLARATION, POWER OF ATTORNEY AND PETITION
`
`I, the undersigned inventor, hereby declare that:
`
`My residence, post office address and citizenship are given. next to my name;
`
`I believe that I am the first, original and sole inventorofthe sub‘cctmatter claimed in the application
`for patent entitled "HIDDEN DRAM REFRESH IN FIXED BURST MEMORIES", which:
`
`X
`
`is submitted herewith;
`
`‘was filed on
`
`
`
`as Application Serial No.
`
`and amended on
`
`;
`
`I have reviewed and understand the contents of the above-identified application for patent
`(hereinafter, "this application"), including the claims;
`
`I acknowledge the duty under Title 37, Code ofFederal Regulations, Section 1.56, to disclose to the
`United States Patent and Trademark Office infonnation known to be material to thepatentability of
`this application.
`I also acknowledge that information is material to patentability when it is not
`etunulative to information already provided to the United States Patent and Trademark Office and
`when it either
`
`compels, by itselforin combination with other information, a conclusion that a claim
`is unpatentable under the preponderance of evidence standard, giving each term in
`the claim its broadest reasonable construction consistent with the application, and
`before any consideration is given to evidence which may be submitted to establish
`a contrary conclusion ofpatentability, or
`
`refutes or is inconsistent with a position taken in either (i) asserting an argument of
`patentability, or (ii) opposing an argument ofunpatentability relied on by the United
`States Patent and Trademark Office;
`
`I hereby claim the priority benefit under Title 35, Section 119(e), of the following United States
`provisional patent applications:
`
`Application No.
`
`Filing Date
`
`Ihereby claim the priority benefit under Title 35, Section 120, ofthe following United States patent
`applications:
`
`Serial No.
`
`Filing Date
`
`Status
`
`
`
`
`
`NANYA IECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`‘ 02711/00
`
`FRI 11:22 FAX 810 498 0673
`
`CHRISTOPHER MAIORANA PC
`
`.009
`
`
`
`
`
`Docket No. 032500309
`
`Page 2 of 2
`
`I hereby claim the priority benefit under Title 3 5, S ection 3 65(c), ofthe following PCT International
`patent applications designating the United States:
`
`Application No.
`
`Filing Date
`
`Where the subject matter of the claims of this application is not disclosed in the United States or
`PCT priority patent applications identified above, I acknowledge the duty to disclose infonnation
`known to be material to the patentability ofthis application that became available between the filing
`dates of this application and of the priority United States or PCT patent applications.
`
`I hereby appoint as my attorneys with full power of substitution to prosecute this application and
`conduct all business in the United States Patent and Trademark Office associated with this
`
`application: Customer No. 021363.
`
`\\l\\\\\\\\|“Nil“\\\\\\\\||\\\\\\\\
`
`02 1363
`
`"WW “if"? ‘
`_, M...»4 7’
`
`I declare that all statements made herein ofmy own. knowledge are true and that all statements made
`on information and belief are believed to be true; and further that these statements were made with
`the knowledge that willful false statements and the like so made are