Paper 29
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`____________________________
`
`QUALCOMM INCORPORATED
`
`PETITIONER
`
`
`v.
`
`
`MONTEREY RESEARCH, LLC,
`
`PATENT OWNER
`____________________________
`
`INTER PARTES REVIEW NO. IPR2020-01492
`PATENT 6,651,134
`______________
`
`
`PETITIONER’S DEMONSTRATIVES
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`____________________________
`
`QUALCOMM INCORPORATED
`
`PETITIONER
`
`
`v.
`
`
`MONTEREY RESEARCH, LLC,
`
`PATENT OWNER
`____________________________
`
`INTER PARTES REVIEW NO. IPR2020-01492
`PATENT 6,651,134
`______________
`
`
`PETITIONER’S DEMONSTRATIVES
`
`
`
`
`
`Petitioner’s Hearing Demonstratives
`IPR2020‐01492
`
`U.S. Patent No. 6,651,134
`December 7, 2021
`
`1
`
`
`
`Overview
`
`•
`
`•
`
`’134 Patent
`– Purports to have developed “non‐interruptible” burst memory
`Schaefer
`– Schaefer discloses “non‐interruptible” burst operations
`– A user command is issued at T2 before the precharge is initiated.
`– PO’s Expert concedes that the only user command is issued at time T2
`– Petitioner’s Expert confirms Schaefer’s disclosure
`– PO’s Expert reliance on “termination” commands is not applicable
`– Schaefer’s purported goals do not negate anticipation
`
`2
`
`
`
`’134 Patent | Purports to have developed “non‐interruptible” burst memory
`
`’134 Patent (EX1001)
`
`3
`
`
`
`’134 Patent | Purports to have developed “non‐interruptible” burst memory
`
`SUMMARY OF THE INVENTION
`The present invention concerns an integrated circuit
`comprising a memory and a logic circuit. The memory
`may comprise a plurality of Storage elements each
`configured to read and write data in response to an internal
`address Signal. The logic circuit may be configured to
`generate a predetermined number of the internal address
`Signals in response to (i) an external address signal, (ii) a
`clock signal and (iii) one or more control Signals. The
`generation of the predetermined number of internal
`address signals may be non-interruptible.
`
`’134 Patent (EX1001) at 1:46‐56
`
`4
`
`
`
`’134 Patent | Purports to have developed “non‐interruptible” burst memory
`
`1. A circuit comprising:
`a memory comprising a plurality of storage elements each
`configured to read and write data in response to an
`internal address signal; and
`a logic circuit configured to generate a predetermined
`number of said internal address signals in response to (i)
`an external address signal, (ii) a clock signal and (iii)
`one or more control signals, wherein said generation of
`said predetermined number of internal address signals is
`non-interruptible.
`
`’134 Patent (EX1001) at Claim 1
`
`5
`
`
`
`’134 Patent | Purports to have developed “non‐interruptible” burst memory
`
`The ’134 Patent’s circuit is configured for non‐interruptible bursts via a control signal.
`
`The Signal ADV may be, in one example,
`used as a control signal. The circuit 100
`may be configured to transfer a fixed
`number of words to or from the memory
`104 in response to the signals ADV, CLK
`and R/Wb. When the signal ADV is
`asserted, the circuit 100 will generally
`begin transferring a predetermined
`number of words. The transfer is generally
`non‐interruptible.
`
`’134 Patent (EX1001) at 3:5‐11; Petition at 7, 16; POR at 11, 13
`
`’134 Patent (EX1001) at Fig. 1
`
`6
`
`
`
`’134 Patent | Purports to have developed “non‐interruptible” burst memory
`
`The ’134 Patent’s circuit is configured for non‐interruptible bursts via a control signal.
`
`The signal ADV/LDb may be a control signal
`…. When the signal ADV/LDb is in the
`second state, the circuit 102 may be
`configured to generate the signal ADDR
`INT …. Once the circuit 102 has started
`generating the fixed number of addresses,
`the circuit 102 will generally not stop until
`the fixed number of addresses has been
`generated (e.g., a non‐interruptible burst).
`
`’134 Patent (EX1001) at 3:14‐29; Petition at 7, 16, 17; POR at 11, 13
`
`’134 Patent (EX1001) at Fig. 5A
`
`7
`
`
`
`Overview
`
`•
`
`•
`
`’134 Patent
`– Purports to have developed “non‐interruptible” burst memory
`Schaefer
`– Schaefer discloses “non‐interruptible” burst operations
`– A user command is issued at T2 before the precharge is initiated.
`– PO’s Expert concedes that the only user command is issued at time T2
`– Petitioner’s Expert confirms Schaefer’s disclosure
`– PO’s Expert reliance on “termination” commands is not applicable
`– Schaefer’s purported goals do not negate anticipation
`
`8
`
`
`
`Schaefer | Discloses “non‐interruptible” burst operations
`
`Schaefer discloses that when using the AUTO‐PRECHARGE command feature, “[t]he user is not
`allowed to issue another command until” the precharge is completed.
`
`By using the AUTO-PRECHARGE command feature, a manual
`PRECHARGE command does not need to be issued during the
`functional operation of SDRAM 20. The AUTO-PRECHARGE
`command insures that the precharge is initiated at the earliest, valid
`stage within a burst cycle. The user is not allowed to issue another
`command until the precharged time (tRP) is completed. Therefore,
`when an AUTO-PRECHARGE command is employed in SDRAM 20,
`the selected bank memory array must not be accessed again until tRP,
`is complete.
`
`Schaefer (EX1017) at 7:38‐48; Petition at 1, 13, 20, 33
`
`9
`
`
`
`Schaefer | Discloses “non‐interruptible” burst operations
`
`PO concedes that Schaefer’s language—“[t]he user is not allowed to issue another command
`until the precharged time (tRP) is completed” discloses a “prohibition on user commands.”
`By using the AUTO-PRECHARGE command
`feature, a manual PRECHARGE command does not
`need to be issued during the functional operation of
`SDRAM 20. The AUTO-PRECHARGE command
`insures that the precharge is initiated at the earliest,
`valid stage within a burst cycle. The user is not
`allowed
`to
`issue another command until
`the
`precharged time (tRP) is completed. Therefore, when
`an AUTO-PRECHARGE command is employed in
`SDRAM 20, the selected bank memory array must
`not be accessed again until tRP, is complete.
`
`Schaefer goes on to describe how
`the prohibition on user commands
`preventing access to the bank
`memory array during the precharged
`time tRP would work for various
`periods of tRP.
`
`POR at 44
`
`Schaefer (EX1017) at 7:38‐48
`
`10
`
`
`
`Schaefer | Discloses “non‐interruptible” burst operations
`
`PO asserts that Schaefer’s prohibition is limited to the precharged time tRP
`
`Qualcomm accurately identifies the dispute between the parties:
`The only dispute between the parties is whether this prohibition is limited to “during
`tRP,” as PO asserts, or from the issuance of the user command at T2, as Petitioner
`asserts. That is, PO asserts that the prohibition is limited to the time highlighted in
`green below, while Petitioner asserts the prohibition begins when the user issues the
`burst command at T2.
`
`PO Sur‐Reply at 4
`
`Schaefer does not disclose prohibiting user commands beyond the precharge period
`tRP, which begins after completion of the burst transfer and extends only from t6
`through t9 in Figure 4.
`
`POR at 37
`
`11
`
`
`
`Schaefer | Discloses “non‐interruptible” burst operations
`
`PO’s only dispute relates to the start of the time period over which the user is not allowed to
`issue another command.
`PO’s position ‐ “non‐interruptible” period is from
`T6 ‐ T9
`
`Petitioner’s position ‐“non‐interruptible” period is
`from T2 ‐ T9
`
`Schaefer (EX1017) at 7:42‐45, Fig. 4; PO Sur‐Reply at 4; POR at 37
`
`Schaefer (EX1017) at 7:42‐45, Fig. 4; Petition at 33
`
`12
`
`
`
`Overview
`
`•
`
`•
`
`’134 Patent
`– Purports to have developed “non‐interruptible” burst memory
`Schaefer
`– Schaefer discloses “non‐interruptible” burst operations
`– A user command is issued at T2 before the precharge is initiated
`– PO’s Expert concedes that the only user command is issued at time T2
`– Petitioner’s Expert confirms Schaefer’s disclosure
`– PO’s Expert reliance on “termination” commands is not applicable
`– Schaefer’s purported goals do not negate anticipation
`
`13
`
`
`
`Schaefer | A user command is issued at T2 before the precharge is initiated
`
`Schaefer (EX1017) at 4:53‐56, 7:32‐38, Fig. 4; Petition at 30‐31, 42
`
`14
`
`
`
`Schaefer | A user command is issued at T2 before the precharge is initiated
`
`Schaefer’s plain language discloses that a user issues an external AUTO‐PRECHARGE
`command signal on A10 that programs the READ/WRITE command into a READ/WRITE with
`AUTO‐PRECHARGE command at time T2.
`Address pin A10 provides an input path for a
`command signal which determines whether or not
`an AUTO-PRECHARGE command, described in
`detail below, is to be initiated automatically after
`the READ command.
`
`Schaefer (EX1017), 4:53‐56
`The AUTO-PRECHARGE command feature of
`the preferred embodiment of SDRAM 20, permits
`a user to program a READ command or WRITE
`command that automatically performs a precharge
`upon the completion of the READ command or
`the WRITE command.
`
`Schaefer (EX1017) at 7:32‐38
`
`Schaefer (EX1017) at Fig. 4; Petition at 30‐31, 42
`
`15
`
`
`
`Schaefer | A user command is issued at T2 before the precharge is initiated
`
`Following issuance of the READ/WRITE with AUTO‐PRECHARGE command at time T2, the
`memory device automatically initiates the internal precharge (i.e. AUTO‐PRECHARGE) at
`time T6.
`
`the preferred
`The AUTO-PRECHARGE command feature of
`embodiment of SDRAM 20, permits a user to program a READ
`command or WRITE command that automatically performs a
`precharge upon the completion of the READ command or the WRITE
`command.
`
`Schaefer (EX1017) at 7:32‐38; Petition at 8, 13, 42, POR at 36, 43‐44
`
`16
`
`
`
`Schaefer | A user command is issued at T2 before the precharge is initiated
`
`Schaefer’s “prohibition on user commands” bars issuance of external user commands – not
`initiation of internal procedures/commands.
`
`By using the AUTO-PRECHARGE command feature, a manual
`PRECHARGE command does not need to be issued during the
`functional operation of SDRAM 20. The AUTO-PRECHARGE
`command insures that the precharge is initiated at the earliest, valid
`stage within a burst cycle. The user is not allowed to issue another
`command until the precharged time (tRP) is completed. Therefore,
`when an AUTO-PRECHARGE command is employed in SDRAM 20,
`the selected bank memory array must not be accessed again until tRP,
`is complete.
`
`Schaefer (EX1017) at 7:38‐48; Petition at 1, 4‐5, 13, 20, 33‐35; Petitioner’s Reply at 1‐2, 8‐10
`
`17
`
`
`
`Schaefer | A user command is issued at T2 before the precharge is initiated
`
`The Board’s Institution Decision acknowledged that with the AUTO‐PRECHARGE
`command feature, a user may program.
`
`We do not agree with Patent Owner. Schaefer states that, with the “AUTO-PRECHARGE command
`feature,” a user may “program a READ command or WRITE command that automatically performs
`a precharge upon the completion of the READ command or the WRITE command.” Ex. 1017,
`7:32–37. It explains further that “[t]he AUTO-PRECHARGE command insures that the precharge is
`initiated at the earliest, valid stage within a burst cycle.” Id. at 7:40–42. Schaefer discloses that the
`AUTO-PRECHARGE option is selected when issuing the read/write command. Id. at Fig. 4 (CLK
`cycle T2). In such a case, “[t]he user is not allowed to issue another command until the precharged
`time (tRP) is completed.” Id. at 7:42–44 (emphasis added). Thus, Schaefer’s teachings support that
`the prohibition on user commands begins with the initial READ or WRITE command and ends with
`the completion of the precharge operation.
`
`Institution Decision at 11‐12
`
`18
`
`
`
`Schaefer | A user command is issued at T2 before the precharge is initiated
`
`The Board’s Institution Decision also acknowledged that the AUTO‐PRECHARGE option is
`selected when the user issues a read/write command at CLK cycle T2.
`
`We do not agree with Patent Owner. Schaefer states that, with the “AUTO-PRECHARGE command
`feature,” a user may “program a READ command or WRITE command that automatically performs
`a precharge upon the completion of the READ command or the WRITE command.” Ex. 1017,
`7:32–37. It explains further that “[t]he AUTO-PRECHARGE command insures that the precharge is
`initiated at the earliest, valid stage within a burst cycle.” Id. at 7:40–42. Schaefer discloses that the
`AUTO-PRECHARGE option is selected when issuing the read/write command. Id. at Fig. 4 (CLK
`cycle T2). In such a case, “[t]he user is not allowed to issue another command until the precharged
`time (tRP) is completed.” Id. at 7:42–44 (emphasis added). Thus, Schaefer’s teachings support that
`the prohibition on user commands begins with the initial READ or WRITE command and ends with
`the completion of the precharge operation.
`
`Institution Decision at 11‐12
`
`19
`
`
`
`Overview
`
`•
`
`•
`
`’134 Patent
`– Purports to have developed “non‐interruptible” burst memory
`Schaefer
`– Schaefer discloses “non‐interruptible” burst operations
`– A user command is issued at T2 before the precharge is initiated
`– PO’s Expert concedes that the only user command is issued at time T2
`– Petitioner’s Expert confirms Schaefer’s disclosure
`– PO’s Expert reliance on “termination” commands is not applicable
`– Schaefer’s purported goals do not negate anticipation
`
`20
`
`
`
`Schaefer | PO’s Expert concedes that the only user command is issued at time T2
`
`PO’s Expert concedes that the user issues one command, which is a READ burst with
`AUTO‐PRECHARGE at time T2
`
`Q. So at time T2 in Figure 4, the user issues one command, which is a read burst with auto-
`precharge, correct?
`
`A. Just to be clear, you're asking about Figure 4 now?
`
`Q. Correct.
`
`A.
`
`I think I was on -- okay. So I think -- I think that's right. We see at T2 there's a read
`command with auto-precharge, as denoted by at least what we're seeing on signal A10 at
`that T2 time.
`
`Brogioli Dep. (EX1029) at 28:2‐12; Petitioner’s Reply at 2
`
`21
`
`
`
`Schaefer | PO’s Expert concedes that the only user command is issued at time T2
`
`PO’s expert concedes that there is no other external user command from T2 to T9 other
`than the READ with AUTO‐PRECHARGE command issued at T2
`
`A. I guess Figure 4 of Schaefer, I think it is
`-- that’s a single command that's issued
`at that time T2 in Figure 4, with
`subsequent, you know, multiple phases
`that occur after the issuance of the
`command.
`
`Q. And one of the phases that occurs after
`the issuance of the command is the
`precharge phase, correct?
`
`A. So I'll stick with Figure 4, just to for the
`record. After the issuance of the read
`command with precharge, one of the --
`one of the things that happens in this
`figure, T6 to T9, is the precharge.
`
`Q. And -- and just to be clear, at T6, there
`is no precharge command issued,
`correct, in Figure 4 of Schaefer?
`
`A. That's correct.
`
`Brogioli Dep. (EX1029) at 43:23‐44:16; Petitioner’s Reply at 2, 9
`
`22
`
`
`
`Overview
`
`•
`
`•
`
`’134 Patent
`– Purports to have developed “non‐interruptible” burst memory
`Schaefer
`– Schaefer discloses “non‐interruptible” burst operations
`– A user command is issued at T2 before the precharge is initiated
`– PO’s Expert concedes that the only user command is issued at time T2
`– Petitioner’s Expert confirms Schaefer’s disclosure
`– PO’s Expert reliance on “termination” commands is not applicable
`– Schaefer’s purported goals do not negate anticipation
`
`23
`
`
`
`Schaefer | Petitioner’s Expert confirms Schaefer’s disclosure
`
`Petitioner’s Expert explains why a POSITA would understand Schaefer’s plain language
`to bar user commands from T2 to T9.
`
`78. Schaefer also explains that during a burst operation with AUTO-
`PRECHARGE, “[t]he user is not allowed to issue another command until
`the precharged time (tRP) is completed.” Id., 7:42-44. In other words, the user
`cannot issue another command from the time the command at T2 is
`registered until (tRP) completes as annotated below in Figure 4. Nowhere
`does Schaefer suggest that “another command” could be issued at any time
`after the READ or WRITE with AUTO-PRECHARGE command and before
`tRP concludes.
`
`Murphy Dec (Ex. 1015) at ¶ 78
`
`24
`
`
`
`Schaefer | Petitioner’s Expert confirms Schaefer’s disclosure
`
`Petitioner’s Expert explains why a POSITA would understand Schaefer’s plain language
`to bar user commands from T2 to T9.
`82. Consistent with Schaefer’s language stating “[t]he user is not allowed to issue another
`command until the precharged time (tRP) is completed” (id., 7:42-44), a POSITA at the filing
`date of the ’134 Patent would understand that the prohibition on a user issuing a command
`extends from the start of the read or write with auto-precharge until the precharged time is
`completed. A POSITA would have understood that Schaefer’s language reflects a significant
`design choice combines and optimizes a read/write burst and precharge. Prior to the start of the
`precharge time the device is performing the commanded “READ” operation. The goal of
`READ WITH AUTO-PRECHARGE is to save cycles and command bus usage (a separate
`PRECHARGE command is not required here). Thus, the internal operation of this command
`(“READ WITH AUTO-PRECHARGE”) is structured to make these elements come true, which
`requires non-interruption to allow the implementation to be simple & operate at high speed.
`
`Murphy Dec (Ex. 1015) at ¶ 82
`
`25
`
`
`
`Schaefer | Petitioner’s Expert confirms Schaefer’s disclosure
`
`Petitioner’s Expert explains why a POSITA would understand Schaefer’s plain language
`to bar user commands from T2 to T9.
`
`83. A device could have been designed to allow interruption during the read portion
`of the read with auto-precharge, but that is not what Schaefer discloses, and there are
`reasons Schaefer did not propose such a design. Allowing such interrupts would have
`been more costly (more circuitry) and may have detrimentally impacted the speed of
`operation. The question always ends up being asked, what is the advantage to this
`change vs. the cost and how often will it be used? … Such a system could be
`designed, but at what cost & usefulness? The same is true in this case. A POSITA at
`the filing date of the ’134 Patent would have understood Schaefer’s plain disclosure,
`and understood that disclosure to indicate Schaefer made a reasonable design choice
`weighing cost versus usefulness, and chose not to design the device to have the read
`and write with auto-precharge be interruptible.
`
`Murphy Dec (Ex. 1015) at ¶ 83
`
`26
`
`
`
`Overview
`
`•
`
`•
`
`’134 Patent
`– Purports to have developed “non‐interruptible” burst memory
`Schaefer
`– Schaefer discloses “non‐interruptible” burst operations
`– A user command is issued at T2 before the precharge is initiated
`– PO’s Expert concedes that the only user command is issued at time T2
`– Petitioner’s Expert confirms Schaefer’s disclosure
`– PO’s Expert reliance on “termination” commands is not applicable
`– Schaefer’s purported goals do not negate anticipation
`
`27
`
`
`
`Schaefer | PO’s Expert reliance on “termination” commands is not applicable
`
`No credible evidence supports PO’s assertion that burst termination commands
`apply to all disclosed bursts – Schaefer limits applicability of termination
`commands to full‐page bursts.
`
`the "burst"
`A full-page burst will wrap around and continually restart
`operation until a BURST TERMINATION command or PRECHARGE
`command is indicated by command controller 28 or until interrupted with
`another burst operation.
`
`A full page burst will wrap around and continue writing data until terminated
`by the BURST TERMINATION command, PRECHARGE command, or until
`interrupted with another burst operation.
`
`Schaefer (EX1017) at 5:15‐20, 5:58‐62; Petition at 37, 48; Petitioner’s Reply at 12, 14
`
`28
`
`
`
`Schaefer | PO’s Expert reliance on “termination” commands is not applicable
`
`Petitioner’s Expert confirms that Schaefer’s burst termination commands do not
`apply to bursts with AUTO‐PRECHARGE.
`
`Q. Schaefer discloses at least three ways to terminate a burst, burst
`termination command, a precharge command or a second burst
`operation; correct?
`A. That’s correct, for the bursts that don't include an auto‐precharge.”
`
`EX2009, Murphy Dep. (EX2009) at 118:14‐22; Petitioner’s Reply at 14
`PO’s arguments about what Schaefer could have disclosed do not override—and
`are contrary to—what Schaefer actually disclosed.
`
`Petitioner’s Reply at 3
`
`29
`
`
`
`Schaefer | PO’s Expert reliance on “termination” commands is not applicable
`
`PO’s Expert concedes Schaefer does not explicitly disclose any such termination command
`for a fixed‐length burst with AUTO‐PRECHARGE.
`
`A.
`
`Q. Would you agree that at least for the way Schaefer describes a full‐page burst, that is
`not a fixed‐length burst, because it continues indefinitely?
`I would point out that ‐‐ if we go back to Column 5, the language Schaefer uses is
`that the full‐page burst will wrap around and continuously restart the burst
`operation until the burst termination command or precharge command is indicated.
`Q. And that's not true for a burst of length 2, 4, or 8, correct?
`A.
`I think that's correct. I don't recall in my declaration talking about, for example, a – a
`burst of length 2 that ‐‐ that loops or restarts, kind of thing.
`
`Brogioli Dep. (EX1029) at 34:8‐23; Petitioner’s Reply at 3, 12
`
`30
`
`
`
`Schaefer | PO’s Expert reliance on “termination” commands is not applicable
`
`PO’s Expert concedes Schaefer does not explicitly disclose any such termination command
`for a fixed‐length burst with AUTO‐PRECHARGE.
`
`Q. That's fair enough. So let me ask that question a different way. A difference between
`a burst length 8 of 2, 4, and 8, on one hand, versus full page on the other hand is a
`burst length of 2, 4, or 8 will conclude on its own, if there is no external command
`issued; whereas a full‐page burst will continue indefinitely until an external command
`is issued. Is that fair?
`I would say that the burst length of 2, 4, or 8 in Schaefer will ultimately conclude on
`their own, if allowed, you know, to run to completion. The full‐page burst, at least in
`one embodiment that Schaefer talks about, will wrap around and restart until it's ‐‐ it
`says at least in Column 5, until a burst termination command or precharge command
`is indicated by the command controller, or until interrupted with another burst
`operation.
`
`A.
`
`EX1029, Brogioli Dep. at 36:5‐25; Petitioner’s Reply at 3, 12‐13
`
`31
`
`
`
`Overview
`
`•
`
`•
`
`’134 Patent
`– Purports to have developed “non‐interruptible” burst memory
`Schaefer
`– Schaefer discloses “non‐interruptible” burst operations
`– A user command is issued at T2 before the precharge is initiated.
`– PO’s Expert concedes that the only user command is issued at time T2
`– Petitioner’s Expert confirms Schaefer’s disclosure
`– PO’s Expert reliance on “termination” commands is not applicable
`– Schaefer’s purported goals do not negate anticipation
`
`32
`
`
`
`Schaefer | Schaefer’s purported goals do not negate anticipation
`
`PO cannot negate Schaefer’s anticipating disclosure by pointing to Schaefer’s purported
`goals.
`
`The law of anticipation does not require that the
`reference “teach” what the subject matter of the
`patent teaches . . . . It is only necessary that the
`claims under attack, as construed by the court, “read
`on” something disclosed in the reference.
`
`Kalman v. Kimberly‐Clark Corp., 713 F.2d 760, 772 (Fed. Cir. 1983), overruled in part on other grounds, SRI Int'l v.
`Matsushita Elec. Corp. of Am., 775 F.2d 1107, 1125, 227 (Fed. Cir. 1985) (in banc); Petitioner’s Reply at 11
`Schaefer’s separate disclosure of circuitry for reducing time between bursts sheds no
`light on how a POSITA would interpret Schaefer’s unrelated disclosure of a fixed length
`burst with AUTO‐PRECHARGE.
`
`33
`
`
`
`Schaefer | Schaefer’s purported goals do not negate anticipation
`
`Allowing interrupts to reduce clock cycles before the internal PRECHARGE operation
`automatically begins would negate the stated advantage of AUTO‐PRECHARGE.
`
`As Schaefer states, “[b]y using the AUTO-PRECHARGE command feature, a
`manual PRECHARGE command does not need to be issued” and, instead, “the
`precharge is initiated at the earliest, valid stage within a burst cycle.”
`
`Petition at 10 (quoting Schaefer (EX1017) at 7:38‐43
`If such a burst were terminated prior to that “earliest, valid stage with a burst cycle,”
`which Schaefer explains is after the reads or writes are complete, then the benefit of
`AUTO‐PRECHARGE (including saving bus usage) would not be obtained.
`
`34
`
`
`
`Schaefer | Petitioner’s Expert confirms Schaefer’s disclosure
`
`Petitioner’s Expert explains why a POSITA would understand Schaefer’s plain language
`to bar user commands from T2 to T9.
`
`82. … The goal of READ WITH AUTO-PRECHARGE is to save cycles
`and command bus usage (a separate PRECHARGE command is not required
`here). Thus, the internal operation of this command (“READ WITH AUTO-
`PRECHARGE”) is structured to make these elements come true, which
`requires non-interruption to allow the implementation to be simple & operate
`at high speed. In Schaefer’s Figure 4, the next ACTIVE command can occur
`BECAUSE the precharge has already been done automatically. Without that,
`a new PRECHARGE command would be required before the next
`ACTIVATE command is received.
`
`Murphy Dec. (Ex. 1015) at ¶ 82
`
`35
`
`
`
`Schaefer | Schaefer’s purported goals do not negate anticipation
`
`Patent Owner argues also that Schaefer is concerned with eliminating wasted
`cycles between burst operations, not preventing interruptions within a burst.
`Prelim. Resp. 42–43. That focus, according to Patent Owner, gives reason not to
`interpret Schaefer’s disclosures as including the initial burst period within the
`precharge-period prohibition on user commands. Id. That argument is not
`persuasive because Schaefer’s disclosures, as explained above, show that user
`commands are prohibited during the entire period from the initial read/write
`command to the completion of the precharge operation.
`
`Institution Decision at 12‐13
`
`36
`
`
`
`Additional Slides
`
`Additional Slides
`
`37
`
`
`
`Schaefer | Discloses “non‐interruptible” burst operations
`
`PO asserts conflicting interpretations regarding the prohibition period.
`(entire precharge period tRP vs. portion of precharge period tRP)
`
`Entire Precharge Period tRP (T6‐T9)
`
`Portion “During” Precharge Period (e.g. T8‐T9)
`
`“The prohibition of issuing another command is
`limited to the precharged time (tRP).”
`
`“Accordingly, the POR clearly identified the
`starting and ending time, i.e., the precharge
`time (tRP), of the prohibition of issuing
`another command. “
`
`“Schaefer goes on to describe how the prohibition
`on user commands preventing access to the bank
`memory array during the precharged time tRP
`would work for various periods of tRP. Critically,
`according to Schaefer, each period of tRP—during
`which user commands are prohibited—begins
`after completion of the previous burst cycle (Ex‐
`2006, ¶120)”
`
`PO Sur‐Reply at 2, 7
`
`POR at 44‐45
`
`38
`
`
`
`Schaefer | Discloses “non‐interruptible” burst operations
`
`PO’s conflicting interpretation asserts that Schaefer’s prohibition is limited to the time
`“during” the precharged time tRP , “after completion” of the previous burst cycle. (e.g. two
`clock cycles within a three clock cycle tRP)
`Schaefer goes on to describe how the
`prohibition on user commands preventing
`access to the bank memory array during
`the precharged time tRP would work for
`various periods of tRP. Critically,
`according to Schaefer, each period of
`tRP—during which user commands are
`prohibited—begins after completion of
`the previous burst cycle (Ex-2006, ¶120):
`
`For example, if a read of two cycles is selected and
`three clock periods are required to satisfy tRP the bank
`memory array cannot be accessed during the two
`clocks following the completion of a burst operation.
`If a burst of four is programmed and three clock periods
`are required to satisfy tRP, the bank memory array
`cannot be accessed during the one clock cycle
`following the completion of the burst, provided that
`the read latency is two or more clocks, otherwise, the
`bank memory array cannot be accessed during the
`two clocks following the completion of the burst cycle.
`
`POR at 44
`
`Schaefer (EX1017) at 7:47‐58; POR at 45
`
`39
`
`
`
`Schaefer | Technology Overview
`
`Schaefer discloses “non‐interruptible” burst operations.
`
`Schaefer (EX1017) at Fig 1 (annotated)
`
`40
`
`
`
`Schaefer | Technology Overview
`
`Schaefer discloses “non‐interruptible” burst operations.
`
`• Before performing any operational
`command, Schaefer’s mode register 40
`[annotated in brown] is set or
`programmed.
`• Burst lengths of 2, 4, 8, or full page
`(1,024) cycles are programmable into
`mode register 40.
`• After programming, Schaefer discloses
`performing a non‐interruptible read or
`write burst operation in response to an
`ACTIVE command followed by READ with
`AUTO‐PRECHARGE or WRITE with AUTO‐
`PRECHARGE command.
`
`Schaefer (EX1017) at 4:1‐3, 6:1‐3; Murphy Dec (Ex. 1015) at ¶ 73
`
`Schaefer (EX1017) at Fig 1 (annotated)
`
`41
`
`
`
`’134 Patent | Technology Overview
`
`• The logic circuit (102) [yellow]
`generates multiple internal address
`signals (ADDR_INT) are fed into a
`memory (104) [blue] to write/read
`burst data to/from the memory (104).
`• The memory (104) is where data is
`stored (a “write” operation) or
`accessed (a “read” operation).
`
`’134 Patent (EX1001) at 2:26‐30, 61‐65, 3:2‐4
`
`’134 Patent (EX1001) at Fig 1
`
`42
`
`
`
`’134 Patent | Technology Overview
`
`• The logic circuit (102) generates the
`predetermined number of internal address
`signals when the address counter register
`(126) receives (i) an external address signal
`(ADDR_EXT), (ii) a clock signal (CLK) and (iii)
`one or more control signals.
`• Once the circuit (102) has started
`generating the fixed number of addresses,
`the circuit (102) will generally not stop
`until the fixed number of addresses has
`been generated (e.g., a non‐interruptible
`burst).
`
`’134 Patent (EX1001) at 3:25‐29, 3:65‐4:1
`
`’134 Patent (EX1001) at Fig 2
`
`43
`
`
`
`Schaefer | Technology Overview
`
`• Each of READ and WRITE with AUTO‐
`PRECHARGE are burst operations in
`which reads or writes to a series of
`column locations in the activated row
`proceed automatically after receiving a
`single external address.
`
`•
`
`Importantly, during a burst operation
`with AUTO‐PRECHARGE, “[t]he user is
`not allowed to issue another command
`until the precharged time (tRP) is
`completed.”
`
`Murphy Dec (EX1015) at ¶ 75
`
`By using the AUTO-PRECHARGE command feature, a
`manual PRECHARGE command does not need to be
`issued during the functional operation of SDRAM 20. The
`AUTO-PRECHARGE
`command
`insures
`that
`the
`precharge is initiated at the earliest, valid stage within a
`burst cycle. The user is not allowed to issue another
`command until the precharged time (tRP) is completed.
`Therefore, when an AUTO-PRECHARGE command is
`employed in SDRAM 20, the selected bank memory array
`must not be accessed again until tRP, is complete.
`
`Schaefer (EX1017) at 7:38‐48
`
`44
`
`
`
`Schaefer | Technology Overview
`
`As shown in FIG. 4 below, by using the Read/Write with AUTO‐PRECHARGE command, the internal
`AUTO‐PRECHARGE command is automatically initiated at time T6 (i.e. the precharge is initiated).
`
`By using the AUTO-PRECHARGE command feature,
`a manual PRECHARGE command does not need to be
`issued during the functional operation of SDRAM 20.
`The AUTO-PRECHARGE command insures that the
`precharge is initiated at the earliest, valid stage within
`a burst cycle. The user is not allowed to issue another
`command until the precharged time (tRP) is completed.
`
`Schaefer (EX1017) at 7:38‐45
`
`FIG. 4 is similar to FIG. 2 except at time t6 a NOP
`command is issued rather than the PRECHARGE
`command since at time t6 the AUTO-PRECHARGE
`command is internally performed.
`
`Schaefer (EX1017) at 8:65‐9:1
`
`Schaefer (EX1017) at Fig 4; Murphy Dec (Ex. 1015) at ¶ 74
`
`45
`
`
`
`Patent Owner’s Arguments Fail
`
`Dr. Brogioli concedes that there is no other user (external) command from T2 to T9
`other than the command issued at T2.
`
`Q. And the ‐‐ and again, now I'm going more general and
`somewhat going back to ‐‐ to Schaefer. When Schaefer
`describes a read burst with auto‐precharge, it's the same
`kind of simplification, in the sense that in the prior ‐‐
`without auto recharge, the system has to issue two
`commands: First a read burst, and then at the conclusion of
`that read burst, a precharge external command; whereas if
`you use auto‐precharge, the user only has to issue a single
`command, external command ‐‐ the read with auto
`precharge – and internally, the operations that would be
`performed is the burst read, as well as the precharge
`operation. Correct?
`A. I would say one of the things Schaefer contemplates is
`reducing unused cycles in this multi‐step process of a burst
`and a precharge. And so the read with auto‐precharge,
`going back to – I guess Figure 4
`
`of Schaefer, I think it is ‐‐ that’s a single command that's
`issued at that time T2 in Figure 4, with subsequent, you
`know, multiple phases that occur after the issuance of the
`command.
`Q. And one of the phases that occurs after the issuance of
`the command is the precharge phase, correct?
`A. So I'll stick with Figure 4, just to ‐‐ for th
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