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`T_l TERMINAL
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`NOTICE OF ALLOWANCE MAILED
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`i_.. The term of this .:atent shall
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`i_J The terminal _months of
`this patent have been disclaimed.
`
`Date Paid
`
`Amount Que
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`WARNING:
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Otfice is reslricted to authorized employees and contractors only.
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`Form PTO-436A
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`EX1004
`Page 1 of 186
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`

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`PATENT APPLICATION SERIAL NO.
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`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
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`Page 3 of 186
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`

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`fi le:///c:/APPS/preexam/correspondence/ Lhhn
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`l||il|iltil||l|ililililtilililIfi ililtililililtl|tilff ililil[ilil
`Bib Data Sheet
`
`UNITED STATES DEPARTMENT OF COMMERCE
`Patent and Trademark Office
`Address: COMMISSIONER OF PATENTS AND TRADEIVI{RKS
`Washington, D.C. 20231
`
`SERIAL NUMBER
`091504.344
`
`FILING DATE
`02t14t2000
`
`RULE
`
`CLASS
`ffi
`.-? //
`
`GROUP ART UNIT
`
`' .*24y)91
`
`ATTORNEY
`DOCKET NO.
`0325.000309
`
`\PPLICANTS
`Cathal G. Phelan, Mountain View, CA;
`- CONTINUING-DATA ************************* n O'n e
`
`/v) r
`
`FOREIGN APPLICATIONS
`
`/]a,/
`
`F REQU|RED, FORETGN FtLtNG LTCENSE GMNTED **
`.0510212000
`
`:oreign Priority claimed
`
`!5 USC '1 19 (a-d) conditions
`nel
`/erified and
`\cknowledged
`\DDRESS
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`)21363
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`flyu, E|1o
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`\
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`STATE
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`/
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`'CLAIMS
`l1lt
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`- SHEETS
`DRAWING5/
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`NDEPENDENT
`CLAIMS
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`: Authority has been given in Paper
`to charge/credit DEPOSIT ACCOUNT
`for following:
`
`4t"prl,,v,ufrllx
`f,l nttF"et
`Itr r.ro Fees ( Filing )
`J Ln Fees ( Processing Ext. of
`time )
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`FILING FEE
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`690
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`tlo.
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`
`l of 1
`
`5/2/0011:39AM
`
`Page 4 of 186
`
`

`

`OL- 15-o':
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`-11#9,B=3
`=--'e#lE:Ya-*
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`CHRISTOPI{ER P. MAIORANA, P.C.
`g
`24025 Greater Mack, Suite 200
`St. Ctair Shores, Michigan 48080
`=
`l* E"
`Uriiity patent Application Transmittal
`:g
`(Only for new non-provisionafapplications Under 37 CFR 1.53(b)
`I-,qES
`=S
`:Cl
`|/rr
`ASSISTANT COMMISSIONER FOR PATENTS
`Case Docket No.0325'000308
`=
`washington, D. c. 20231
`Date:February 14" 2000
`
`Sir:
`
`Transmitted herewith for filing is a patent application of:
`
`Inventor(s): Cathal G. Phelan
`FoT:
`
`FIXED BLIRST MEMORIES
`
`Enclosed are:
`
`Specification (13 pages); Claims (4 pages); Abstract (1 page)
`
`5 sheets of formal drawings.
`
`Total Pages 2
`Oath or Declaration
`a. X Newly executed (original or copy)
`b.
`Copy from aprior application (37 CFR 1'63(d)
`(for continuation/divisional with Item 5 completed)
`c.
`Copy of Revocation of Previous Power
`
`X X
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`X
`
`Incorporation By Reference (usable if Item 3b is checked)
`The entire disciosure of the prior application, from which a copy of the oath or
`declaration is supplied under Item 3b, is considered as being part of the disclosure
`of the u..o*punying application and is hereby incorporated by reference therein.
`
`If a Continuing Application, check appropriate box and supply the requisite
`information below and in a preliminary amendment:
`_ continuation Divisional
`of prior application no.:
`
`continuation-in-part (cIP)
`
`1
`
`2.
`
`3.
`
`4.
`
`5,
`
`6.
`
`X
`
`--
`An assignment to CYPRESS SEMICONDUCTOR CORP' along with PTO form
`1595.
`
`A PTO Form 1449 with a copy of the references not previously cited.
`
`8.
`
`9,
`
`X
`
`Return Receipt Postcard
`
`Other:
`
`Page 5 of 186
`
`

`

`The
`
`ltlmg f.ee has been calculated as shown below:
`No. Filed
`No. Extra
`
`Page2 of2
`
`Fee
`
`Amount
`
`$690.00
`$ 0.00
`$ 0.00
`$ 0.00
`.. . $690.00
`. S
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`r<" €'
`.€.:o,-f.t
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`x $ 18.00
`x $ 78.00
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`0
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`
`Basic Fee
`
`Total Claims
`
`Indep. Claims
`
`Mult. Dep. Claims
`
`$260.00
`s{tB-ToTAL
`SMALL ENTITY STATUS (divide SUB-TOTAL by two)
`AssignmentRecordarFee($40.00L
`: : :. : : : : :. :. :. :. : : : :.. : $7i&ffi
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`A check in the amount of $730.00 to cover the filing fee is enclosed.
`
`The Commissioner is hereby authorized to charge any fees under 37 CFR l.16 and,1.17
`which may be required by this paper or associated with this filing to Deposit Account No.
`50-0541. A duplicate copy of this sheet is enclosed.
`
`Correspondence Address :
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`Customer Number or Bar Code Label:
`
`I llilil tlill il|il illlt iltlt |ilil llil ltll
`021383
`FiIEtlI TiMffil OFFICI
`
`CERTIFICATE OF' EXPRESS MAILING
`
`I hereby cerlify that this paper (along with any paper referred to as being attached or enclosed) is being deposited with the
`United States Postal Service via Express Mail Label No. EL417953316US in an envelope addressed to: BOX PATENT
`APPLICATION, Assistant Commissioner for Patents, Washington, D.C,. 20231,
`{
`
`By:
`
`Date: February 14,2000
`
`Attornev Docket No.: 0325.00309
`
`Chris
`Reg. No.
`
`P. Maiorana
`
`P. MAIORANA, P.C.
`24025 Greater Mack, Suite 200
`St. Clair Shores, Michigan 48080
`(810) 4e8-0670
`
`Page 6 of 186
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`

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`t
`
`\ 1
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`\
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`0325.00309
`cDg9073
`
`Field of the fnvention
`
`The present invention relates to memory devices general-ly
`particularly,
`
`to a memory device t.hat, transfers a fixed
`
`a nrl mn ro
`
`number of
`
`words of data wit.h each access.
`
`Backqround of the Invention
`
`A synchronous Static Random Access Memory (SRAM) can
`provide data from multiple address locations using a single
`address. Accessing multiple locat.ions in response to a single
`address is called a burst mode access. A memory device Lhat
`provides a burst. mode can reduce activity on the address and
`control buses. The burst. mode of a conventional synchronous SRAM
`
`Can be Staft.ed
`
`.
`
`rnd ar-annarl i n rFgn1-1nse f O a COnt1.Ol Signal
`A convent.ional- Dynamic Random Access Memory (DRAM)
`preserves data during periodic absences of power by implement.ing a
`memory cell- as a capacitor and an access transist.or. Since the
`charge on the capacitor will slowly leak away, the cells need to be
`"refreshed" once every
`few milliseconds.
`
`frequency of accesses, a conventional DRAM can need an interrupt
`
`t.o
`
`Depending on the
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`Page 7 of 186
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`

`

`I
`
`interrupts)
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`devices due
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`burst.s can
`
`be
`
`a325.00309
`cD99073
`perform dat.a refreshes. Using a DRAM in a burst. application is
`difficult
`because of t,he need to refresh. Completely hiding
`refresh cycles (e.g.,
`refreshing data without the need for
`in a DRAM cannoL happen with conventional_ memory
`architecture choices that have been made. Data word
`interrupted wh1le in progress since conventional
`architectures support both burst and single access modes.
`Convent.ional- DRAM access takes about l-0ns to geL data, buL nearly
`2Ons to complet.e writeback and equalization. The addition of
`another 20ns for a refresh results in a total access of 40ns.
`Since the dat.a burst transfers of convenLional memories
`can be interrupted and single accesses made, the amount of time
`that the data, address and control busses are not in use can vary.
`The variability of bus availabiliLy complicat.es the design of
`svstems wi fh sharerj dafa address and control busses.
`' It would be desirable to have a memorv device that has a
`fixed burst lenqth.
`
`,
`
`sss!epp
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`*--
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`-
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`
`Summary of the Invention
`The present invention concerns an integrated circuit
`comprising a memory and a logic circuit.. The memory may comprise
`
`2
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`of i-nternal address
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`
`0325.00309
`cD99073
`a plurality of storage elements each configured to read and writ.e
`dat.a in response to an internal address signal. The logic circuit
`may be configured t.o generate a predetermined number of the
`internal address signals in response to (i)
`an ext,ernaf address
`signal, (il) a clock slgnal and (iii) one or
`The generation of the predetermined number
`signals may be non-interruptible.
`The objects, feat.ures and advantages of the present
`invenLion include providing a fixed burst memory that may (i) give
`network customers who typically burst large data lengths t.he
`ability
`to set a fixed burst. length that. suits particular needs;
`(ii) have non-interruptibte bursts; (iii)
`free up t.he address bus
`and control bus for
`(iv) provide
`number of cycles;
`programmability for set.ting the burst lengt.h by using DC l-evel-s
`[Vss or Vcc] on externa] pins; (v) hide required DRAM refreshes
`inside a known f ixed burst length of dat.a words ; and.f or (vi )
`operate at higher frequencies wlthout. needing interrupts to perform
`refreshes of data.
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`0325.00309
`cD99073
`Brief Description of the Drawinqs
`These and other objects, feat.ures and advantages of the
`present invention will be apparent, from the following detailed
`description and the appended claims and drawings in which:
`FIG. 1 is a block diagram ill-ustrating a preferred
`embodiment of the present invention;
`FIG. 2 is a detailed block diagram il-lust.rating a circuit
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`alt.ernative embodiment of the circuit
`I02 of FIG.
`
`I02,
`
`FIG. 4 is a flow diaqram illustraLinq an example burst
`
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`F]GS. 5A and 5B are diagrams illustrating
`example
`4 word (FIG. 5A) and an B word (FIG. 58) fixed
`operarrons oI a
`ts-i^'.^
`^F
`burst access in accordance with the present invention; and
`FfG. 6 is a diaqram illust.rating an example operation
`where a burst length may be long enough to include a writeback and
`a refresh cvcle.
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`0325.00309
`cD99073
`Detailed Description of the Preferred Embodiments
`Referring t.o FIG. I, a block diagram of a circuit, 1-00 is
`shown in accordance with a preferred embodiment of the present
`invention. The circuit 100 may be implemented, in one example,
`a fixed burst memory. The circuit 100 may be configured
`to
`transfer a fixed number of words of data with each access (e.g.,
`read or write) . A number of words Lransferred as a group is called
`a burst. The circuit 100 generally comprises a circuit. I02 and a
`memory array (or circuit.) L04. The circuit t02 may be implemented,
`
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`. The memofy
`array IA4 may be implement.ed, in one example, ds a st.atic random
`access memory (SRAM), a dynamic random access memory (DRAM), or
`other appropriat.e memory to meeL the design criteria of
`part icular j-mr:lementation.
`
`The circuit 1-02 may have an input, 106 t.hat may recej-ve a
`signal (e.g., ADDR_EXT) , an input 108 t.hat may receive a signat
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`an input IL2 that may receive a signal (e.g., ADV), and an input
`II4 that may receive a signal (e.9., BURST). The circuiL 102 may
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`0325.00309
`cD99073
`that may receive a signal (e.g. , R/Wb) , dfl input. l-22 t.hat. may
`receive a signal (e.9., DATA_IN) and an output L22 that may presenL
`a signal (e.9., DATA*OUT). The various signals are generally "on"
`(e.9., a digital HIGH, or 1) or ,.off, (e.g., a digital LOW, or 0) .
`However, the particular polarit.ies of the on (e.g., asserted) and
`(e.g., de-asserted) st.ates of Lhe signals may be adjusted
`off
`(e.g., teversed) accordingly to meet the design crj-teria of a
`particular implementat.ion.
`
`.
`
`an inl-ar-ror
`qrr rrlLu::s!
`
`The signal ADDR_EXT may be, in one example, dD ext.ernal
`address signal. The signal ADDR_EXT may be n-bits wide, where n is
`Tho qianal
`?T.v
`rrrv uryrrqr elrL may be a clock signal
`. The signal R/Wb
`may be a control signal LhaL may be in a first state or a second
`state. When the signal R/Wb j-s in the first state, the circuit 100
`wi]1 generally read data from the memory circuit.
`]-o4 for
`presentation as Lhe signal DATA our. when the signal R/wb is in
`the second state,
`the circuit 100 will generally store data
`received as the siqnal DATA IN.
`
`The signal LOAD may be, in one example, drl address load
`control- signal. The circuit 100 may be configured. to load an
`initial address, present.ed by the signal ADDR_EXT, in response co
`the signal LOAD. The initial address may determine the initial
`
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`12 of 186
`
`

`

`032.5.00309
`cD99073
`Iocation where data Lransfers
`
`to and from the memory 104 will
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`The signal ADV may be, in one example, used as a control
`rrrs circuit 100 may be configured t,o transfer a fixed
`^-i -^,,-i
`number of words to or from the memory IO4 in response to the
`signals ADV, CLK and R/Wb. When t.he signal ADV is asserted, Lhe
`circuit ,100 w1l1 generally begin transferring a predetermined
`number of words. The transfer is generatly non-interrupLibl-e. In
`*,,. -. --r,,___". --
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`of addresses for presentation as the signal ADDR INT.
`
`The signals ADV and'LOAD may be, in one example, a single
`signal (e.g., ADV/LDb) . The signal ADV/LDb may be a control signal
`that. may be in a first staLe or a second sLate. When the signal
`ADV/LDb is in the first st,ate, the circuiL 102 will generally load
`an address presented by t.he signal ADDR_EXT as an initial address.
`When t.he signal ADV/LDb is in the second state, the circuit. 1-02 may
`
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`be,
`
`addresses in response to t.he signal CLK. The signal ADDR_INT may
`in one example, an internal- address siqnal.
`ADDR_INT may be n-biLs wide. Once the circuit L02 has started
`I02 will
`generating the fixed number of addresses, the circuit
`
`The signal
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`13 of 186
`
`

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`0325.00309
`cD99073
`generally noL st.op until- the fixed number of addresses has been
`generated (e .g. , a non- int.erruptible burst ) .
`The signal BURST may be, in one example, a configuration
`!v! orogrammi-ng the fixed number of addresses that the
`cj-rcuit " La2 may generate in response to the signals cLK and
`^Dv/ r,rJrr. rne signal BURST may be generated, in one example, by (i)
`using bond opt,ions, (ii) voltage levels applied to external pins ,
`or (iii) oLher appropriate signal generation means.
`When the memory 104 is implemented as a DRAM, the circuit.
`100 may be configured to hide required DRAM refreshes (e.g.,
`refreshes may occur wit.hout. affecting ext,ernal environment) inside'
`a known fixed burst length of data words. The fixed burst lengLh
`may allow the circuit
`l-00 to operate at. higher frequencies t.han a
`conventional DRAM wiLhout neerjincr int. arrrrnf s f n nerfnrm refreshes
`of data.
`rn one example, the fixed burst length may be four or
`eight words. However, the burst length may be set. t.o whatever
`length is necessary to meet the design criteria of a particular
`applicat.ion. For example, the burst lengt.h may be programmed, in
`one example, to allow both writeback and refresh Lo occur within a
`single access. The fixed burst length may be set, in one example,
`
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`14 of 186
`
`

`

`I
`
`032s.00309
`cD99073
`longer or shorter depending upon a frequency ar Lechnology to be
`used.
`
`l-rrrrct-
`
`The clrcuit 100 may be configured to provide a fixed
`vulpu rsrryLrr that may suit the requirements of nelwork cusLomers
`'l ana{-l-r
`who typically burst large data lengtirs. By providing a fixed burst
`length, the circuit 100 may allow shared usage of dat.a, address and
`control 'busses. A flxed length non-interrupt.ible burst. generally
`frees up the address bus and conlrol bus for a known number of
`cycles. The address and control busses may be shared by a number
`of memory devices. The circuit 100 may provide a more reliable and
`/or accuraLe bursL than is possible wit.h multipl.e chips.
`Referring
`to FIG. 2,
`detailed block diaqram
`illustrating
`implementation of the circuit 1,02 is shown. The
`circuit. I02 may comprise an address count,er register ],26 and a
`bursL counter I2B. The address counter register 126 generally
`receives the signals ADDR EXT, LOAD, and cLK. The address counter
`register 126 may be configured to present the signal ADDR INT. The
`signal ADV and the signal- BURST may be presented to a burst counter
`L2B. The signal CLK may be presented at an input 130 of t.he burst
`counter 128. The burst counter l2B may have an output 132 t.hat may
`present. a signal (e.g., BURST cLK) at an input !34 of t.he circuit.
`
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`15 of 186
`
`

`

`0325.00309
`cD99073
`1-26. An init.ial address may be loaded into the address counter
`address in the signal
`register L26 by presenting the initial
`ADDR_EXT and asserting the signal LOAD. The circuit L26 may be
`configured Lo increment an address in response to the signal
`BURST CL,K. When the Signal ADV is asserted, the burst counter L28
`will generally present the signal BURST-CLK in response to Lhe
`signal cT-,K. The signal BURST_CLK generally contains a number of
`pulses that has been programmed by Lhe signal BURST'
`Referrinqt,oFIG'3,ad.etailedblockdiagram
`illustrating an alternative embodiment of the cj-rcuit' l-02 is shown'
`The circuit 102'may compri-se a latch 134, a mult,iplexer 136 and a
`counLer 13g. The signals ADDR_EXT, LOAD and Cr.,K may be presented
`to t,he lat.ch L34. The latch 1-34 may have an outpuL 140 that may
`present a portion (e.g., mbits, where m is an integer smaller than
`n) of the signal ADDR_EXT as a portion of the signal ADDR-INT, an
`output 1-42 that may present a second port.ion (e.g., k bits, where
`.k is an rnteger smaller than n) of the signal ADDR-EXT to a first
`input of the multiplexer L36, and an ouLput I44 that may present
`the second portion of the signal ADDR-EXT to an input L46 of the
`counter 138.
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`16 of 186
`
`

`

`0325.00309
`cD99073
`
`The signals ADV, CLK and BURST may be presenLed to inputs
`of the counter 138. The counter 138 may be configured to generate
`a number of addresses in response t.o the signals CLK, BURST and
`ADV. The number of addresses generated by t.he counter 138 may be
`
`i
`
`I
`
`an
`
`programnted by t,he signal BURST.
`The signal BURST may be presented to a control input of
`t.he mulLiplexer 136. The mult.iplexer 135 may select between a
`number of signals from the latch L34 and a number of signals from
`the counter l-38 t.o be presented as a second portion of the signal
`ADDR INT in response t.o t.he signal BURST.
`Referring to FfG. 4, a flow diagram illustrating
`example burst. address sequence is shown. When the signal ADV is
`asserted - fhe circuit 100 will generally generate a number of
`address signals, for example, N where N is an integer. The address
`signals may be generaled, in one example, ofl a rising edge of the
`signal CLK. The address signals will generally continue to be
`generated until the Nth address signal i-s generated.
`timing diagrams
`Referring Lo FIGS. 5A and 58,
`illustrating example operations for a four word (FIG. 5A) and an
`elght word (FIG. 58) fixed burst memory in accordance with the
`present. invention are shown. The timing diagrams generally
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`

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`1
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`I
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`
`0325.00309
`CD99O73
`illustrate externally measurable signals for four and eight word
`fixed burst read/write architectures.
`fn general, dD operation
`(e.g., read or writ.e) of t.he circuit. 100 begins with loading an
`init.ial address (e .g. , portions t5O, !54 , and 1-58 of FIG. 5A;
`portions l-50' , 1-54' , and l-58' of FIG. 58) . Starting with the
`initial address,
`fixednumberofwordsaregenera11yLransferred
`(e .9. , Line DQ of
`FIGS. 5A and 58) . During the transf er of t.he
`fixed number of words, the address and control buses (e.g., ADDR,
`cE, R/w, etc. ) are generalJ-y available to other devi-ces (e. g. ,
`port.ions 1,52, 1-56, and 160 of FIG. 5A; portions L52' , l-56' , and
`160' of FIG. 5B).
`In one example, the control and address bus
`act,ivity may be one-fourth (FIG. 5A) or one-eighth (FIG. 58) the
`data bus actilrir-rr (a a
`^^npare line ADDR with line DQ of FIGS. 5A
`and 58). The reduced bus activity may be an effect of the
`architecture. The data bus may be, in one example, active nearly
`l-00? of the Li-o (a a
`I ino DQ of FIGS. 5A and 58) In one example,
`t.here may be no inefficiencies swltching from read to write t.o read
`
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`5A and 58) .
`
`Referring to FIG. 6, a timing diagram illustrating
`fixed burst lengt.h long enough to hide a writeback and a refresh
`cycle is shown.
`Internally
`the action being performed may
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`

`

`4325.00309
`cD99073
`completel-y hide DRAM ref resh act.ivit,y inside nominal external
`acLivities. A port.iorr L62 il-lustrates that refresh activiLy (e.g.,
`writ.eback, read for refresh, and writ.eback for refresh) may be
`completed within the time of the burst Lransfer. When a fixed
`burst. long enough to completely hide refresh activit.y is provided,
`t.here may be no penalty for us:.ng DRAM instead of SRAM for the
`
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`hile the invention has been particul-arly shown and
`described with reference to fhc nrcfarrcql embodiments thereof, it
`will be understood by those skilled in the art, t.hat various changes
`in form and details may be made wit.hout departing from the spirit
`and scope of the invention.
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`

`

`0325.00309
`cD99073
`
`el-ements each
`
`an internal
`
`I
`
`"-'T-"
`1 - An inf rrorated circluit comprising:
`a memory comprising a n{urafity of storage
`configured to read and write
`ta in response to
`address *signal; and
`a logic circuit configu
`number of said internal- address
`exLernal address signal, (ii) a cl
`control signals, wherein said ge
`number of internal address signals
`
`I ;
`
`'
`
`to qenerate a predetermined
`ignals in response t.o (i) an
`k signal and (iii) one or more
`rat j-on of said predet,ermined
`is non-inLerruptible.
`
`The inteqrated circu
`said predetermine number of internal
`by a fixed burst. lengt.h.
`
`accordi-ng to claim
`
`1, wherein
`
`address slgnals is
`
`determined
`
`3.
`said predetermined
`
`The
`
`i nl-anraf
`
`ad
`
`c].rcul-
`
`according to claim 1, wherei-n
`
`number of
`
`i-nt.erna
`
`address siqnals is 4.
`
`4.
`
`The
`
`integrated
`
`circuit,
`
`ccording
`
`to claim 1-, wherein
`
`said nrcdcl-crmined
`
`number of
`
`internal-
`
`ddress
`
`signals is 8.
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`

`

`4325.00309
`
`5.
`
`I
`according to claim 2, wherein
`The integraLed cifuit
`fixed burst, length is progrpmmable.
`
`6.
`The int.egrated ci*cuit according to cl-aim 5, wherein
`said fixed burst, length is pro{rammed by bond opt.ions.
`
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`5, wherein
`Ievel-s on
`
`1, wherein
`
`1, wherein
`
`9, wherei-n
`
`chosen t,o
`
`I I II
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`
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`
`. 7 . The int.egrated cfcuit according to claim
`said fixed burst lencrth is
`fprogrammed by voltage
`exLernal pins.
`
`B. The int.egrated c[rcuit accordi-ng to claim
`said memory comprises a static lrandom access memory.
`
`I
`
`I I II
`
`I I I I I
`
`g.
`
`The inf r-crrel-"a .{t"rrit according to claim
`said memory comprises a dynamicl random access memory.
`
`I I
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`
`l-0. The integrated ci[cuit according to claim
`saicl nroric]- o.mined number of intLrna] address signals is
`nrnrlide t-imo for writeback rna l"fresh cycles.
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`21 of 186
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`

`

`I
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`int.egrated circuid according t.o claim 1, wherein
`
`II
`
`JI
`
`said predetermined
`
`meef nredel-crmined
`I/& usv
`
`uvr
`
`!r
`
`criteria
`
`number of internan- address signals is chosen to
`for sharlng address and control busses.
`
`L2. An integrated
`
`circui
`
`comprising:
`
`and w iting data in response to an
`
`means for reading
`internal address signal; and
`means for generating
`
`i-nternal
`
`^ .: ^* ^ 'l
`b -L91rdr
`
`/
`
`wherein
`
`address
`
`address signals in res
`(ii) a clock signal apd (
`said generation of said
`signals is non-interrupt
`
`oredetermined number
`nse to (i) an external
`ii) one or more control
`
`of said
`
`address
`
`signals,
`
`redetermined number of
`
`internal-
`
`1e.
`
`l-3. A method of Drov dinq a fixed burst, lenqt,h dat.a
`transfer comprising the steps of
`
`g data to a memory in response Lo
`
`readinq from and writi
`an internal address signal; and
`generating a predet.e
`ined number of said internal
`signals in response to (i an external address si-gnal, ( j-i)
`signal and (iii) a contro signal, wherein said generation
`
`address
`
`a clock
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`22 of 186
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`

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`V t
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`032s.00309
`l)n \ ) cDeeoT3
`v"//
`of said predeterrnined nurnber of
`
`signals is non- lntern:ptible .
`
`14 .' The method accorAi-rfS to claim 13, further comprising
`1-hc qf orr nf nr
`I,rogramming said predptermined number.
`
`I
`
`I I I I
`
`l-5 . The met.hod u""or{ir,g to claim 14, wherein said
`programming step is performed
`""ifnS bond. options.
`
`I
`
`I I
`
`L6. The method .."o/Urnn t.o claim 14, wherein said
`programming step is performea lrJing voltage leve1s.
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`L7 . The method accorJr"n to claim 13, further comprising
`t.he step of selecting said pt.O{"rmined. number to provide tlme for
`writeback and refresh cycles.
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`23 of 186
`
`

`

`0325 . 003 09
`cD99073
`
`5
`
`ABSTRACT OF THE DISCLOSURE
`An integrated clrculL comprising a memory and a logic
`The memory may comprise a plurality of storage elements
`circuit.
`each configured to read and write dat,a in response to an internal
`address signal. The logic circuit may be configured to generaLe a
`predetermined number of the internal address signals in response to
`(i) an e'xternal address signal, (ii) a clock signal and (iii) one
`i;;3 or more control signals. The generaLion of the predetermined
`'i,rrijii"i
`nrrmi-ror nf internal address signals may be non-interrupt.ible.
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`25 of 186
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`ADDR-'NT
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`FIG.2
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`LAAD
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`CLK
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`ADV
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`BURST
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`ADDR_IN'T
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`l,#i
`
`LOA D
`
`CLK
`
`flbv
`
`BuRs-r
`
`27 of 186
`
`

`

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`';.j it
`j;,d
`
`r,,i;i
`
`
`
`i.-.ii
`
`trd
`iy
`
`seal
`2%
`tt
`li
`
`\ndhrts )vCLK=I
`
`
`G\
`
`" o
`
`Abtl=l
`CLK=l
`
`FIG.4
`FIG. 4
`
`28 of 186
`
`28 of 186
`
`

`

`4-Fixed-Buirst Read/Writq/ Read Timing
`o'l
`l
`
`FIG. 5A
`
`8-Fixed-Burst Read/Write/Read Timing
`l"tl t{z'
`
`clj(
`
`iil
`
`l"
`
`*j
`
`i:'1 ii
`a ier
`
`i,"n
`
`CE'
`RUf
`
`AOV,IOt
`
`re
`00
`
`CLK
`
`BIOR
`
`Dq
`
`Anv.rn^l
`frction
`
`FIG. 58
`
`X)<XXXXKX
`
`FIG. 6
`
`29 of 186
`
`

`

`AbDrJttf
`
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`
`I z'l
`
`PRI.\T OF DRAIVINGS
`s__oila.H#LsJ
`
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`gr
`
`I l I
`
`W;T
`
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`
`l11
`
`ADDR-TXT
`
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`
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`
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`
`EURST
`
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`
`D+rn-tN.
`
`:i
`
`it:
`
`FIG. 1
`
`..'''.'.''.:..,:'..'','':'l.'.'
`
`'!l
`
`30 of 186
`
`

`

`PRIIT OF DRAWThGS
`AT-O3IQ.WI gJ
`
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`FS;:,
`
`. -"-.-'--,",..--..-.
`
`-,*-*ffi
`
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`
`f r4r.
`
`{
`
`ll('
`
`ADDR-'TI-T
`
`- -t
`)2b I
`
`I I
`
`I I I I I I
`
`J
`
`t3z t3tl
`
`FIG.2
`
`I I I
`
`t0b
`
`to8
`
`lso
`
`I
`
`t_
`
`QDDP -E\t-r
`
`LAfrD
`
`eLk
`
`4DV
`
`BURST
`
`{ i-i:
`
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`
`i'i
`
`31 of 186
`
`

`

`PRIITT OF DRAWIhGS
`AS ORICTNALLY FILF
`
`ii,
`ri
`i,
`
`{
`
`iii
`
`lil
`
`ADDR -EYT
`/OA D
`
`CLK
`
`t08
`
`ll0'
`
`ADV
`
`ilt
`
`BURST
`
`t I t'l'
`
`IL-
`
`.loL'
`t_
`
`tsl
`
`FIG.3
`
`ADDR-III-T
`
`ll 12
`
`32 of 186
`
`

`

`PRTJ\T OF DRAWIhGS
`{t-oi!Q,WIsJ
`
`fi
`
`{
`
`it:
`
`rt
`
`6vCr("t
`
`ctK'.l
`
`CL,k?
`
`FIG.4
`
`- t;
`"'r:'
`
`33 of 186
`
`

`

`PRTIT OF DRAINIhGS
`,LS ORICINALLY FILT
`
`/rb
`
`rite
`l,:l
`
`Timing
`
`lLo
`
`FIG. 5A
`
`8 - Fixed- B urst Read /Write/Read Timin g
`l"'l
`
`clJ(
`gE
`
`Rtutt
`AD\rn ot
`ME
`00
`
`CLK
`
`pnR
`
`Dq
`
`J,n.rn^l
`frclion
`
`FIG. 58
`
`xXXXXXK
`
`FIG. 6
`
`34 of 186
`
`

`

`02/n/0A FRI 11:22 FAX 810 498 0673
`
`CHRISTOPEER IIAIORANA PC
`
`@ ooe
`
`Docket No, 0325.00309
`
`DSCLARATION, POWER OF ATTORNEY AI'{D PETIfiON
`
`I, the undersigned inventorn hereby declare that
`
`My residence, post offi.co address anil citi.zenship are given next to my name;
`
`I believe that I am the first, original and soic invcntot ofthc subjcct mattcr claimed in the applioation
`tor patent entitted "IIIDDEN DRAM RETRESH IN FI)ffiD BURST MBMORIES", which:
`X
`
`is submittedherewith;
`
`t1
`r. "i
`
`it,i i
`
`liil
`
`ti:i
`
`rrrrEi
`
`r;'i r
`i;
`
`i:":i
`i' -i
`
`I have reviewed. and understand. the conteirts of the above-idcntified. applioation for patont
`(hereinafter, "this application'), including the clairns ;
`
`I acknowledge the duty under Title 37, Code of Federal Regulations, Section 1.56, to disclose to the
`United States Patent and Trademark Office infonnation known to be material to the patentability of
`this applioation. I also acknowlodge th.at i"u,fomt.ahon is ruaterial to patentability when it is not
`cunulative to information already provided to the United Stares Paterrt and Tradcmark Officc and
`when it eithcr
`
`compels, by itselfor in combination with other information, a conelusion that a olaim
`is unpatentable wrder the preponder

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