Case IPR2020-01492
`U.S. Patent No. 6,651,134
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________________________________
`
`
`
`QUALCOMM INCORPORATED,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`__________________
`
`Case IPR2020-01492
`
`U.S. Patent No. 6,651,134
`__________________
`
`
`
`PATENT OWNER RESPONSE
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`
`TABLE OF CONTENTS
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`Page
`Introduction ...................................................................................................... 1
`I.
`II. Overview Of The ’134 Patent. ......................................................................... 2
`A.
`Technical Background ........................................................................... 3
`1.
`SRAM/DRAM ............................................................................ 3
`2.
`DRAM Activate Operations ....................................................... 4
`3.
`DRAM Precharge Operations ..................................................... 6
`B. Advantages Of The ’134 Patent. ......................................................... 11
`1.
`Advantages Over The Prior Art ................................................ 13
`III. Qualcomm’s Prior Art References Differ From The Teachings Of The
`’134 Patent. .................................................................................................... 14
`A.
`Schaefer Is Directed To Reducing The Amount Of Time
`Necessary To Complete DRAM Precharge And Activate
`Operations In Between Bursts ............................................................. 14
`1.
`Schaefer Recognizes That DRAM Precharge And
`Activate Operations Take A Given Amount Of Time To
`Complete, Resulting In Wasted Cycles In Between
`Bursts......................................................................................... 14
`Schaefer’s Purported Invention Allows ACTIVE and
`PRECHARGE Command Operations To Be Initiated
`One Cycle Early. ....................................................................... 19
`IV. Person Of Ordinary Skill In The Art. ............................................................ 21
`V.
`Claim Construction ........................................................................................ 22
`A. All Challenged Claims: “non-interruptible”. ...................................... 22
`B.
`Claim 16: “means for reading data ... / means for generating a
`predetermined number of said internal address signals in
`
`2.
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`U.S. Patent No. 6,651,134
`response to (i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals”. ....................................................... 22
`VI. Mr. Murphy’s Declaration Should Be Given Little Or No Weight .............. 23
`VII. Ground 1: Claims 11-5, 7, 9-10, 12-18, 20, And 21 Are Not
`Anticipated By Schaefer. ............................................................................... 29
`A.
`Schaefer Does Not Disclose “wherein said generation of said
`predetermined number of internal address signals is non-
`interruptible”. ...................................................................................... 29
`1.
`Schaefer Discloses Interrupting Bursts ..................................... 30
`
`Schaefer Discloses Multiple Means For
`Interrupting Bursts Before Completion .......................... 30
`Schaefer Does Not Describe Non-Interruptible
`Bursts Because It Is Directed To Preventing
`Wasted Cycles In Between Bursts .................................. 32
`Qualcomm’s Expert Agrees That Interrupting
`Bursts Is Advantageous And Prevents Wasting
`Cycles In Between Bursts ............................................... 34
`A POSITA Would Have Understood Schaefer’s
`Prohibition On User Commands To Apply Only To The
`Precharge Period TRP ................................................................. 36
`
`Schaefer Is Explicitly Directed To Reducing The
`Time Necessary To Activate and Precharge A Row
`By Initiating ACTIVE and PRECHARGE
`Command Operations Early ........................................... 38
`Initiating PRECHARGE Command Operations
`Early Requires Prohibiting Interruptions During
`The Time Period Necessary To Complete The
`Precharge Command Operation In Between Bursts ....... 40
`Schaefer’s AUTO-PRECHARGE Command
`Operation Necessitates Preventing Interruptions Of
`The Precharge Period tRP ................................................ 43
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`2.
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`U.S. Patent No. 6,651,134
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`Schaefer’s No Operation (NOP) Command Does
`Not Disclose Preventing User Commands
`Throughout The Burst Transfer Period .......................... 45
`VIII. Ground 1B: Claims 1-7, 9-10, and 12-21 Are Not Obvious Over
`Schaefer In Combination With Fujioka. ........................................................ 52
`IX. Ground 2A: Claim 11 Is Not Obvious Over Schaefer In Combination
`With Lysinger. ............................................................................................... 53
`X. Ground 2B: Claim 11 Is Not Obvious Over Schaefer In Combination
`With Lysinger And Fujioka. .......................................................................... 53
`XI. Conclusion ..................................................................................................... 54
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`Cont’l Can Co. v. Monsanto Co.,
`948 F.2d 1264 (Fed. Cir. 1991) .....................................................................29
`In re Fine,
`837 F.2d 1071 (Fed. Cir. 1988) .............................................................. 52, 53
`Microsoft Corp. v. Biscotti, Inc.,
`878 F.3d 1052 (Fed. Cir. 2017) .....................................................................29
`Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359 (Fed. Cir. 2008) .....................................................................29
`PAR Pharm., Inc. v. TWI Pharms., Inc.,
`773 F.3d 1186 (Fed. Cir. 2014) .....................................................................29
`UltraTec, Inc. v. CaptionCall, LLC,
`872 F.3d 1267 (Fed. Cir. 2017) .....................................................................28
`Unigene Labs., Inc. v. Apotex, Inc.,
`655 F.3d 1352 (Fed. Cir. 2011) .....................................................................52
`
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`All emphases are added unless otherwise indicated.
`
`This paper includes color illustrations and should be viewed in color.
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`U.S. Patent No. 6,651,134
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`PATENT OWNER’S EXHIBIT LIST
`
`Exhibit No.
`2001
`
`2002
`
`2003
`
`2004
`2005
`
`2006
`2007
`2008
`
`2009
`
`DESCRIPTION
`Monterey’s First Amended Complaint in Monterey Research, LLC v.
`Advanced Micro Devices, Inc., C.A. No. 19-cv-2149-CFC, Dkt. 16
`(D. Del. Feb. 5, 2020)
`Scheduling Order in Monterey Research, LLC v. Qualcomm Inc. et
`al, C.A. No. 19-2083-NIQA-LAS (D. Del. Oct. 1, 2020); Monterey
`Research, LLC v. Nanya Tech. Corp. et al, C.A. No. 19-2090-NIQA-
`LAS (D. Del. Oct. 1, 2020); Monterey Research, LLC v. Advanced
`Micro Devices, Inc., C.A. No. 19-cv-2149-NIQA-LAS (D. Del. Oct.
`1, 2020); Monterey Research, LLC v. STMicroelectronics N.V. et al,
`C.A. No. 20-0089-NIQA-LAS (D. Del. Oct. 1, 2020); Monterey
`Research, LLC v. Marvell Tech. Grp. Ltd., et al, C.A. No. 20-0158-
`NIQA-LAS (D. Del. Oct. 1, 2020)
`Qualcomm’s Answer, Counterclaims and Defenses to the First
`Amended Complaint in Monterey Research, LLC v. Qualcomm Inc.
`et al, C.A. No. 19-2083-NIQA-LAS, Dkt. 22 (D. Del. Feb. 28, 2020)
`December 29, 2020 Email fr. USPTO Trials
`Declaration In Support Of Patent Owner Monterey Research, LLC’s
`Unopposed Motion For Admission Pro Hac Vice Of Michael A.
`Wueste
`Declaration Of Michael C. Brogioli, Ph.D.
`Curriculum Vitae Of Michael C. Brogioli, Ph.D.
`Declaration of Robert Murphy In Support of Defendant GSI
`Technology, Inc.’s Responsive Claim Construction Brief in Cypress
`Semiconductor Corp. v. GSI Tech., Inc., Case Nos. 3:13-cv-02013,
`4:13-cv-03757 (N.D. Cal. May 20, 2014)
`May 18, 2021 Deposition Transcript of Robert Murphy
`
`All citations to specific pages of exhibits follow the pagination added to those
`exhibits per 37 C.F.R. § 42.63(d)(2)(i).
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`Introduction
`I.
`
`The Board should confirm the validity of the Challenged Claims.
`
`Qualcomm’s primary reference—U.S. Patent No. 5,600,605 (“Schaefer”)—alone or
`
`in combination does not cover U.S. Patent No. 6,651,134 (“the ’134 Patent”), which
`
`improves upon prior art memories operating in burst mode. Unlike prior art
`
`memories, the ’134 Patent proposes an integrated circuit comprising a memory and
`
`a logic circuit which fixes the length of the burst and renders it non-interruptible.
`
`But Schaefer does not disclose a memory that provides a non-interruptible
`
`burst. Indeed, Schaefer explicitly provides for multiple options for terminating and
`
`interrupting a burst before completion. Qualcomm does not deny this. Rather,
`
`Qualcomm alleges that a different, AUTO-PRECHARGE operation—which has
`
`nothing to do with a burst data transfer and by definition begins after a burst data
`
`transfer completes—purportedly discloses a non-interruptible burst. Specifically,
`
`Qualcomm misreads a portion of Schaefer, which discloses prohibiting user
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`commands only during the time necessary to perform and complete a precharge
`
`operation after completion of a burst transfer operation, and argues that the
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`prohibition on user commands applies to burst transfers as well. But based on the
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`intrinsic record, the knowledge of a person of ordinary skill in the art (POSITA) and
`
`Qualcomm’s expert’s—Mr. Robert Murphy—own admissions, Schaefer’s AUTO-
`
`PRECHARGE operation period—and the entire point of Schaefer’s invention—is
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`directed at reducing the amount of overhead time in between bursts, and not
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`preventing interruptions of a burst. As such, Schaefer does not disclose—nor would
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`a POSITA have understood Schaefer to disclose—a non-interruptible burst.
`
`II. Overview Of The ’134 Patent.
`The ’134 patent teaches a novel design and operation for memories, such as a
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`Static Random Access Memory (SRAM) or a Dynamic Random Access Memory
`
`(DRAM), operating in burst mode. In burst mode, a memory can provide data from
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`multiple locations within the memory using a single external address, thereby
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`increasing efficiency and reducing activity on address and control buses connected
`
`to the memory. (Ex-1001, 1:11-13; Brogioli Declaration (“Ex-2006”), ¶65.) Before
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`the ’134 Patent, burst mode in both conventional SRAMs and DRAMs had
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`drawbacks, particularly a susceptibility to interruptions. In a conventional SRAM,
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`burst mode could be “started and stopped in response to a control signal.” (Ex-1001,
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`1:15-18.) Using burst mode in a conventional DRAM was “difficult because of the
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`need to refresh” data within the memory cell (Ex-1001, 1:26-27), which might
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`necessitate interrupting the burst application and thus greatly lengthen the amount
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`of time required for accessing data. (Ex-1001, 1:27-36.) As such, the ’134 Patent
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`explains that it “would be desirable to have a memory device that has a fixed burst
`
`length.” (Ex-1001, 1:44-45.) To address these issues, the’134 Patent proposes an
`
`integrated circuit comprising a memory and a logic circuit which fixes the length of
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`U.S. Patent No. 6,651,134
`the burst and renders it non-interruptible. (Ex-1001, Abstract, 1:44-45; Ex-2006,
`
`¶65.)
`
`A. Technical Background
`SRAM/DRAM
`1.
`At the time of the ‘134 Patent, two common types of memory used in digital
`
`computer systems were Static Random Access Memory (commonly referred to as
`
`SRAM), and Dynamic Random Access Memory (commonly referred to as DRAM).
`
`Both SRAM and DRAM store digital data within a system, represented as binary
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`ones ‘1’ and zeros ‘0’, using what are referred to as cells within the memory to store
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`each bit of digital information. SRAM and DRAM have characteristic differences
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`that make each one suitable for various use cases and implementations such as local
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`on-chip scratch pad memories, versus larger off-chip storage. (Ex-2006, ¶50.)
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`SRAM uses transistors to implement each memory cell. Due to the fact that
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`SRAM uses only transistors to implement a given memory cell, it is considered
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`static. In other words, leakage current is not an issue within SRAM and for
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`maintaining the state of a given SRAM memory cell. However, this feature also
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`comes at a cost: SRAM takes up a larger amount of chip real estate versus
`
`technologies such as DRAM. As such, SRAM has a lower on-chip density of
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`memory cells per unit of area than alternate technologies, such as DRAM. (Ex-2006,
`
`¶51.)
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`In contrast to SRAM, DRAM is dynamic. For example, DRAM uses a
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`capacitor in addition to transistors to implement memory cells. The capacitor is used
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`to represent a digital one ‘1’ or zero ‘0’. However, capacitors leak charge over time.
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`As such, each capacitor and respective memory cell in a DRAM implementation
`
`must be periodically recharged so as to maintain the correct state. This requires
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`consistent reading, and subsequent writing, of information from and to a DRAM
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`memory cell and introduces the dynamic nature of DRAM. (Ex-2006, ¶52.)
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`DRAM Activate Operations
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`2.
`The charges, or voltage levels, used to represent a digital one ‘1’ or zero ‘0’
`
`in each DRAM capacitor are very small. In order to read those values—and thus
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`read the stored data—the charges in each capacitor are passed through bitlines to
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`sense amplifiers in the DRAM device to raise the voltages to a higher, readable level.
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`As such, the process of reading a DRAM capacitor—or cell—is destructive: after
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`passing the charge to the sense amplifier, the charge is gone from within the DRAM
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`capacitor and stored instead in the sense amplifiers (Ex-2006, ¶53):
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`“Q. The process of reading a DRAM cell is destructive because as
`
`soon as the charge within a given DRAM cell is read, that information
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`U.S. Patent No. 6,651,134
`or data value is gone from within that DRAM capacitor and is now
`
`stored in the sense amplifier connected to the bit line; correct?
`
`A Yes.”
`
`
`
`(Ex-2009, 48:25-49:8.)
`
`The procedure for moving the charges from the DRAM capacitors through the
`
`bitlines to the sense amplifiers in preparation for a read or write operation is initiated
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`by an active command (Ex-2006, ¶54):
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`“Q And then the active command, which also in parallel addresses a
`
`particular word line, is the command that begins the operation of
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`dumping the charge in the DRAM cells in a particular word line down
`
`through the bit lines into the sense amplifiers for storage; correct?
`
`A Yes.”
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`
`
`(Ex-2009, 58:3-11.)
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`Only after the active command operation has been completed can the read or
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`write operation begin (Ex-2006, ¶55):
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`“Q Once you have dumped the charge in the DRAM capacitors or
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`cells in a given word line into the sense amplifiers, you can then begin
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`your read or write operation; correct?
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`A Yes. You don't -- you cannot read anything from an array that has
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`not been through an activate command.
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`Q It's necessary to activate an array using the active command in an
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`SDRAM in order to perform a read or write operation?
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`A That's correct.”
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`
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`(Ex-2009, 58:23-59:11.)
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`For a given DRAM device, the activation procedure—without which a read
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`or write transfer operation cannot begin—takes a given amount of time (Ex-2006,
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`¶56):
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`“Q And then the active command, which also in parallel addresses a
`
`particular word line, is the command that begins the operation of
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`dumping the charge in the DRAM cells in a particular word line down
`
`through the bit lines into the sense amplifiers for storage; correct?
`
`A Yes.
`
`Q That operation takes a given amount of time to complete as well;
`
`correct?
`
`A Yes. I mean, just to say it here, all of the operations are limited by
`
`physics. They all take a certain amount of time, yes.”
`
`(Ex-2009, 58:3-22.)
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`DRAM Precharge Operations
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`3.
`Because the process of reading data from a DRAM capacitor or memory cell
`
`is destructive, after the data has been moved from the DRAM capacitor to the sense
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`amplifiers, the data must be restored—or “written back”—to the DRAM capacitor.
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`Additionally, the voltage levels of the DRAM capacitor must be precharged—or
`
`“normalized”—after accessing data stored within the DRAM capacitor in order for
`
`the sense amplifiers to accurately read the voltage levels (Ex-2006, ¶57):
`
`Q. Is a precharge operation in a DRAM device necessary to
`
`normalize voltage on the bit line after performing a read operation?
`
`A That's one of the things, yes.
`
`Q Similarly, a precharge operation in a DRAM device would be
`
`necessary to normalize the voltage on a bit line after a write
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`operation?
`
`A That's correct.
`
`
`
`(Ex-2009, 53:21-54:6.)
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`Therefore, in order to perform two read operations in different rows of the
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`DRAM, both a writeback and a precharge operation must be performed in between
`
`the two read operations (Ex-2006, ¶58):
`
`“Q So as I understand it, let's take a read operation in which we know
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`that we're going to be moving to another row in the next read
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`operation. Do you have that in mind?
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`A Yes.
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`Q And in that scenario in which we have a read operation of data
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`stored within an SDRAM, we are going to -- and we know we're
`
`going to move to another row, we need to perform a precharge
`
`operation; correct?
`
`A At least the precharge. You also have to do a write back, which is
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`an internal operation that happens before the precharge.”
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`(Ex-2009, 64:16-65:7.)
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`Due in part to the destructive nature of DRAM read and write operations,
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`DRAM precharge operations must be carefully timed to avoid interruptions and
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`thereby ensure data integrity in the memory device. Particularly, sufficient time
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`must be allotted to both execute the PRECHARGE command and complete the
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`PRECHARGE operation. Due to the inherent characteristics of very large scale
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`integration (VLSI) circuits, including DRAM devices and other memory chips, there
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`is typically a delay between fully executing a command to the device and performing
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`the resulting operation. As such, timing requirements for completing essential
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`operations—such as PRECHARGE operations in DRAM devices—must account
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`for not only the time necessary to complete the PRECHARGE operation itself, but
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`also the time delay between executing the PRECHARGE command and initiating
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`the PRECHARGE operation. (Ex-2006, ¶59.)
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`For example, a PRECHARGE command operation in a DRAM module may
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`require, among other things, that (1) the memory controller correctly handles and
`
`issues signaling information necessary for executing the PRECHARGE command;
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`(2) the necessary transistors in a given DRAM module switch and initiate the
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`PRECHARGE operation; (3) the DRAM module charges the relevant capacitors in
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`memory cells; and (4) the DRAM module closes the open row. These actions take
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`a given amount of time to complete. When a PRECHARGE command is executed
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`too quickly, the DRAM device may not have sufficient time to complete the
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`PRECHARGE operation, resulting in data corruption within the DRAM cells and
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`often overall system instability and other undesirable results (Ex-2006, ¶60):
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`“Q So in a DRAM device that requires a precharge, interrupting the
`
`precharge before the given amount of time necessary to complete the
`
`precharge operation has elapsed would leave the voltage on the bit
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`lines in an indeterminate state; is that fair?
`
`A That’s correct.
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`Q In that scenario, you would not be able to perform an active
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`command operation to begin a subsequent read command, for
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`example; correct?
`
`A I would change that sentence a little bit. You certainly can perform
`
`an activate, but I’m pretty sure that the data that you read would not
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`be valuable at all. There would be some errors in it somewhere and
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`you wouldn’t know where, so you would have corrupted the data
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`that was on that particular word line.”
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`(Ex-2009, 74:19-75:16.)
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`For example, Schaefer states that, in operation, an “internally generated row
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`address strobe remains active and the selected row is open until a PRECHARGE
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`command deactivates and precharges the selected row of the memory array.” (Ex-
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`1017, 1:37-41 (emphasis added). If the PRECHARGE operation described in
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`Schaefer, for example, is not completed, the contents of the open, selected row of
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`memory may become corrupted or placed in an unknown state when deactivating a
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`given row. (Ex-2006, ¶61.)
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`As such, an appropriate amount of time between the command and the
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`requested operation is necessary to ensure that both the command and the operation
`
`is completed. The appropriate amount of time for a given memory command,
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`including PRECHARGE commands, may vary based upon the speed of the system,
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`including increasing CPU read and write speeds, as well as increasing clock rates
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`for DRAM technologies. The memory controller in the system must account for
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`such differences in system speeds and frequencies. (Ex-2006, ¶62.)
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`B. Advantages Of The ’134 Patent.
`The benefits and advantages of the ’134 Patent include, inter alia, the ability
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`to set a fixed burst length to suit application needs, have non-interruptible bursts,
`
`hide required DRAM refreshes inside a known fixed burst length of data words, and
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`operate at higher frequencies without needing interrupts to refresh data. (Ex-1001,
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`1:58-67; Ex-2006, ¶77.)
`
`The disclosed memories of the ’134 Patent “may be configured to transfer a
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`fixed number of words to or from the memory 104 in response to” internal and
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`external signals. (Ex-1001, 3:6-8.) For example, in one embodiment shown in
`
`Figure 2, reproduced below, the address counter register 126 of circuit 102 receives
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`the signals ADDR_EXT, LOAD, and CLK, while the burst counter 128 receives the
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`signals ADV and BURST. (Ex-1001, 3:65 – 4:2.) The burst counter 128 presents a
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`signal BURST_CLK—which contains “a number of pulses that has been
`
`programmed by the signal BURST”—to the address counter 126 when the signal
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`ADV is asserted. (Ex-1001, 4:10-14.) An initial address may be loaded into the
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`address counter register 126 by presenting the initial address in the external address
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`signal ADDR_EXT and asserting the signal LOAD. (Ex-1001, 4:6-8.) The initial
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`address identifies the starting point for accessing the memory array. The address
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`counter register 126 then “increment[s] an address in response to the signal
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`BURST_CLK,” for a number of times that equals the number of pulses in the signal
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`BURST_CLK as programmed by the burst counter 128 in response to the signal
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`BURST. (Ex-1001, 4:8-10.) As such, the predetermined number of internal
`
`addresses is generated by incrementing the initial address based on the number of
`
`pulses from the signal BURST_CLK. (Ex-2006, ¶¶72-73.)
`
`(Ex-1001, Figure 2.)
`
`
`
`
`
`The ’134 Patent teaches that the burst can be non-interruptible by preventing
`
`the burst counter 128 from stopping the generation of internal addresses until the
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`fixed number is reached:
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`• “When the signal ADV is asserted, the circuit 100 will generally
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`begin transferring a predetermined number of words. The
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`transfer is generally non-interruptible.” (Ex-1001, 3:6-13.)
`
`• “Once the circuit 102 has started generating the fixed number
`
`of addresses, the circuit 102 will generally not stop until the
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`fixed number of addresses has been generated (e.g., a non-
`
`interruptible
`
`burst).”
`
` (Ex-1001, 3:25-28; Ex-2006, ¶¶75.)
`
`Advantages Over The Prior Art
`
`1.
`The non-interruptible generation of internal address signals presents an
`
`advantage over prior art solutions that merely read or write a preset number of data
`
`words or present options for continuously reading data from or writing data to the
`
`memory. For example, the Patent and Trademark Office (“PTO”) allowed the ’134
`
`Patent over prior art such as US Patent No. 6,289,138 to Yip et al. (Ex-2002, “Yip”.)
`
`Yip disclosed restricting rearbitration for a DRAM device so that an interruptible
`
`burst transfers a preset number of data words. (Ex-1004, 0065.) But an interruptible
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`burst “is not the same as generating a predetermined number of internal address
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`signals that is non-interruptible.” (Ex-1004, 0065; Ex-2006, ¶78.)
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`Similarly, the ’134 Patent was allowed, and provides advantages, over prior
`
`art that merely presented methods for continuously bursting data in and/or out of the
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`memory. For example, the PTO allowed the ’134 Patent over U.S. Patent No.
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`5,729,504 to Cowles (Ex-2001 “Cowles”), which was directed to “an ability to
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`access a second row of memory while bursting data out of a first row (a so-called
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`‘continuous BEDO,’ or ‘CBEDO’ architecture ...).” (Ex-1004, ¶¶0107-0108.) But
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`the “ability to access a second row of memory while bursting data out of a first row
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`has little or nothing to do with whether a “burst” can be interrupted.” (Ex-1004,
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`0107-0108; Ex-2006, ¶79.)
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`III. Qualcomm’s Prior Art References Differ From The Teachings Of The
`’134 Patent.
`
`A.
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`Schaefer Is Directed To Reducing The Amount Of Time Necessary
`To Complete DRAM Precharge And Activate Operations In
`Between Bursts
`
`1.
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`Schaefer Recognizes That DRAM Precharge And Activate
`Operations Take A Given Amount Of Time To Complete,
`Resulting In Wasted Cycles In Between Bursts
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`U.S. Patent No. 5,600,605 to Schaefer (“Schaefer”) is directed to a
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`semiconductor memory integrated circuit—and particularly a synchronous dynamic
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`random access memory (SDRAM)—which reduces the amount of time necessary to
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`activate and precharge a row of storage cells in an SDRAM memory bank in between
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`burst operations. (See, e.g., Ex-1017, [54] Title: “Auto-Activate on Synchronous
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`Dynamic Random Access Memory.”) According to Schaefer, a typical SDRAM
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`“requires separate commands for accessing and precharging a row of storage cells
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`in the SDRAM memory array.” (Ex-1017, 1:33-35.) As such, according to Schaefer
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`(Ex-2006, ¶80):
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`In a SDRAM, a transfer operation involves [1] performing a
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`PRECHARGE command operation to deactivate and precharge a
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`previously accessed bank memory array, [2] performing an ACTIVE
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`command operation to register the row address and activate the bank
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`memory array to be accessed in the transfer operation, and [3]
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`performing the transfer READ or WRITE command to register the
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`column address and initiate a burst cycle.
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`(Ex-1017: 1:43-49.)
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`The ACTIVE command activates and addresses a row in a selected bank
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`memory array before beginning a burst READ or WRITE cycle. (See, e.g., Ex-1017,
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`4:14-36; Ex-1015, ¶28.) The ACTIVE command operation must be completed
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`before beginning a burst READ or WRITE cycle. (E.g., Ex-1015, ¶74 (“After the
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`row has been activated, a READ or WRITE with AUTO-PRECHARGE can be
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`initiated”), id., 28, 73; (Ex-2006, ¶81.) Mr. Murphy agrees:
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`“Q Before you can issue an external read command, you have to
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`complete the active operation depicted in Figure 4 as comprising the
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`period TRCD from T0 through T2; correct?
`
`A That's correct, assuming you want the read to be successful.
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`Q If you were to try to initiate the read operation before the amount of
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`TRCD have been completed, your read operation would be
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`unsuccessful?
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`A I assume that's true in one of two ways, either the device itself
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`would lock you out from doing that or the device would just give you
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`data that was nonsensical.
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`
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`(Ex-2009, 105:16-106:7.)
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`The PRECHARGE command operation “deactivates and precharges the bank
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`memory array selected by the state of the BA signal,” such that “the row previously
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`accessed is deactivated and precharged so that row may be refreshed or another row
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`accessed.” (Ex-1017, 6:23-28.) The PRECHARGE command operation must be
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`completed before beginning a burst READ or WRITE cycle addressed to a different
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`row: “a bank memory array must be precharged prior to registering a new row
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`address.” (Ex-1017, 7:1-3; Ex-2006, ¶82.)
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`Further, each of the PRECHARGE and ACTIVE command operations take a
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`given amount of time to complete. For example, Schaefer’s Figure 2, reproduced
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`below, depicts a “timing diagram illustrating a four cycle read burst transfer
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`operation.” (Ex-1017, 2:46-47.) In such a four cycle burst transfer operation, the
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`“time from the initiation of an ACTIVE command to the initiation of a READ
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`command is represent[ed] by tRCD and represents two clock cycles.” (Ex-1017, 8:13-
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`16; see also Ex-2009, 103:19-22 (“Q Okay. So TRCD is the time necessary to
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`perform and complete the active operation; correct? A That's correct.”).) Similarly,
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`the “PRECHARGE command period (tRP) is three system clock cycles.” (Ex-1017,
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`8:26-27; see also Ex-2009, 98:10-15 (“Q So the time TRP refers to the time
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`necessary to perform and complete a precharge operation initiated by a precharge
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`command or an auto-precharge command; correct? A Correct.”); Ex-2006, ¶83.)
`
`(Ex-1017, Fig. 2.)
`
`
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`Therefore, because the PRECHARGE and ACTIVE command operations (1)
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`must be completed before beginning a READ or WRITE burst operation, and (2)
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`require a given number of cycles to complete, “[a]t many frequencies, the time to
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`perform the PRECHARGE command operation, and the ACTIVE command
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`operation results in wasted time which adds up to an extra clock cycle resulting in
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`a wait cycle.” (Ex-1017, 1:49-52.) Specifically, at some frequencies, “the total time
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`required for tRP and tRCD equals an extra clock cycle or system clock cycle time (tCK)
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`than if the two (tRP and tRCD) were able to be accomplished as a single parameter
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`thereby resulting in a wait cycle.” (Ex-1017, 9:11-15.) For example, in “either a
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`READ command or WRITE command with either a PRECHARGE command or an
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`AUTO-PRECHARGE command following the READ or WRITE command, the
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`above-described problem of too much total time between the addition of tRP and tRCD
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`may result an additional wait cycle.” (Ex-1017, 9:16-21.) As such, according to
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`Schaefer, “there is a need to eliminate possible wasted clock cycles between random
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`READS and writes in a SDRAM.” (Ex-1017, 1:53-54; Ex-2006, ¶84.) Mr. Murphy
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`agrees:
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`“Q Schaefer is directed to eliminating the potential wasted clock
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`cycles necessary to perform the precharge command operations and
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`the active command operations; correct?
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`A Yes, given the fact that the frequencies of operation can be
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`different.”
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`
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`(Ex-2009, 110:19-111:1.)
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`Case IPR2020-01492
`U.S. Patent No. 6,651,134
`Schaefer’s Purported Invention Allows ACTIVE and
`2.
`PRECHARGE Command Operations To Be Initiated One
`Cycle Early.
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`To address the need to eliminate wasted clock cycles between reads and writes
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`in an SDRAM due to the time necessary to perform the PRECHARGE (or AUTO-
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`PRECHARGE) and ACTIVE command operations, Schaefer “allow[s] the ACTIVE
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`command to be initiated one cycle early such as at time t9.” (Ex-1017, 9:47-49.)
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`Specifically, Schaefer proposes a synchronous memory device including a
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`“command decoder/controller responsive to selected command signals to initiate”
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`(1) “a first command controlling a first operation on the memory array” and (2) “a
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`second command controlling a second operation on the memory array.” (Ex-1017