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`E A S T P A L O A L T O
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`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 1 of 8
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`MARK FOWLER (Bar No. 124235)
`mark.fowler@dlapiper.com
`GERALD T. SEKIMURA (Bar No. 096165)
`gerald.sekimura@dlapiper.com
`ANDREW P. VALENTINE (Bar No. 162094)
`andrew.valentine@dlapiper.com
`ALAN LIMBACH (Bar No. 173059)
`alan.limbach@dlapiper.com
`TIMOTHY LOHSE (Bar No. 177230)
`timothy.lohse@dlapiper.com
`MICHAEL G. SCHWARTZ (Bar No. 197010)
`michael.schwartz@dlapiper.com
`BRENT YAMASHITA (Bar No. 206890)
`brent.yamashita@dlapiper.com
`SAORI KAJI (Bar No. 260392)
`saori.kaji@dlapiper.com
`DLA PIPER LLP (US)
`2000 University Avenue
`East Palo Alto, CA 94303-2214
`Tel: 650.833.2000
`Fax: 650.833.2001
`
`Attorneys for Defendant
`GSI TECHNOLOGY, INC.
`
`
`UNITED STATES DISTRICT COURT
`
`NORTHERN DISTRICT OF CALIFORNIA
`
`SAN FRANCISCO DIVISION
`
`CYPRESS SEMICONDUCTOR
`CORPORATION,
`
`Plaintiff,
`
`
`
`v.
`
`GSI TECHNOLOGY, INC.,
`
`Defendant.
`
`CASE NOS. 3:13-cv-02013-JST (JCS)
` 4:13-cv-03757-JST (JCS)
`
`DECLARATION OF ROBERT MURPHY IN
`SUPPORT OF DEFENDANT GSI
`TECHNOLOGY, INC.’S RESPONSIVE
`CLAIM CONSTRUCTION BRIEF
`
`DATE: May 20, 2014
`TIME: 2:00 P.M.
`PLACE: Courtroom 9, 19th floor
`JUDGE: Hon. Jon S. Tigar
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`
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`
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`WEST\247431062.1
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`CASE NOS. 13-CV-02013-JST (JCS), 13-CV-03757-JST (JCS)/MURPHY
`DECLARATION IN SUPPORT OF GSI’S RESPONSIVE CLAIM CONSTRUCTION
`BRIEF
`
`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0001
`
`

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`DLA PI PER LLP (US)
`E A S T P A L O A L T O
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`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 2 of 8
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`
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`I, Robert Murphy, do hereby declare:
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`1.
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`I am making this declaration at the request of GSI Technology Inc. in support of
`
`its responsive claim construction brief. I am being compensated for my work in this matter at the
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`rate of $450 per hour. My compensation in no way depends upon the outcome of this proceeding.
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`2.
`
`In preparing this declaration and forming the opinions expressed below, I have
`
`considered:
`
`a.
`
`b.
`
`c.
`
`d.
`
`e.
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`f.
`
`g.
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`h.
`
`i.
`
`U.S. Patent No. 6,651,134 (the “’134 patent”);
`
`The file history of the ’134 patent;
`
`U.S. Patent No. 6,069,839 (the “’839 patent”);
`
`The file history of the ’839 patent;
`
`U.S. Patent No. 6,292,403 (the “’403 patent”);
`
`The file history of the ’403 patent;
`
`The various pieces of evidence listed in the Joint Claim Construction and
`
`Prehearing Statement under Patent Local Rule 4-3 and the exhibits thereto dated
`
`January 27, 2014;
`
`Plaintiff Cypress’s Opening Claim Construction Brief dated February 26, 2014
`
`and the exhibits thereto;
`
`My knowledge and experience based upon my work in this area as described
`
`below.
`
`I.
`
`Qualifications and Professional Experience
`
`3.
`
`As indicated in my Curriculum Vitae, attached as Exhibit A, I received a B.S. in
`
`Electrical Engineering from Drexel University in 1974, and a M.S. in Electrical Engineering from
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`University of California, Los Angeles (UCLA) in 1976.
`
`4.
`
`While at Hughes Aircraft Co. from 1974-1978, in addition to other circuit designs,
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`I designed charged coupled device (CCD) based memories that included control circuitry,
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`addressing scheme and circuitry, data input and data output paths. The CCD based memories used
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`a CCD device as a memory cell to store data in a different manner than is done with a DRAM
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`WEST\247431062.1
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` CASE NOS. 13-CV-02013-JST (JCS), 13-CV-03757-JST (JCS)/ MURPHY
`DECLARATION ISO GSI’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0002
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`E A S T P A L O A L T O
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`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 3 of 8
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`
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`memory. In memories that use either a CCD memory cell or a single transistor based memory cell
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`such as is used in a DRAM memory, the memories must be addressed to either read or write data
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`into the memory, must have the other usual control circuitry and must have read data paths and
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`write data paths to get the data into or out from the memory. As a result, the control circuitry,
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`addressing scheme and circuitry, data input and data output paths for the CCD based memories
`
`are very similar to the control circuitry, addressing scheme and circuitry, data input and data
`
`output paths used in other semiconductor memories.
`
`5.
`
`In 1978, I was hired at National Semiconductor Corp. to design a pseudostatic
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`dynamic random access memory (DRAM). As part of the design of the pseudostatic DRAM, I
`
`designed the sense amplifiers for the device. The pseudo-static DRAM used CCD devices for the
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`memory cells, but used the same manufacturing processes and circuitry as typical DRAM.
`
`6.
`
`About a year after my hire at National Semiconductor Corp., I transferred over to
`
`the static random access memory (SRAM) group and then learned about various SRAM
`
`operations including addressing, data outputting and controlling of the SRAM. As part of the
`
`work, I designed a four transistor (4T) cell 4K SRAM product. After the 4T cell 4K SRAM
`
`product was built, I was promoted to SRAM design manager. As the SRAM design manager, I
`
`was responsible for all SRAM designs. As part of my role as SRAM design manager, I resolved
`
`an SRAM yield crash in 62 days. I was responsible for the SRAM designs in production in the
`
`amount of 30,000 4 inch wafers per month.
`
`7.
`
`From 1982 to 1983, I was a program manager at RCA and led the development of
`
`a 64K SRAM including the design, layout, process development and manufacturing of the SRAM
`
`part. As part of that development of the 64K SRAM, the team that I led also created a 4K SRAM
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`test chip.
`
`8.
`
`At Silicon Graphics, I was in charge of all circuit designers including cache
`
`designers for a major microprocessor. I was also responsible for the circuit design of a floating
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`point processor for a microprocessor system.
`
`9.
`
`In 1998, I founded a company, Firenza, LLC., that develops and licenses high
`
`performance building blocks for semi-custom and ASIC designs. A part of those designs that I
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`WEST\247431062.1
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`DECLARATION ISO GSI’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
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`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0003
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`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 4 of 8
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`
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`have built are memory blocks. For example, I was hired to build memory blocks for a DVD
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`controller chip that included a MIPs processor core. The memories included i-cache, d-cache; i-
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`tag, d-tag and 22 dual port register files.
`
`II. Overview of the ’134 Patent
`
`10.
`
`The ’134 patent is generally directed to a computer memory that is used for
`
`volatile storage of data. The ’134 patent more specifically relates to burst read and write
`
`operations (“burst operations”) using a circuit, such as a volatile memory. ’134 patent at Title and
`
`col. 2, lines 25-38. In burst operations, two or more pieces of data are read from the volatile
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`memory or written to the volatile memory. The ’134 patent relates to burst operations in which
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`the generation of internal address signals is non-interruptible. ’134 patent at col. 3: 5-29 and col.
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`4: 15-48. A fixed length non-interruptible burst generally frees up the address bus and control bus
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`for a known number of cycles. ’134 patent at col. 3: 56-58.
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`11.
`
`The specification of the ’134 patent describes the circuits used within the volatile
`
`memory.
`
`
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`12.
`
`As shown in Figure 1 of the ’134 patent reproduced above, the circuit 100 has a
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`logic circuit 102 that generates multiple internal address signals (ADDR_INT) that are fed into a
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`WEST\247431062.1
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` CASE NOS. 13-CV-02013-JST (JCS), 13-CV-03757-JST (JCS)/ MURPHY
`DECLARATION ISO GSI’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0004
`
`

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`E A S T P A L O A L T O
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`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 5 of 8
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`
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`memory 104 to write/read burst data to/from the memory 104. The logic circuit uses a number of
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`signals in order to generate the multiple internal address signals, such as an external address
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`signal (ADDR_EXT) that is generated external to the circuit 100 as shown in Figure 1, a clock
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`signal (CLK) that is generated external to the circuit 100 and one or more control signals (LOAD,
`
`ADV and BURST).
`
`13.
`
`The logic circuit may be a burst address counter/register as shown in Figure 1. The
`
`other embodiments of the logic circuit shown have an address counter register and a burst counter
`
`(Figure 2) or a latch, counter and multiplexer (Figure 3).
`
`14.
`
`To perform the addressing for the burst operation, the external address is a starting
`
`address of the burst. ’134 patent at col. 4: 4-14. The logic circuit then generates a fixed number of
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`internal addresses based on the starting address.
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`II.
`
`Claim Construction
`
`15.
`
`It is my understanding that in order to properly evaluate a patent, the terms of the
`
`claims must first be interpreted. It is also my understanding that the claims should be construed
`
`in light of their ordinary and customary meaning, which is the meaning that the term would have
`
`to a person of ordinary skill in the art in question at the time of the invention. It is my further
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`understanding that claim terms are given their ordinary and accustomed meaning as would be
`
`understood by one of ordinary skill in the art, unless the inventor, as a lexicographer, has set forth
`
`a special meaning for a term.
`
`16.
`
`In order to construe the claims, I have reviewed the entirety of the ’134, ’839 and
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`’403 patents, as well as their prosecution histories.
`
`A.
`
`17.
`
`Level of Ordinary Skill in the Art
`
`In my opinion, a person of ordinary skill in the art as of the time of the ’134 patent
`
`would have had a BS in Electrical Engineering and 5 years of experience with direct SRAM
`
`design experience.
`
`18.
`
`In my opinion, a person of ordinary skill in the art as of the time of the ’403 and
`
`’839 patents would have needed to have the capability of understanding the scientific and
`
`engineering principles applicable to the ’839 patent and ’403 patent, which would have required a
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`-4-
`WEST\247431062 1
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`DECLARATION ISO GSI’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
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`
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`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0005
`
`

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`E A S T P A L O A L T O
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`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 6 of 8
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`Bachelors of Science degree in electrical engineering and at least two years working in the field
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`of semiconductor design.
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`B.
`
`19.
`
`’134 Patent - Memory
`
`I understand that GSI proposes to construe the term “memory” of the ’134 patent
`
`to mean “addressable storage.” In my opinion, based on the specification and claim language,
`
`one of ordinary skill in the art at the time the ’134 patent was filed would have understood the
`
`term “memory” of the ’134 patent to mean “addressable storage.”
`
`20.
`
`One of ordinary skill in the art would understand that the claim language of the
`
`’134 patent supports and is consistent with GSI’s proposed construction. Claim 1 of the ’134
`
`patent recites “a memory comprising a plurality of storage elements each configured to read and
`
`write data in response to an internal address signal.” First, I understand that this claim language
`
`requires that the memory has many storage elements and is storage. Second, I understand from
`
`this claim language that each of the storage elements, such as a memory cell in the memory array,
`
`has to be able to read and write data in response to an address, such as an internal address signal.
`
`This means that each of the storage elements can be addressed by the address and each of the
`
`storage elements is therefore addressable. This further means that the memory is also addressable
`
`since each of the storage elements is addressable. I thus understand that this portion of claim 1
`
`means that the memory is addressable storage.
`
`21.
`
`Claim 17 of the ’134 patent recites “accessing the memory in response to a
`
`plurality of address signals.” I understand that this claim language requires that the memory is
`
`accessed so that data can be read from or written to the memory. Furthermore, I understand from
`
`this claim language that the memory is accessed in response address signals. This means that the
`
`memory can be addressed by the address signals and that the memory is therefore addressable. I
`
`thus understand that this portion of claim 17 also means that the memory is addressable storage.
`
`22.
`
`In the ’134 patent, as shown in Figure 1 above, a memory 104 receives internal
`
`address signals (ADDR_INT) shown in Figure 1 from the logic circuit. One of ordinary skill in
`
`the art at the time of the ’134 patent understood that the memory 104 has a number of memory
`
`cells within a memory array and that each memory cell is a storage element. Each such memory
`
`-5-
`WEST\247431062.1
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`DECLARATION ISO GSI’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
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`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0006
`
`

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`E A S T P A L O A L T O
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`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 7 of 8
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`cell is separately addressable using an address, such as the internal address signals. To address
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`each memory cell, a word line and a pair of bit lines are selected that allow data to be read from
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`the memory cell or written to the memory cell. The word line and a pair of bit lines for a
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`particular memory cell are selected based on the address, such as the internal address signals. As
`
`shown in Figure 1, the memory 104 uses the internal address signals to select a particular memory
`
`cell and the memory 104. The memory described in the specification is thus addressable storage.
`
`23.
`
`I understand that Cypress has proposed to construe “memory” as “circuit elements
`
`used to store data.” I disagree with this proposed construction. If Cypress’s proposed
`
`construction were adopted, it would be inconsistent with the claim language that I discussed
`
`above. In addition, Cypress’s proposed construction would read on circuit elements that store
`
`data, but cannot meet the claim requirement that each of the circuit elements is configured to read
`
`and write data in response to an internal address signal. For example, a latch is a circuit element
`
`that is used to store data, but does not read and write data in response to an address signal.
`
`Furthermore, a register also is a circuit element that is used to store data, but does not read and
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`write data in response to an address signal. Thus, it is my opinion that Cypress’s proposed
`
`construction is too broad and would read on circuit elements that are not covered by the claims.
`
`C.
`
`24.
`
`’134 Patent – Address Signal
`
`I understand that GSI proposes to construe the term “address signal” of the ’134
`
`patent to mean “a signal for determining the address location in the memory array from which
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`data is read or to which data is written.” In my opinion, based on the specification and claim
`
`language, one of ordinary skill in the art at the time the ’134 patent was filed would have
`
`understood the term “address signal” of the ’134 patent to mean “a signal for determining the
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`address location in the memory array from which data is read or to which data is written.”
`
`25.
`
`Claim 1 recites “a memory comprising a plurality of storage elements each
`
`configured to read and write data in response to an internal address signal.” I understand that this
`
`claim language requires that data is read and written into a memory in response to an address
`
`signal as is set forth in GSI’s proposed construction. Furthermore, the specification uses the
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`terms “memory” and “memory array” interchangeably. ’134 patent at 2:30-38; 3:2-4. The
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`-6-
`WEST\247431062.1
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`
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`
`
`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0007
`
`

`

`Case 3:13-cv-02013-JST Document 74-1 Filed 03/26/14 Page 8 of 8
`
`Monterey Exhibit 2008
`Qualcomm, Inc. v. Monterey Research LLC
`Case IPR2020-01492, 0008
`
`