Trials@uspto.gov
`571-272-7822
`
`
`Paper No. 9
`Date: March 8, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`QUALCOMM INC.,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2020-01492
`Patent 6,651,134 B1
`
`
`
`
`
`
`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`MELVIN, Administrative Patent Judge.
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`571-272-7822
`
`
`Paper No. 9
`Date: March 8, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`QUALCOMM INC.,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2020-01492
`Patent 6,651,134 B1
`
`
`
`
`
`
`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`MELVIN, Administrative Patent Judge.
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`IPR2020-01492
`Patent 6,651,134 B1
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`
`INTRODUCTION
`I.
`Qualcomm Inc., (“Petitioner”) filed a Petition (Paper 1, “Pet.”)
`requesting institution of inter partes review of claims 1–7 and 9–21 (“the
`challenged claims”) of U.S. Patent No. 6,651,134 B1 (Ex. 1001,
`“the ’134 patent”). Pet. 6. Monterey Research, LLC, (“Patent Owner”) filed
`a Preliminary Response. Paper 6 (“Prelim. Resp.”). After our email
`authorization, Petitioner filed a Preliminary Reply (Paper 7) and Patent
`Owner filed a Preliminary Sur-Reply (Paper 8). Pursuant to 35 U.S.C. § 314
`and 37 C.F.R. § 42.4(a), we have authority to determine whether to institute
`review.
`An inter partes review may not be instituted unless “the information
`presented in the petition . . . and any response . . . shows that there is a
`reasonable likelihood that the petitioner would prevail with respect to at
`least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a). For the
`reasons set forth below, we conclude that Petitioner has shown a reasonable
`likelihood it will prevail in establishing the unpatentability of at least one
`challenged claim, and we therefore institute inter partes review.
`
`A. REAL PARTIES IN INTEREST
`Petitioner identifies itself, Qualcomm Technologies, Inc., and
`Qualcomm CDMA Technologies Asia-Pacific Pte Ltd. as real parties in
`interest. Pet. 2. Patent Owner identifies itself and IPValue Management as
`real parties in interest. Paper 3, 1.
`
`B. RELATED MATTERS
`As required by regulation, the parties identify matters related to the
`’134 patent. Pet. 2–3; Paper 3, 1–2. Of note is Advanced Micro Devices, Inc.
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`v. Monterey Research, LLC, IPR2020-00985, in which AMD challenges all
`claims of the ’134 patent. We instituted review in that proceeding on
`December 2, 2020. IPR2020-00985, Paper 13. Additionally, the district-
`court case involving Qualcomm is identified as Monterey Research, LLC v.
`Qualcomm Inc. et al., No. 1:19-cv-02083 (D. Del. 2019), whereas the case
`involving AMD is identified as Monterey Research, LLC v. Advanced Micro
`Devices Inc., No. 1:19-cv-02149 (D. Del. 2019). Paper 3, 1; Pet. 3.
`
`C. THE ’134 PATENT
` The ’134 patent is titled Memory Device with Fixed Length Non
`Interruptible Burst. Ex. 1001, code (54). The patent discloses that “the data
`burst transfers of conventional memories can be interrupted and single
`access made,” and proposes a memory device “that has a fixed burst length.”
`Id. at 1:37–45.
`Figure 1 is reproduced below:
`
`Ex. 1001, Fig. 1. Figure 1 depicts circuit 100 configured as a fixed burst
`memory, in which circuit 102 accepts external signals including external
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`address signal ADDR_EXT, and “generate[s] the signal ADDR_INT as a
`fixed number of addresses in response to the signal CLK.” Id. at 3:21–22.
`The ’134 patent states that “[o]nce the circuit 102 has started generating the
`fixed number of addresses, the circuit 102 will generally not stop until the
`fixed number of addresses has been generated (e.g., a non-interruptible
`burst).” Id. at 3:25–28.
`The ’134 patent depicts two embodiments for circuit 102, in Figures 2
`and 3. Figure 2 is reproduced below:
`
`
`
`Id. Fig. 2. Figure 2 shows burst counter 128 receiving signal CLK (a clock
`signal), signal ADV, and signal BURST, and providing signal
`BURST_CLK. “When the signal ADV is asserted, the burst counter 128 will
`generally present the signal BURST_CLK in response to the signal CLK.
`The signal BURST_CLK generally contains a number of pulses that has
`been programmed by the signal BURST.” Id. at 4:10–14. Figure 3 and the
`associated description disclose an alternative circuit, in which “counter 138
`may be configured to generate a number of addresses in response to the
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`signals CLK, BURST[,] and ADV” and where “[t]he number of addresses
`generated by the counter 138 may be programmed by the signal BURST.”
`Id. at 4:29–34. The ’134 patent describes more generally that, “[w]hen the
`signal ADV is asserted, the circuit 100 will generally generate a number of
`address signals” and that “[t]he address signals will generally continue to be
`generated until the Nth address signal is generated.” Id. at 4:42–48.
`
`D. CHALLENGED CLAIMS
`Challenged claim 1 is reproduced below:
`1. A circuit comprising:
`a memory comprising a plurality of storage elements each
`configured to read and write data in response to an
`internal address signal; and
`a logic circuit configured to generate a predetermined
`number of said internal address signals in response to
`(i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals, wherein said generation
`of said predetermined number of internal address signals
`is non-interruptible.
`Ex. 1001, 5:22–32. Independent claim 16 recites limitations similar to those
`of claim 1, expressed as means-plus-function elements. Id. at 6:20–30.
`Independent claim 17 recites limitations similar to those of claim 1,
`expressed as a “method of providing a fixed burst length data transfer.” Id.
`at 6:31–39. Claims 2–7 and 9–15 depend, directly or indirectly, from
`claim 1. Id. at 5:33–6:19. Claims 18–21 depend, directly or indirectly, from
`claim 17. Id. at 6:40–48.
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`E. PRIOR ART AND ASSERTED GROUNDS
`Petitioner asserts the following grounds of unpatentability:
`Claim(s) Challenged
`35 U.S.C. § References/Basis
`1–5, 7, 9, 10, 12–18, 20, 21 102
`Schaefer1
`
`1–7, 9, 10, 12–21
`
`11
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`11
`
`103
`
`103
`
`103
`
`Schaefer, Fujioka2
`
`Schaefer, Lysinger3
`
`Schaefer, Lysinger, Fujioka
`
`Pet. 6–7. Petitioner also relies on the Declaration of Robert Murphy.
`Ex. 1015.
`
`II. ANALYSIS
`A. LEVEL OF ORDINARY SKILL IN THE ART
`Petitioner proposes that a person of ordinary skill “would have had at
`least a degree in electrical or computer engineering, and at least two years of
`experience in design, development, and/or testing of memory circuits,
`related hardware design, or the equivalent, with additional education
`substituting for experience and vice versa.” Pet. 14 (citing Ex. 1015 ¶ 48).
`Patent Owner does not dispute this definition of a person of ordinary skill.
`See generally Prelim. Resp. For purposes of this Decision, we adopt
`Petitioner’s proposed level of ordinary skill as it appears to be consistent
`with the level of skill reflected by the Specification and in the asserted prior
`art references.
`
`
`1 U.S. Patent No. 5,600,605 (Ex. 1017).
`2 U.S. Patent No. 6,185,149 (Ex. 1006).
`3 U.S. Patent No. 5,784,331 (Ex. 1009).
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`B. CLAIM CONSTRUCTION
`For an inter partes review petition filed after November 13, 2018, we
`construe claim terms “using the same claim construction standard that would
`be used to construe the claim in a civil action under 35 U.S.C. 282(b).”
`37 C.F.R. § 42.100(b) (2019). Petitioner proposes constructions for the
`following terms: “non-interruptible,” “internal address signal,”
`“predetermined number of [said] internal address signals,” “fixed burst
`length,” “means for reading data” and “means for generating a
`predetermined number of said internal address signals.” Pet. 21–27.
`Patent Owner agrees that a number of terms were construed
`previously by a tribunal or were construed in a way agreed to by the parties
`involved, but asserts that only “non-interruptible” requires construction at
`this stage of the proceeding. Prelim. Resp. 13.
`Other than as addressed below, we conclude that none of the claim
`terms requires express construction or discussion at this time. See Nidec
`Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017
`(Fed. Cir. 2017).
`
`1. “non-interruptible”
`As to “non-interruptible,” the parties apply the construction adopted
`by the ITC in ITC-337-TA-792 (“the ’792 Investigation”)—“cannot be
`stopped or terminated once initiated until the fixed number of internal
`addresses has been generated.” Pet. 21; Prelim. Resp. 14. We proceed with
`that agreed-upon construction.
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`2. “predetermined number of internal address signals”
`“fixed burst length”
`Petitioner states that the ITC expressly construed the “predetermined”
`term as “a fixed number of internal address signals for a burst access” such
`that “predetermined” and “fixed” were synonymous. Pet. 22. Patent Owner
`does not disagree. Prelim. Resp. 13–14. Petitioner submits that we should
`construe the term to mean “occurring prior to receipt of the recited external
`address signal, clock signal, and one or more control signals.” Pet. 22–23.
`Petitioner submits further that the ITC applied the term in a narrower
`manner, such that “burst lengths defined by a programmable mode register
`are necessarily not ‘predetermined’ / ‘fixed.’” Id. at 23–24. Thus, Petitioner
`presents grounds under an alternative construction in which “predetermined”
`/ “fixed” means “occurring prior to initialization / power up (e.g., at
`manufacturing of the circuit).” Id.
`We do not understand any dispute regarding institution to turn on
`whether we adopt Petitioner’s primary or alternative construction. That is,
`Patent Owner does not dispute Petitioner’s primary, broader, construction of
`“predetermined.” Prelim. Resp. 13–14. We note that Petitioner’s alternative,
`narrower, construction appears to be inconsistent with dependent claim 5,
`which recites that the “fixed burst length is programmable,” but does not
`require it to be programmable at initialization. Ex. 1001, 5:40–41. Thus, we
`proceed with no express construction for “predetermined number.”
`
`3. “means for reading data . . . / means for generating a predetermined
`number of said internal address signals in response to (i) an external
`address signal, (ii) a clock signal and (iii) one or more control signals”
`The parties agree that the structure corresponding to the means for
`reading data is “memory array 104.” Pet. 25; Prelim. Resp. 15.
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`The parties appear to agree that the structure corresponding to the
`means for generating a predetermined number of internal address signals is
`“burst address counter/register 102,” which may take the form shown in
`either Figure 2 or Figure 3. Pet. 25–27; Prelim. Resp. 15–17.
`We accept both proposed constructions for purposes of this decision.
`
`C. ANTICIPATION BY SCHAEFER
`Schaefer discloses a “synchronous dynamic random access memory
`(SDRAM)” in which command signals and address bits cause a controller to
`access memory cells in a variety of ways. Ex. 1017, code (57). Schaefer
`explains that “a SDRAM requires separate commands for accessing and
`precharging a row of storage cells in the SDRAM memory array.” Id. at
`1:33–35. That precharge operation “deactivate[s] and precharge[s] a
`previously accessed bank memory ar[ra]y” and may result in wasted time
`between read and write operations. Id. at 1:42–54. Schaefer discloses the
`ability to use an “AUTO-PRECHARGE command feature” so that “a
`manual PRECHARGE command does not need to be issued during the
`functional operation” of the SDRAM. Id. at 7:29–40. “The
`AUTO-PRECHARGE command insures that the precharge is initiated at the
`earliest, valid stage within a burst cycle.” Id. at 7:40–42. When the
`AUTO-PRECHARGE command is used in conjunction with a READ or
`WRITE command, “[t]he user is not allowed to issue another command until
`the precharged time (tRP) is completed.” Id. at 7:42–44. To that end, “[a] no
`operation (NOP) command can be provided to SDRAM 20 to prevent other
`unwanted commands from being registered during idle or wait states.” Id. at
`8:8–10. Schaefer depicts the timing of a read operation using the
`auto-precharge option in Figure 4, reproduced below:
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`Figure 4 depicts a four-cycle burst transfer read operation, in which the
`READ command is given at time t2, the first cycle of data is output at time
`t4, and the precharge period tRP runs from time t6 to time t9. Id. at 8:37–9:1,
`Fig. 4.
`Petitioner contends that Schaefer discloses the required circuit
`elements through its SDRAM memory. Pet. 36–38 (quoting Ex. 1017,
`Fig. 1). In Petitioner’s view, by disclosing burst read and write operations
`that use the AUTO-PRECHARGE feature, Schaefer discloses generating a
`predetermined number of internal address signals such that the generation is
`non-interruptible. Pet. 40–43.
`Patent Owner challenges Petitioner’s showing, arguing first that
`Petitioner relies on a declarant to impermissibly fill gaps in Schaefer’s
`disclosures. Prelim. Resp. 34. In particular, Patent Owner argues that
`Schaefer does not disclose a bar on user commands prior to the start of the
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`precharge period (tRP) and that Petitioner’s assertion otherwise requires facts
`beyond Schaefer’s disclosure. Id. We do not agree. Petitioner and its
`declarant state that skilled artisans reading Schaefer would understand its
`disclosures in a certain manner. See Pet. 29–36. By explaining how the
`skilled artisan’s knowledge would bear on Schaefer’s disclosures, Petitioner
`and its declarant do not necessarily fill gaps in Schaefer.
`Patent Owner challenges whether Schaefer discloses non-interruptible
`address generation, arguing that Schaefer discloses three options for burst
`interruption: a “BURST TERMINATION” command, a “PRECHARGE”
`command, and an additional burst command. Prelim. Resp. 35 (citing
`Ex. 1017, 5:15–19). Although Schaefer discloses that, when using the
`AUTO-PRECHARGE option, “[t]he user is not allowed to issue another
`command until the precharged time (tRP) is completed,” Patent Owner
`submits that the initial portion of the read or write operation (before the
`precharge period begins) may be interrupted according to Schaefer’s three
`options. Id. at 36–37. Patent Owner relies on Schafer’s statement that, when
`using the AUTO-PRECHARGE option, “the precharge” is initiated at the
`earliest possible time and then “[t]he user is not allowed to issue another
`command until the precharged time (tRP) is completed.” Id. at 39 (quoting
`Ex. 1017, 7:38–50) (emphasis omitted). In Patent Owner’s view, that
`language supports only the proposition that user commands are prohibited
`during the precharge time, and Schaefer does not support Petitioner’s
`assertion of a prohibition starting with the original read/write command. Id.
`at 40–41.
`We do not agree with Patent Owner. Schaefer states that, with the
`“AUTO-PRECHARGE command feature,” a user may “program a READ
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`command or WRITE command that automatically performs a precharge
`upon the completion of the READ command or the WRITE command.”
`Ex. 1017, 7:32–37. It explains further that “[t]he AUTO-PRECHARGE
`command insures that the precharge is initiated at the earliest, valid stage
`within a burst cycle.” Id. at 7:40–42. Schaefer discloses that the
`AUTO-PRECHARGE option is selected when issuing the read/write
`command. Id. at Fig. 4 (CLK cycle T2). In such a case, “[t]he user is not
`allowed to issue another command until the precharged time (tRP) is
`completed.” Id. at 7:42–44 (emphasis added). Thus, Schaefer’s teachings
`support that the prohibition on user commands begins with the initial READ
`or WRITE command and ends with the completion of the precharge
`operation.
`Patent Owner relies also on Schaefer’s disclosure of an internal NOP
`command, which Patent Owner agrees “is the mechanism by which Schaefer
`prevents issuing additional user commands.” Id. at 41 (quoting Ex. 1017,
`8:65–9:1) (emphasis omitted). Patent Owner asserts that the NOP command
`“is not issued until the precharge command period (tRP) begins at t6” but
`Figure 4 shows that NOP commands are issued at every clock period
`between the initial read/write command and completion of the precharge
`operation. Ex. 1017, Fig. 4 (showing NOP commands for CLK periods t3
`through t8). Thus, Schaefer discloses that, when using the
`AUTO-PRECHARGE option, user commands (including one that could
`interrupt the burst generation) are blocked during the entire period from a
`read/write command to completion of the precharge operation.
`Patent Owner argues also that Schaefer is concerned with eliminating
`wasted cycles between burst operations, not preventing interruptions within
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`a burst. Prelim. Resp. 42–43. That focus, according to Patent Owner, gives
`reason not to interpret Schaefer’s disclosures as including the initial burst
`period within the precharge-period prohibition on user commands. Id. That
`argument is not persuasive because Schaefer’s disclosures, as explained
`above, show that user commands are prohibited during the entire period
`from the initial read/write command to the completion of the precharge
`operation.
`Separately, Patent Owner argues that Schaefer’s burst-termination
`options apply not only to Schaefer’s full page burst commands, as Petitioner
`contends, but to fixed burst commands that use the AUTO-PRECHARGE
`command because Schaefer discloses that its SDRAM “can be programmed
`to perform 2, 4, 8, or full page cycle burst operations and the present
`invention is not limited to a four burst transfer operation.” Prelim. Resp. 44
`(quoting Ex. 1017, 8:57–60) (emphasis omitted). We do not agree that
`Schaefer’s statement that its invention includes “full page cycle burst
`operations” also means that all embodiments must support the
`AUTO-PRECHARGE command. Rather, Schaefer’s disclosures support that
`auto precharge is an optional feature. Ex. 1017, 2:20–26 (describing auto-
`precharge as used “optionally”). Thus, Patent Owner’s argument is not
`persuasive.
`We have reviewed the parties submissions and determine that the
`present record supports that Petitioner is reasonably likely to prevail with
`respect to anticipation of claims 1–5, 7, 9, 10, 12–18, 20, and 21 by
`Schaefer.
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`D. OBVIOUSNESS OVER SCHAEFER AND LYSINGER
`Claim 11 depends from claim 1 and recites that the “predetermined
`number of internal address signals is chosen to meet predetermined criteria
`for sharing address and control busses.” Ex. 1001, 6:4–7. Petitioner submits
`that claim 11 would have been obvious over the combined disclosures of
`Schaefer and Lysinger. Pet. 77–82.
`Lysinger discloses a memory circuit with a burst controller that
`increments memory addresses. Ex. 1009, 2:5–7. As one approach, Lysinger
`teaches delaying the transmission of a new address until the end of a
`possible “timing window” such that the memory device may “perform other
`functions such as accessing other memory devices or interfacing with the
`microprocessor.” Id. at 26:34–49.
`Petitioner asserts that skilled artisans “would have understood the
`advantage of increased data throughput by being able to access additional
`memory arrays by using the address and control busses that were freed.”
`Pet. 80 (citing Ex. 1015 ¶ 168). At this stage, Patent Owner does not
`challenge Petitioner’s assertions regarding Lysinger. See Prelim. Resp. 45–
`46.
`
`We have reviewed the parties’ submissions and determine that the
`present record supports that Petitioner is reasonably likely to prevail with
`respect to obviousness of claim 11 over Schaefer and Lysinger.
`
`E. OBVIOUSNESS GROUNDS INCLUDING FUJIOKA
`Fujioka discloses a memory circuit with burst operation where the
`burst length may be set in a variety of ways. See Ex. 1006, code (57). One
`such way includes reading a register’s value to determine the burst length.
`Id. at 6:7–8, Fig. 4. Another way is to set the burst length during a device’s
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`manufacture, based on wire bonding, laser-cut fuses, or switches. Id.
`at 14:50–15:24, Figs. 10A–10F.
`Petitioner submits that, under the alternative construction requiring
`that the “predetermined” number of internal address signals be set prior to
`manufacturing, the challenged claims would have been obvious over the
`same grounds discussed above, each further modified by Fujioka’s teachings
`regarding setting the burst length at time of manufacture. Pet. 64–77, 82–83.
`As noted above, although we need not construe “predetermined number” for
`purpose of institution, a narrow construction that requires fixation at the time
`of manufacture does not appear to be consistent with certain dependent
`claims. See supra at 8. Nonetheless, Petitioner’s grounds including Fujioka
`demonstrate how Petitioner is reasonably likely to show the claims are
`unpatentable under such a narrow construction. Patent Owner does not raise
`any arguments specific to the grounds including Fujioka. See Prelim.
`Resp. 45.
`
`F. DISCRETIONARY DENIAL UNDER § 314(A)
`The Director has discretion to institute inter partes review. See
`35 U.S.C. § 314(a); SAS Inst. Inc. v. Iancu, 138 S. Ct. 1348, 1356 (2018)
`(“[Section] 314(a) invests the Director with discretion on the question
`whether to institute review . . . .” (emphasis omitted)). That discretion has
`been delegated to the Board, which considers and weighs several non-
`exclusive factors in determining whether to exercise it. See 37 C.F.R.
`§ 42.4(a); General Plastic Co., Ltd. v. Canon Kabushiki Kaisha, IPR2016-
`01357, slip op. 15–16, Paper 19 (PTAB Sept. 6, 2017) (precedential).
`Patent Owner asserts that we should exercise our discretion to deny
`institution because the Petition challenges the same patent as the petition in
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`IPR2020-00985, filed by Advanced Micro Devices (“AMD”). Prelim.
`Resp. 24–33. Patent Owner argues the General Plastic factors support that
`outcome. Id. We consider those factors as follows.
`
`1. Factor 1: whether the same petitioner previously filed a petition
`directed to the same claims of the same patent
`Factor 1 may apply to petitions filed by two separate petitioners,
`taking into account “any relationship between those petitioners.” Valve
`Corp. v. Elec. Scripting Prods., Inc., IPR2019-00062, Paper 11, 9 (PTAB
`Apr. 2, 2019) (precedential). Patent Owner argues that Petitioner and AMD
`have a significant relationship because they “are joint defendants in parallel
`underlying District Court litigations” and “stand accused of infringing the
`’134 patent based on the same accused instrumentalities: products including,
`using, or supporting JEDEC DDR-compliant memory devices.” Prelim.
`Resp. 27. Patent Owner asserts also that AMD and Petitioner are in a joint-
`defense group, which supports their relationship. Id. at 28. Petitioner points
`out that, in fact, it and AMD are distinct parties, direct competitors sued
`separately in the district court. Prelim. Reply 1.
`Patent Owner argues also that because the two petitions challenge
`nearly the same set of claims (the present omits only claim 8), we should
`find a relationship between the two petitioners. Prelim. Resp. 28. We do not
`agree that a substantive overlap shows a relationship between the parties.
`Factor 1 weighs strongly against denying institution because
`Petitioner and AMD are not co-defendants and are not accused of
`infringement based on the same products. See Ex. 1024 (complaint against
`AMD); Ex. 1026 (complaint against Petitioner). Even if Petitioner and AMD
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`are in a joint-defense group, that does not establish a relationship that
`counsels for denying institution.
`
`2. Factor 2: whether at the time of filing of the first petition the petitioner
`knew of the prior art asserted in the second petition
`or should have known of it
`The parties here are neither the same party nor related parties.
`Therefore, we find the second General Plastic factor has a limited, neutral
`value, in this proceeding. See NetApp Inc. v. Realtime Data LLC, IPR2017-
`01195, Paper 9 at 10 (PTAB Oct. 12, 2017).
`
`3. Factor 3: whether at the time of filing of the second petition the
`petitioner already received the patent owner’s preliminary response to the
`first petition or received the Board’s decision on whether to institute review
`in the first petition
`Patent Owner admits that Petitioner filed the present Petition before
`receiving Patent Owner’s preliminary response to AMD’s petition. Prelim.
`Resp. 30. Thus, factor 3 weighs against exercising discretion to deny
`institution.
`
`4. Factors 4 and 5: the length of time that elapsed between the time the
`petitioner learned of the prior art asserted in the second petition and the
`filing of the second petition; and whether the petitioner provides adequate
`explanation for the time elapsed between the filings of multiple petitions
`directed to the same claims of the same patent
`Patent Owner asserts that, because Petitioner knew of the Fujioka and
`Lysinger references no later than when AMD filed its petition, Petitioner
`delayed three months without explanation. Prelim. Resp. 31–32.
`Factors 4 and 5 weigh against discretionary denial. The Petition was
`filed before the November 4, 2020, statutory deadline. Prelim. Reply 2.
`Petitioner submits that it “had zero influence over AMD’s Petitions, only
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`Patent 6,651,134 B1
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`learning of them upon their filing.” Id. Petitioner further submits that its
`counsel developed invalidity positions from the time the suit was filed until
`filing the Petition. Id. Indeed, this Petitioner asserts a different primary
`reference from AMD’s Petition. See id. at 3. We determine Petitioner
`adequately explains the time that passed before filing the Petition. Thus,
`Factors 4 and 5 weigh against denying institution.
`
`5. Factors 6 and 7: the finite resources of the Board; and the requirement
`to issue a final determination not later than one year after institution
`Patent Owner asserts that the substantive overlap between this
`proceeding and the AMD proceeding supports denying institution. Prelim.
`Resp. 32–33.
`Factors 6 and 7 weigh against discretionary denial. This proceeding
`involves a different primary reference that appears to have a materially
`different disclosure compared to the primary reference at issue in the AMD
`proceeding. Thus, maintaining two proceedings has a substantial possibility
`of different results. Additionally, the substantive overlap between the two
`proceedings relates to the asserted secondary references, which Patent
`Owner has not challenged at this point. See Prelim. Reply 3. That overlap
`reduces the additional burden on the Board.
`
`6. Conclusion on discretionary denial
`For the reasons discussed, the General Plastic factors weigh against
`denying institution here. Accordingly, we do not exercise our discretion to
`deny institution.
`
`18
`
`
`
`IPR2020-01492
`Patent 6,651,134 B1
`
`
`III. CONCLUSION
`For the reasons discussed above, we conclude Petitioner has shown a
`reasonable likelihood of prevailing with respect to at least one claim. We
`have evaluated all of the parties’ submissions and determine that the record
`supports institution.
`Our determination at this stage of the proceeding is based on the
`evidentiary record currently before us. This decision to institute trial is not a
`final decision as to patentability of any claim for which inter partes review
`has been instituted. Our final decision will be based on the full record
`developed during trial.
`
`IV. ORDER
`
`Accordingly, it is
`ORDERED that, pursuant to 35 U.S.C. § 314(a), inter partes review
`of claims 1–7 and 9–21 of the ’134 patent is instituted on the grounds set
`forth in the Petition;
`FURTHER ORDERED that, pursuant to 35 U.S.C. § 314(c) and
`37 C.F.R. § 42.4, notice is hereby given of the institution of a trial
`commencing on the entry date of this decision.
`
`
`19
`
`
`
`IPR2020-01492
`Patent 6,651,134 B1
`PETITIONER:
`Eagle H. Robinson
`Daniel S. Leventhal
`Richard S. Zembek
`NORTON ROSE FULBRIGHT US LLP
`eagle.robinson@nortonrosefulbright.com
`daniel.leventhal@nortonrosefulbright.com
`richard.zembek@nortonrosefulbright.com
`
`
`PATENT OWNER:
`
`Theodoros Konstantakopoulos
`Yung-Hoon Ha
`Christian M. Dorman
`DESMARAIS LLP
`tkonstantakopoulos@desmaraisllp.com
`yha@desmaraisllp.com
`cdorman@desmaraisllp.com
`
`
`
`
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