`
`Paper No. 1
`Filed: August 10, 2020
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`INTEL CORPORATION,
`Petitioner
`v.
`FG SRC LLC,
`Patent Owner
`____________________
`CASE NO.: IPR2020-01449
`PATENT NO. 7,149,867
`____________________
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,149,867
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`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`TABLE OF CONTENTS
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`Page
`INTRODUCTION ............................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ....................................... 2
`A. Real party-in-interest under 37 C.F.R. § 42.8(b)(1) ...................................... 2
`B. Related matters under 37 C.F.R. § 42.8(b)(2) ............................................... 2
`C. Lead and back-up counsel under 37 C.F.R. § 42.8(b)(3) .............................. 3
`D. Service information under 37 C.F.R. § 42.8(b)(4) ........................................ 3
`III. REQUIREMENTS FOR IPR .............................................................................. 3
`A. Payment under 37 C.F.R. § 42.103 ............................................................... 4
`B. Certification of standing under 37 C.F.R. § 42.104(a) .................................. 4
`C. Identification of challenge under 37 C.F.R. § 42.104(b) .............................. 4
`1. Challenged claims and claim constructions ............................................ 4
`2. Specific grounds, supporting evidence and claim-by-claim
`analysis, and exhibit number and relevance of supporting
`evidence ................................................................................................... 4
`IV. DISCRETIONARY FACTORS .......................................................................... 6
`A. Denial is not warranted under §314(a) .......................................................... 6
`B. Denial is not warranted under §325(d) .......................................................... 8
`V. TECHNOLOGICAL BACKGROUND ............................................................ 10
`A. Conventional computer architecture and data prefetch ............................... 10
`B. FPGAs .......................................................................................................... 11
`C. Scatter/Gather .............................................................................................. 12
`VI. THE ’867 PATENT ........................................................................................... 13
`A. Summary of the patent ................................................................................. 13
`B. Priority date and prosecution history ........................................................... 13
`C. Level of ordinary skill in the art .................................................................. 14
`D. Claim construction ....................................................................................... 14
`1. “reconfigurable processor” in all claims ............................................... 14
`2. “data prefetch unit” in all claims ........................................................... 14
`3. “data access unit” in claims 11-19 ........................................................ 15
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`4. “functional unit” .................................................................................... 15
`5. “memory hierarchy” .............................................................................. 15
`6. “computational unit” in claims 11-19 ................................................... 15
`SPECIFIC GROUNDS ................................................................................ 16
`VII.
`A. Overview of the cited prior art references ................................................... 16
`1. Zhang (EX1003) .................................................................................... 17
`2. Gupta (EX1004) .................................................................................... 19
`3. Chien (EX1005)..................................................................................... 21
`B. A person of ordinary skill in the art would have been motivated
`to combine the Zhang, Gupta and Chien references ................................... 22
`C. Ground 1: Claims 1-2, 4-8 and 13-19 are obvious over Zhang
`and Gupta ..................................................................................................... 28
`1. Claim 1: ................................................................................................. 28
`a. Preamble: A reconfigurable processor that instantiates
`an algorithm as hardware comprising: ............................................ 28
`b. 1(a): a first memory having a first characteristic memory
`bandwidth and/or memory utilization ............................................. 30
`c. 1(b): a data prefetch unit coupled to the first memory .................... 32
`d. 1(c): wherein the data prefetch unit retrieves only
`computational data required by the algorithm from a
`second memory of second characteristic memory
`bandwidth and/or memory utilization and places the
`retrieved computational data in the first memory ........................... 36
`e. 1(d): wherein the data prefetch unit operates
`independent of and in parallel with logic blocks using
`the computional [sic] data ............................................................... 41
`f. 1(e): wherein at least the first memory and data prefetch
`unit are configured to conform to needs of the algorithm .............. 46
`g. 1(f): the data prefetch unit is configured to match format
`and location of data in the second memory..................................... 49
`2. Claim 2: The reconfigurable processor of claim 1, wherein: ................ 53
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`ii
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`a. 2(a): the data prefetch unit is coupled to a memory
`controller that controls the transfer of data between the
`second memory and the data prefetch unit ...................................... 53
`b. 2(b): and [the memory controller] transmits only
`portions of data desired by the data prefetch unit and
`discards other portions of data prior to transmission of
`the data to the data prefetch unit ..................................................... 57
`3. Claim 4: The reconfigurable processor of claim 1, wherein
`the data prefetch unit comprises at least one register from
`the reconfigurable processor ................................................................. 58
`4. Claim 5: The reconfigurable processor of claim 1, wherein
`the data prefetch unit is disassembled when another program
`is executed on the reconfigurable processor ......................................... 60
`5. Claim 6: The reconfigurable processor of claim 1 wherein
`said second memory comprises a processor memory and
`said data prefetch unit is operative to retrieve data from the
`processor memory ................................................................................. 61
`6. Claim 7: The reconfigurable processor of claim 6 wherein
`said processor memory is a microprocessor memory ........................... 61
`7. Claim 8: The reconfigurable processor of claim 6 wherein
`said processor memory is a reconfigurable processor
`memory .................................................................................................. 62
`8. Claim 13: A method of transferring data comprising: .......................... 63
`a. 13(a): transferring data between a memory and a data
`prefetch unit in a reconfigurable processor ..................................... 63
`b. 13(b): transferring the data between a computational
`unit and a data access unit ............................................................... 64
`c. 13(c): wherein the computational unit and the data
`access unit, and the data prefetch unit are configured to
`conform to needs of an algorithm implemented on the
`computational unit and transfer only data necessary for
`computations by the computational unit ......................................... 67
`d. 13(d): wherein the prefetch unit operates independent of
`and in parallel with the computational unit ..................................... 69
`9. Claim 14 ................................................................................................ 69
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`iii
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`a. 14(a): The method of claim 13, wherein the data is
`written to the memory, said method comprising: ........................... 69
`b. 14(b): transferring the data from the computational unit
`to the data access unit ...................................................................... 70
`c. 14(c): writing the data to the memory from the prefetch
`unit ................................................................................................... 71
`10. Claim 15: ............................................................................................... 72
`a. 15(a): The method of claim 13, wherein the data is read
`from the memory, said method comprising: ................................... 72
`b. 15(b): transferring only the data desired by the data
`prefetch unit as required by the computational unit from
`the memory to the data prefetch unit .............................................. 73
`c. 15(c): reading the data directly from the data prefetch
`unit to the computational unit through a data access unit ............... 74
`11. Claim 16: The method of claim 15, wherein all the data
`transferred from the memory to the data prefetch unit is
`processed by the computational unit ..................................................... 74
`12. Claim 17: The method of claim 15, wherein the data is
`selected by the data prefetch unit based on an explicit
`request from the computational unit ...................................................... 75
`13. Claim 18: The method of claim 13, wherein the data
`transferred between the memory and the data prefetch unit
`is not a complete cache line ................................................................... 75
`14. Claim 19: The method of claim 13, wherein a memory
`controller coupled to the memory and the data prefetch unit,
`controls the transfer of the data between the memory and the
`data prefetch unit ................................................................................... 76
`D. Ground 2: Claims 3 and 9-12 are obvious over Zhang, Gupta
`and Chien ..................................................................................................... 76
`1. Claim 3: The reconfigurable processor of claim 1, wherein
`the data prefetch unit receives processed data from on-
`processor memory and writes the processed data to an
`external off-processor memory ............................................................. 76
`2. Claim 9: ................................................................................................. 83
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`iv
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`a. Preamble: A reconfigurable hardware system
`comprising: ...................................................................................... 83
`b. 9(a): a common memory ................................................................. 83
`c. 9(b): one or more reconfigurable processors that can
`instantiate an algorithm as hardware coupled to the
`common memory ............................................................................ 84
`d. 9(c): wherein at least one of the reconfigurable
`processors includes a data prefetch unit to read and
`write only data required for computations by the
`algorithm between the data prefetch unit and the
`common memory ............................................................................ 85
`e. 9(d): wherein the data prefetch unit operates
`independent of and in parallel with logic blocks using
`the computational data .................................................................... 85
`f. 9(e): wherein the data prefetch unit is configured to
`conform to needs of the algorithm .................................................. 85
`g. 9(f): and [the data prefetch unit is configured to] match
`format and location of data in the common memory ...................... 86
`3. Claim 10: The reconfigurable hardware system of claim 9,
`comprising a memory controller coupled to the common
`memory and the data prefetch unit that transmits to the
`prefetch unit only data desired by the data prefetch unit as
`required by the algorithm ...................................................................... 86
`4. Claim 11: The reconfigurable hardware system of claim 9,
`wherein the at least one of the reconfigurable processors
`also includes a computational unit coupled to a data access
`unit ......................................................................................................... 87
`5. Claim 12: The reconfigurable hardware system of claim 11,
`wherein the computational unit is supplied the data by the
`data access unit ...................................................................................... 87
`VIII. CONCLUSION ........................................................................................... 87
`IX. CERTIFICATE OF COMPLIANCE ................................................................. 89
`CERTIFICATE OF SERVICE ................................................................................ 90
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`TABLE OF AUTHORITIES
`
`Cases
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`Page(s)
`
`FG SRC LLC v. Intel Corp.,
`No. 6:20-cv-00315-ADA (W.D. Texas) ............................................................... 2
`FG SRC LLC v. Xilinx, Inc.,
`No. 1:20-cv-00601 (D. Delaware) ........................................................................ 2
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 24
`Ruiz v. A.B. Chance Co.,
`357 F.3d 1270 (Fed. Cir. 2004) .......................................................................... 24
`SRC Labs, LLC et al., v. Amazon Web Services, Inc., et al.,
`No. 2:18-cv-00317 (W.D. Washington) ............................................................... 2
`Administrative Proceedings
`Par Pharm., Inc. v. Jazz Pharm., Inc., IPR2016-01356
`Paper 19 (PTAB Sept. 6, 2017) ............................................................................ 6
`OneD Material LLC v. Nexeon Ltd., IPR2016-01528
`Paper 10 (PTAB Feb. 9, 2017) ........................................................................... 23
`Valve Corp. v. Electronic Scripting Products, Inc., IPR2019‐00062
`Paper 11 (PTAB April 2, 2019) ............................................................................ 6
`Amazon.com, Inc. v. St. Regis Mohawk Tribe, IPR2019-00103
`Paper 1 (PTAB Oct. 19, 2019) .......................................................................... 8, 9
`Paper 22 (PTAB May 10, 2019) ................................................................... 2, 7, 9
`Paper 24 (PTAB June 9, 2020) ......................................................................... 7, 9
`
`Advanced Bionics, LLC et al v. MED-EL Elektromedizinische Geraete
`GmbH, IPR2019-01469
`Paper 6 (PTAB Feb. 13, 2020) ............................................................................. 8
`Apple Inc. v. Fintiv, Inc., IPR2020-00019
`Paper 11 (PTAB March 20, 2020) ........................................................................ 7
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`vi
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`Statutes and Codes
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`United States Code
`Title 35, Section 102 ............................................................................................. 4
`Title 35, Section 102(a) ...............................................................................passim
`Title 35, Section 102(b) ...............................................................................passim
`Title 35, Section 103 ............................................................................................. 4
`Title 35, Section 112 ........................................................................................... 14
`Title 35, Section 314(a) ........................................................................................ 6
`Title 35, Section 325(d) ........................................................................................ 8
`Rules and Regulations
`
`Code of Federal Regulations
`Title 37, Section 42.8 ............................................................................................ 2
`Title 37, Section 42.8(b)(1)................................................................................... 2
`Title 37, Section 42.8(b)(2)................................................................................... 2
`Title 37, Section 42.8(b)(3)................................................................................... 3
`Title 37, Section 42.8(b)(4)................................................................................... 3
`Title 37, Section 42.10(b) ..................................................................................... 3
`Title 37, Section 42.15(a) ..................................................................................... 4
`Title 37, Section 42.103 ........................................................................................ 4
`Title 37, Section 42.104(a) ................................................................................... 4
`Title 37, Section 42.104(b) ................................................................................... 4
`Title 37, Section 42.106 ........................................................................................ 3
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`vii
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`TABLE OF EXHIBITS
`
`Description
`Exhibit No.
`Exhibit 1001 U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June
`16, 2004, and issued on December 12, 2006 (the “’867 patent”).
`Exhibit 1002 Prosecution history of the ’867 patent.
`Exhibit 1003 X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”).1
`Exhibit 1004 R. Gupta, Architectural Adaptation in AMRM Machines, IEEE
`(2000) (“Gupta”).
`Exhibit 1005 A. Chien and R. Gupta, MORPH: A System Architecture for
`Robust Higher Performance Using Customization,” IEEE (1996)
`(“Chien”).
`Exhibit 1006 Declaration of Stanley Shanfield, Ph.D.
`Exhibit 1007 RESERVED
`Exhibit 1008 RESERVED
`Exhibit 1009 RESERVED
`Exhibit 1010 Declaration of Rajesh K. Gupta
`Exhibit 1011 Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999).
`Exhibit 1012 Declaration of Jacob Munford
`Exhibit 1013 RESERVED
`
`
`1 For ease of reference and citation, Petitioner has added line numbers to Exhibits
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`1003, 1004, 1005 and 1011. For example, the citation “EX1003-15 C2:4-16” refers
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`to Exhibit 1003, Page 15, Column 2, Lines 4-16, and the subsequent citation “id.-
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`12 C1:12-C2:5” refers to Exhibit 1003, Page 12, Column 1, Line 12 through
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`Column 2, Line 5.
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`Description
`Exhibit No.
`Exhibit 1014 Order Governing Proceedings - Patent Case by Judge Alan D
`Albright, filed on June 30, 2020 in FG SRC LLC v. Intel
`Corporation, No. 6:20-cv-00315-ADA (W.D. Tex.)
`Exhibit 1015 Scheduling Order by Judge Alan D Albright, filed on August 1,
`2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-00315-
`ADA (W.D. Tex.)
` Plaintiffs SRC Labs, LLC & Saint Regis Mohawk Tribe's
`Opening Claim Construction Brief, filed on November 5, 2018 in
`SRC Labs, LLC et al. v. Amazon Web Services, Inc. et al., No.
`2:18-cv-00317-JLP (W.D. Was.)
`Exhibit 1017 Provisional Patent Application No. 60/479,339
`Exhibit 1018 Plaintiff's Preliminary Infringement Contentions, submitted on
`July 23, 2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-
`00315-ADA (W.D. Tex.)
`
`Exhibit 1016
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`ix
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`I.
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`INTRODUCTION
`U.S. Patent 7,149,867 (EX1001) purports to invent the use of data prefetch
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`in a reconfigurable hardware system. However, Patent Owner has conceded that
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`data prefetch has been used to move data between memories in a memory
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`hierarchy since the mid-1960s. Moreover, reconfigurable processors and
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`hardware systems, such as field programmable gate arrays (“FPGAs”), were well-
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`known devices for implementing software algorithms as computer hardware long
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`before the ’867 patent’s earliest alleged priority date. The patent thus faced
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`multiple rejections and was allowed only after claim amendments requiring a data
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`prefetch unit that: (1) retrieves only computational data required by an algorithm
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`instantiated on the processor; (2) operates independent of and in parallel with logic
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`blocks using the computational data; and (3) is configurable to conform to the
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`needs of the algorithm and match format and location of data in the second
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`memory.
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`The asserted grounds are based on three publications describing the same
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`research project that began as early as 1996. That project implemented data
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`prefetch techniques in reconfigurable hardware systems using a data prefetch unit
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`that practiced each of the limitations that resulted in the patent’s allowance. It even
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`used a scatter/gather technique like the patent’s disclosed embodiment. None of
`1
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`these references were cited in prosecution. Thus, Petitioner requests an IPR to
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`cancel claims 1-19 (“Challenged Claims”) of the ’867 patent.
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`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`A. Real party-in-interest under 37 C.F.R. § 42.8(b)(1)
`Intel is the only real party-in-interest.
`
`B. Related matters under 37 C.F.R. § 42.8(b)(2)
`The ’867 patent is currently the subject of a lawsuit in the United States
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`District Court for the Western District of Texas: FG SRC LLC v. Intel Corp., No.
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`6:20-cv-00315-ADA (W.D. Texas), filed April 24, 2020.
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`The ’867 patent is also subject to additional lawsuits not involving
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`Petitioner: SRC Labs, LLC et al., v. Amazon Web Services, Inc., et al., No. 2:18-cv-
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`00317 (W.D. Washington), filed Feb. 26, 2018; and FG SRC LLC v. Xilinx, Inc.,
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`No. 1:20-cv-00601 (D. Delaware), filed April 30, 2020.
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`The ’867 patent was previously the subject of an IPR not involving
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`Petitioner: Amazon.com, Inc., et al., v. St. Regis Mohawk Tribe et al., IPR2019-
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`00103, filed October 19, 2018. Intel was not a petitioner or real party-in-interest to
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`that proceeding, nor was Intel otherwise involved in that proceeding. The Board
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`declined to institute. Id., Paper 22 (PTAB May 10, 2019).
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`2
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`C. Lead and back-up counsel under 37 C.F.R. § 42.8(b)(3)
`
`Lead Counsel
`Brian C. Nash, Reg. No. 58,105
`PILLSBURY WINTHROP SHAW
`PITTMAN LLP
`401 Congress Avenue, Ste 1700
`Austin, Texas 78701
`Telephone: (512) 580-9629
`Facsimile: (512) 580-9601
`Email:
`brian.nash@pillsburylaw.com
`
`
`Back-up Counsel
`Evan Finkel, Reg. No. 49,059
`PILLSBURY WINTHROP SHAW
`PITTMAN LLP
`725 South Figueroa Street, Ste 2800
`Los Angeles, CA 90017-5406
`Telephone: (213) 488-7307
`Facsimile: (213) 226-4058
`Email:
`evan.finkel@pillsburylaw.com
`
`Matthew W. Hindman, Reg. No. 57,396
`PILLSBURY WINTHROP SHAW
`PITTMAN LLP
`2550 Hanover Street
`Palo Alto, CA 94304
`Telephone: (650) 233-4087
`Facsimile: (650) 233-4545
`Email:
`matthew.hindman@pillsburylaw.com
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`Service information under 37 C.F.R. § 42.8(b)(4)
`Intel consents to electronic service to the email address: Intel-
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`D.
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`SRC@Pillsburylaw.com. A Power of Attorney pursuant to 37 C.F.R. § 42.10(b) is
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`filed concurrently herewith.
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`III. REQUIREMENTS FOR IPR
`This Petition complies with all statutory and regulatory requirements and
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`should be accorded the filing date of this Petition pursuant to 37 C.F.R. §42.106.
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`A.
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`Payment under 37 C.F.R. § 42.103
`The Office is authorized to charge Account No. 033975 for the fee in
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`§42.15(a) and any additional fees in connection with this Petition.
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`B. Certification of standing under 37 C.F.R. § 42.104(a)
`Petitioner certifies that the ’867 patent is available for IPR and that
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`Petitioner is not barred or estopped from requesting IPR on the Challenged Claims.
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`C.
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`Identification of challenge under 37 C.F.R. § 42.104(b)
`1.
`Challenged claims and claim constructions
`Petitioner requests an IPR trial on claims 1-19 of the ’867 patent to cancel
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`each claim. Petitioner’s proposed constructions are in Section VI.D., infra.
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`2.
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`Specific grounds, supporting evidence and claim-by-claim
`analysis, and exhibit number and relevance of supporting
`evidence
`The following prior art references render the Challenged Claims obvious
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`under 35 U.S.C. §1032:
`
` X. Zhang et al., Architectural Adaptation of Application-Specific Locality
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`Optimizations, IEEE (1997) (“Zhang”) (EX1003). Zhang was published
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`in 1997 and is prior art under at least §102(a) and §102(b).
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`2 All references herein to 35 U.S.C. §§102 and 103 refer to pre-AIA sections.
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`4
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` R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
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`(“Gupta”) (EX1004). Gupta was published in 2000 and is prior art under
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`at least §102(a) and §102(b).
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` A. Chien and R. Gupta, MORPH: A System Architecture for Robust
`
`Higher Performance Using Customization,” IEEE (1996) (“Chien”)
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`(EX1005). Chien was published in 1996 and is prior art under at least
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`§102(a) and §102(b).
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`The specific grounds for challenge are set forth below, and are supported by
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`the Declaration of Dr. Stanley Shanfield (EX1006). In this Petition and in Dr.
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`Shanfield’s declaration, Petitioner has identified the exhibit number of supporting
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`evidence relied upon to support the challenge and has explained the relevance of
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`that evidence to the challenge. See Section VII, infra; EX1006.
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` Ground 1: Claims 1-2, 4-8, 13-19 are unpatentable as obvious over
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`Zhang in view of Gupta as understood by one of ordinary skill in the art.
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` Ground 2: Claims 3 and 9-12 are unpatentable as obvious over Zhang in
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`view of Gupta and Chien as understood by one of ordinary skill in the art.
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`5
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`IV. DISCRETIONARY FACTORS
`A. Denial is not warranted under §314(a)
`The Board should not exercise discretion to deny institution due to a prior
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`petition filed by a different party. See IPR2016-01356, Paper 19 (PTAB Sept. 6,
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`2017); IPR2019‐00062, Paper 11 (PTAB April 2, 2019). First, this is Petitioner’s
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`first and only petition challenging the ’867 patent. A prior petition was filed by
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`Amazon.com, Inc. See IPR 2019-00103. Petitioner is not related to Amazon, was
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`not a co-defendant with Amazon, and was not involved in that IPR or its parallel
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`district court proceeding. Second, Petitioner relies on references different from
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`those underlying Amazon’s petition (Zhang, Gupta, and Chien vs. Lange and
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`Zhong). Thus, Petitioner’s grounds were not considered in the prior proceeding.
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`Third, Petitioner filed this Petition just over three months after Patent Owner filed
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`its lawsuit against Petitioner, prior to which Petitioner had not been accused of
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`infringing the ’867 patent. Petitioner diligently investigated and prepared this
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`Petition within that short time. Lastly, this IPR would be an appropriate use of
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`Board resources for all the reasons given above and because the Board has not yet
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`considered the ’867 patent’s validity because Amazon’s petition used an incorrect
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`construction and thus failed to specify with particularity how the prior art teaches
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`6
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`the Challenged Claims as properly construed, see IPR2019-00103, Paper 22
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`(PTAB May 10, 2019); id., Paper 24.
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`The Board also should not exercise its discretion to deny institution based on
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`concurrent litigation. See IPR2020-00019, Paper 11 at 5-6 (PTAB March 20,
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`2020). First, discovery in the district court case is stayed pending a claim
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`construction hearing, EX1014, and Petitioner intends to request a stay if an IPR
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`proceeding is instituted. Second, there is no conflict between the projected
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`timelines. That case is just beginning, and no trial date has been set. The Case
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`Management Conference was held on July 30, 2020, and a claim construction
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`hearing is scheduled for February 5, 2021. EX1016. Third, neither the parties nor
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`the court have invested much in the parallel case. Discovery is stayed, and the
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`parties will only have provided initial contentions and engaged in claim
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`construction proceedings before an institution decision here. Fourth, the Petition
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`challenges all claims of the ’867 patent, whereas the parallel case only involves
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`claims 1, 3-4, 9, 11 and 12, see EX1018, making this IPR an efficient use of the
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`Board’s resources. Finally, there will not be an overlap in issues. Petitioner
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`stipulates that if IPR is instituted, Petitioner will not raise these same Grounds in
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`the district court proceeding.
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`7
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`B. Denial is not warranted under §325(d)
`The Board should only deny institution under §325(d) if the same or
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`substantially the same prior art or arguments were presented to the Office.
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`IPR2019-01469, Paper 6 at 7 (PTAB Feb. 13, 2020). That is not the case here. This
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`Petition raises invalidity challenges based on Zhang, Gupta, and Chien, none of
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`which was the basis for a rejection or ever before the Examiner/Patent Office, see
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`EX1002,3 nor raised as grounds in the prior IPR, see IPR2019-00103, Paper 1.
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`Moreover, Zhang, Gupta, and Chien are materially different from—and not
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`cumulative of—prior art and arguments already presented. During prosecution:
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` The Examiner primarily relied on Paulraj as anticipating the claims. See
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`EX1002 53-68, 104-17, 145-60, 175-89.
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`3 The Examiner’s search identified a different article by one of the same authors.
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`See EX1002, 69. That article, which was never used in a rejection or otherwise
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`referenced by the Examiner, see EX1002 53-68, 104-17, 145-60, 175-89, focused
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`on the project’s protection architecture for the multi-process environment rather
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`than a prefetch capability as claimed in the ’867 patent. See EX1011; EX1006
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`¶126.
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`8
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` Applicants argued Paulraj did not disclose a data prefetch unit that (1)
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`retrieves only computational data required by an algorithm, and (2)
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`operates independent of and in parallel with the computational unit. Id.
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`201.
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` Applicants amended the claims to require those purported distinctions
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`and to require the data prefetch unit be configurable to conform to needs
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`of an algorithm and match format and location of the data. Id. 197-200.
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` The Examiner identified those distinctions as a basis for allowance.
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`EX1002 231.
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`In contrast, Zhang, Gupta, and Chien teach the limitations purportedly missing
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`from Paulraj. See Section VII. Similarly, in the prior IPR:
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` Amazon relied on Lange and Zhong. See IPR2019-00103, Paper 1.
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` The Board did not fully evaluate the merits of whether either of those
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`references met the Challenged Claims’ limitations because Amazon used
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`an incorrect construction. Id. Paper 22; Id. Paper 24.
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`Here, in contrast, Petitioner has identified with particularity how the combinations
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`teach the limitations of the Challenged Claims as properly construed. See Sections
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`VI.D., VII.
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`9
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`V. TECHNOLOGICAL BACKGROUND
`A. Conventional computer architecture and data prefetch
`A central processing unit (i.e., CPU or processor) is the circuitry within a
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`computer that executes a computer program’s instructions. EX1006 ¶68. CPUs
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`perform basic arithmetic, logic, control, and input/output functions specified by the
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`instructions in the program. Id. The basic components include an arithmetic logic
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`unit (ALU) for computation, a set of processor registers that supply operands to the
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`ALU and store the results before they are written back to memory, and a control
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`unit that orchestrates the fetching of instructions from a software application
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`(computer program) stored in memory and execution of those instructions in the
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`processor’s computational units. Id. Each software application includes algorithms
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`that, when executed by a processor, interact to implement a certain set of computer
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`functions and operations. See id.; EX1001 6:32-35.
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`Most modern architectures include a memory hierarchy for improving
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`memory bandwidth. EX1006 ¶69. Each memory in a system can be viewed as part
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`of a hierarchy that varies in size and speed. Memories closer to the processor are
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`smaller with faster access times by the CPU (e.g., processor registers and cache
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`memories), whereas memories further away from the processor are larger with
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`slower access (e.g., processor main memory or hard disk storag