UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION and XILINX, INC.,
`Petitioners
`v.
`FG SRC LLC
`Patent Owner
`____________
`
`Case IPR2020-01449
`U.S. Patent No. 7,149,867
`
`PETITIONERS’ DEMONSTRATIVE EXHIBITS
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Intel Exhibit 1047 - 1
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION and XILINX, INC.,
`Petitioners
`v.
`FG SRC LLC
`Patent Owner
`____________
`
`Case IPR2020-01449
`U.S. Patent No. 7,149,867
`
`PETITIONERS’ DEMONSTRATIVE EXHIBITS
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Intel Exhibit 1047 - 1
`
`
`
`IPR2020-01449 – Pat. No. 7,149,867
`
`• Overview of ’867 patent & asserted art
`• Disputed issues
`•
`Zhang, Gupta, Chien are prior art
`•
`PO’s constructions for the “only” limitations
`•
`Instituted combination discloses each limitation
`•
`Secondary considerations
`• PO’s Revised Motion to Amend
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`2
`
`Intel Exhibit 1047 - 2
`
`
`
`Overview: The ’867 Patent
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 13
`
`3
`
`Intel Exhibit 1047 - 3
`
`
`
`Overview: The ’867 Patent
` Key elements:
`• Reconfigurable processor that
`instantiates an algorithm as hardware
`• One or more memories
`• Data prefetch unit that
`• retrieves (reads/writes/transfers) “only”
`computational data
`• “configured to conform” to algorithm
`• operates independent of and in parallel
`with computational unit / logic blocks
`using computational data
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`4
`
`Intel Exhibit 1047 - 4
`
`
`
`Overview: The ’867 Patent
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`5
`
`Intel Exhibit 1047 - 5
`
`
`
`Overview: The ’867 Patent
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`6
`
`Intel Exhibit 1047 - 6
`
`
`
`Overview: The ’867 Patent
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`7
`
`Intel Exhibit 1047 - 7
`
`
`
`Overview: The ’867 Patent
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`8
`
`Intel Exhibit 1047 - 8
`
`
`
`Overview: Zhang
`
` “Architectural Adaptation for Application-
`Specific Locality Optimizations”
`• By Zhang, Dasdan, Schulz, Gupta, Chien
`• Presented at conference & published by IEEE in 1997
`• Available on IEEE Explore in 2002
`• MORPH project (MultiprocessOr with Reconfigurable
`Parallel Hardware)
`• Reconfigurable processor with first and second
`memories and data prefetch unit configured to
`retrieve only data required for computations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 17–19
`
`9
`
`Intel Exhibit 1047 - 9
`
`
`
`Overview: Zhang
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 17–19
`
`10
`
`Intel Exhibit 1047 - 10
`
`
`
`Overview: Zhang
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 17–19
`
`11
`
`Intel Exhibit 1047 - 11
`
`
`
`Overview: Gupta
`
` “Architectural Adaptation in AMRM
`Machines”
`• By Gupta
`• Presented at conference & published by IEEE in 2000
`• Available on IEEE Explore in 2002
`• Prototype implementation of Zhang’s MORPH
`architecture and data prefetching technique
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 19–21
`
`12
`
`Intel Exhibit 1047 - 12
`
`
`
`Overview: Gupta
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 19–21
`
`13
`
`Intel Exhibit 1047 - 13
`
`
`
`Overview: Chien
`
` “MORPH: A System Architecture for Robust
`High Performance Using Customization”
`• By Chien and Gupta
`• Presented at conference & published by IEEE in 1996
`• Available on IEEE Explore in 2002
`• Also relates to MORPH project
`• Discloses configuration using global shared memory
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 21–22
`
`14
`
`Intel Exhibit 1047 - 14
`
`
`
`Overview: Chien
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petition, Paper 1 at 21–22
`
`15
`
`Intel Exhibit 1047 - 15
`
`
`
`Overview: Institution Decision
`
` Adopted agreed constructions:
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Institution, Paper 13 at 23–26
`
`16
`
`Intel Exhibit 1047 - 16
`
`
`
`Overview: Institution Decision
`
` Instituted grounds:
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Institution, Paper 13 at 73–74
`
`17
`
`Intel Exhibit 1047 - 17
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`18
`
`Intel Exhibit 1047 - 18
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`19
`
`Intel Exhibit 1047 - 19
`
`
`
`Zhang, Gupta, Chien are prior art
` Weight of evidence shows publication before 2003 critical date
`
`Reference
`
`Zhang
`
`Gupta
`
`Chien
`
`Availability
`• Conference: by October 15, 1997
`• Library: shortly after November 18, 1997
`• IEEE Xplore: August 6, 2002
`
`• Conference: by April 28, 2000
`• Library: shortly after May 15, 2000
`• IEEE Xplore: August 6, 2002
`• Conference: by October 31, 1996
`• Library: shortly after November 18, 1996
`• IEEE Xplore: August 6, 2002
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 4–8; see also Petition, Paper 1 at 17–21
`
`20
`
`Intel Exhibit 1047 - 20
`
`
`
`Zhang, Gupta, Chien are prior art
` Institution: Undisputed available on Xplore; develop if still challenged
` Sufficient evidence at Institution
`• Indicia of publication & accessibility
`• Availability on IEEE’s Xplore
`• Cataloguing in various libraries
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Inst. 43–44
`Institution 43–44; see also Petition, Paper 1 at 17–21
`
`21
`
`Intel Exhibit 1047 - 21
`
`
`
`Zhang, Gupta, Chien are prior art
` Supplemental information further establishes publication in 2003
` Supplemental information:
`• Author Dr. Gupta confirms conference
`distribution on personal knowledge
`EX1030 ¶¶ 4–5, 7–8, 10–11
`• IEEE’s witness testimony and business
`records on conference distribution &
`availability on Xplore
`EX1027 ¶ 9–13
`• Expert testimony with additional
`evidence on hardcopies from libraries
`and Xplore’s index/search in 2002
`EX1031 ¶¶ 16, 78; id. -178 (Federal Register notice on
`examiner resources); -207-11 (news articles in 2002 on
`Xplore)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 4–8
`
`22
`
`Intel Exhibit 1047 - 22
`
`
`
`Zhang, Gupta, Chien are prior art
` PO ignores Institution & supplemental info; does not dispute
` PO’s Response identical to POPR
`despite Institution & supplemental
`information
` Does not dispute availability on
`Xplore; disputes only whether
`indexed
`• Indexing is not required
`Voter Verified, Inc. v. Premier Election Sols. Inc., 698 F.3d 1374, 380 (Fed. Cir. 2012)
`• Evidence shows Xplore was indexed
`and searchable at the time
`EX1031 ¶¶ 16, 78; id. -178 (Federal Register notice on
`examiner resources); -207-11 (news articles in 2002 on
`Xplore)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 7–8
`
`PO’s Resp. 21, 25 (same statements); see also Inst. 43 (quoting
`same statements in POPR 28, 31).
`
`23
`
`Intel Exhibit 1047 - 23
`
`
`
`Zhang, Gupta, Chien are prior art
` Multiple indicia of publication
` Copyright date
` ISBN Number
` Established publisher (IEEE)
` IEEE Order Plan Catalog Number
` Instructions for ordering copies
` Price
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5
`
`24
`
`Intel Exhibit 1047 - 24
`
`
`
`Zhang, Gupta, Chien are prior art
` Multiple indicia of publication
` Copyright date
` ISBN Number
` Established publisher (IEEE)
` IEEE Order Plan Catalog Number
` Instructions for ordering copies
` Price
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5
`
`25
`
`Intel Exhibit 1047 - 25
`
`
`
`Zhang, Gupta, Chien are prior art
` Multiple indicia of publication
` Copyright date
` ISBN Number
` Established publisher (IEEE)
` IEEE Order Plan Catalog Number
` Instructions for ordering copies
` Price
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5
`
`26
`
`Intel Exhibit 1047 - 26
`
`
`
`Zhang, Gupta, Chien are prior art
` Each was presented and distributed at IEEE conference
` Zhang at International Conference on
`Computer Design - VLSI in Computers
`and Processors in Oct. 1997 (Austin)
` Distribution confirmed by:
`• Author Dr. Gupta’s personal knowledge
`EX1030 ¶¶ 7–8
`• Sponsor IEEE’s corroborating testimony
`EX1027 ¶ 11
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5
`
`27
`
`EX1003-2
`
`Intel Exhibit 1047 - 27
`
`
`
`Zhang, Gupta, Chien are prior art
` Each was presented and distributed at IEEE conference
` Gupta at IEEE Computer Society Workshop
`on VLSI 2000 – System Design for a
`System-on-Chip Era in April 2000 (Orlando)
` Distribution confirmed by:
`• Author Dr. Gupta’s personal knowledge
`EX1030 ¶¶ 4–5
`• Sponsor IEEE’s corroborating testimony
`EX1027 ¶ 12
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5
`
`28
`
`EX1004-4
`
`Intel Exhibit 1047 - 28
`
`
`
`Zhang, Gupta, Chien are prior art
` Each was presented and distributed at IEEE conference
` Chien at Frontiers ’96 – The Sixth
`Symposium on the Frontiers of Massively
`Parallel Computing in Oct. 1996 (Annapolis)
` Distribution confirmed by:
`• Author Dr. Gupta’s personal knowledge
`EX1030 ¶¶ 10–11
`• Sponsor IEEE’s corroborating testimony
`EX1027 ¶ 13
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5
`
`29
`
`EX1005-2
`
`Intel Exhibit 1047 - 29
`
`
`
`Zhang, Gupta, Chien are prior art
` Each was publicly available in libraries
` Confirmed by:
`• Machine-Readable Cataloging (MARC)
`records
`• Hard copies from libraries
`• Unrebutted expert testimony on
`shelving practices and comparison
`across multiple physical copies and
`MARC records from numerous libraries
`EX1031 ¶ 14
`
` Zhang: shortly after Nov. 18, 1997
`
`EX1031 ¶ 34
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5–7; see also Petition, Paper 1 at 17
`
`30
`
`Intel Exhibit 1047 - 30
`
`
`
`Zhang, Gupta, Chien are prior art
` Each was publicly available in libraries
` Confirmed by:
`• Machine-Readable Cataloging (MARC)
`records
`• Hard copies from libraries
`• Unrebutted expert testimony on
`shelving practices and comparison
`across multiple physical copies and
`MARC records from numerous libraries
`EX1031 ¶ 14
`
` Gupta: shortly after May 15, 2000
`
`EX1031 ¶ 51
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5–7; see also Petition, Paper 1 at 19
`
`31
`
`Intel Exhibit 1047 - 31
`
`
`
`Zhang, Gupta, Chien are prior art
` Each was publicly available in libraries
` Confirmed by:
`• Machine-Readable Cataloging (MARC)
`records
`• Hard copies from libraries
`• Unrebutted expert testimony on
`shelving practices and comparison
`across multiple physical copies and
`MARC records from numerous libraries
`EX1031 ¶ 14
`
` Chien: shortly after Nov. 18, 1996
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 5–7; see also Petition, Paper 1 at 21
`
`EX1031 ¶ 69
`
`32
`
`Intel Exhibit 1047 - 32
`
`
`
`Zhang, Gupta, Chien are prior art
` Each was publicly available on IEEE Xplore
` IEEE testimony and business
`records show availability through
`Xplore starting August 6, 2002
`EX1027 ¶¶ 6–7, 10
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 7–8
`
`EX1027-6
`
`EX1027-16
`
`EX1027-24
`
`33
`
`Intel Exhibit 1047 - 33
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`34
`
`Intel Exhibit 1047 - 34
`
`
`
`PO’s constructions are irrelevant and not supported
` Designed to fix a failed infringement theory
` Argued for same
`constructions in district
`court to expand what
`data prefetch unit can
`retrieve
`EX1038 8-15
`• Court rejected those
`arguments and confirmed
`DPU cannot retrieve any
`other data or instructions
`
`EX1033-2
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 3
`
`35
`
`Intel Exhibit 1047 - 35
`
`
`
`PO’s constructions are irrelevant and not supported
` Designed to fix a failed infringement theory
` PO dismissed suit and
`confirmed no infringement
`unless constructions are
`changed or claims are amended
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 3
`
`36
`
`EX1036-1; see also EX1035-1
`
`Intel Exhibit 1047 - 36
`
`
`
`PO’s constructions are irrelevant and not supported
` Not used to overcome prior art
` PO recites same constructions for
`“only” limitation
`Resp. 31–33
`• But PO’s analysis does not hinge on
`construction
`Resp. 40–44
` PO’s expert does not even recite
`(let alone rely) on PO’s construction
` Need only construe terms to extent
`necessary to resolve controversy
`Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co.,
`868 F.3d 1013, 1017 (Fed. Cir. 2017)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 2–3
`
`37
`
`EX1044 107:19-108:7; see also id. 28:18-29:5, 32:10-14
`
`Intel Exhibit 1047 - 37
`
`
`
`PO’s constructions are irrelevant and not supported
` Not supported by intrinsic evidence
` Disclosure teaches retrieving only
`requested data and not any other
`data or instruction
`• Not index array
`
`EX1001 Fig. 13 & 9:27-40
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 3–4
`
`38
`
`Intel Exhibit 1047 - 38
`
`
`
`PO’s constructions are irrelevant and not supported
` Not supported by intrinsic evidence
` Disclosure teaches retrieving only
`requested data and not any other
`data or instruction
`• Not instruction traffic
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 3–4
`
`EX1017-4
`
`EX1017-5
`
`39
`
`Intel Exhibit 1047 - 39
`
`
`
`PO’s constructions are irrelevant and not supported
` Not supported by intrinsic evidence
` Disclosure teaches retrieving only
`requested data and not any other
`data or instruction
`• Not configuration/instantiation
`information
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 3–4
`
`EX1002-185
`
`40
`
`Intel Exhibit 1047 - 40
`
`
`
`PO’s constructions are irrelevant and not supported
` Not supported by intrinsic evidence
` Disclosure teaches retrieving only
`requested data and not any other
`data or instruction
`• Not configuration/instantiation
`information
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 3–4
`
`EX1002 197–99
`
`41
`
`Intel Exhibit 1047 - 41
`
`
`
`PO’s constructions are irrelevant and not supported
` Not supported by intrinsic evidence
` Disclosure teaches retrieving only
`requested data and not any other
`data or instruction
`• Not configuration/instantiation
`information
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 3–4
`
`EX1002 197–99
`
`42
`
`Intel Exhibit 1047 - 42
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`43
`
`Intel Exhibit 1047 - 43
`
`
`
`Combination teaches a “reconfigurable processor”
` PO’s requirements ≠ claim scope or agreed construction
` PO’s requirements are not in the claims or the
`agreed construction
`• “fully” reconfigurable processor
`• “replace” a microprocessor
`• Instantiate “entire” algorithm
` Agreed construction requires:
`• Computing device
`• Contains reconfigurable components
`• Instantiates an algorithm as hardware
`
`PO’s Resp. 6, 12, 16–17, 34–37
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 10–11
`
`44
`
`Inst. 48
`
`Intel Exhibit 1047 - 44
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang’s processor is reconfigurable, not “static” or “conventional”
` Zhang’s reconfigurable processor (pink)
`includes reconfigurable components
`• And PO’s expert agrees:
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1044 84:3–19
`Petitioner’s Reply, Paper 40 at 10–16; see, e.g., Petition, Paper 1 at 17–
`18, 25–26, 28–30
`
`EX. 1003 Fig. 2
`
`45
`
`Intel Exhibit 1047 - 45
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang’s processor is reconfigurable, not “static” or “conventional”
` Zhang also confirms its processing elements
`are reconfigurable
`
`EX1003-13 C2:44-49; see also EX1006¶¶ 128-131
`
`EX. 1003 Fig. 2
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 10–16; see, e.g., Petition, Paper 1 at 28–30
`
`46
`
`Intel Exhibit 1047 - 46
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang’s processor is reconfigurable, not “static” or “conventional”
` Zhang also confirms its processing elements
`are reconfigurable
`
`EX1003-14 C1:44-52; see also EX1006¶¶ 128-131
`
`EX. 1003 Fig. 2
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 10–16; see, e.g., Petition, Paper 1 at 28–30
`
`47
`
`Intel Exhibit 1047 - 47
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang’s processor is reconfigurable, not “static” or “conventional”
` PO’s expert concedes: Zhang discloses
`reconfigurable processing elements, not
`merely interface to the processor
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1044 81:6-19
`Petitioner’s Reply, Paper 40 at 10–16
`
`EX1044 82:2-16
`
`48
`
`Intel Exhibit 1047 - 48
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang’s processor instantiates an algorithm as hardware
` Reconfigurability allows application-
`specific customization of processing
`elements to optimize computations
`• I.e., instantiates an algorithm as hardware
`
`EX1003-13 C2:44-49
`
`EX1003-12 C1:28-31, C2:39-45
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 10–16; Petition, Paper 1 at
`28–31, 42–43, 46–49, 51–53, 58–59, 64, 67–69, 84–85
`
`49
`
`Intel Exhibit 1047 - 49
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang does not teach away from instantiation
` PO contends Zhang “teaches away” from
`instantiating any part of the application’s
`algorithms by stating that “the entire
`application remains in software”
`• Argument relates to purported non-disclosure,
`not criticism of modifying a reference
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 8–9, 10–16
`
`PO’s Resp. 35
`
`50
`
`Intel Exhibit 1047 - 50
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang does not teach away from instantiation
` Zhang’s statement refers to application
`remaining in software, preserves usability
`• Does not preclude instantiating an algorithm
`• Neither PO nor its expert explain why an
`application remaining in software precludes
`instantiating an algorithm as hardware
`• Zhang teaches both maintaining application in
`software and reconfiguring hardware to match
`an application
` Application remaining in software is
`entirely consistent with the ’867 patent …
`
`EX1003-14 C1:31-35
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 8–9, 13–16
`
`Institution 49
`
`51
`
`Intel Exhibit 1047 - 51
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang does not teach away from instantiation
` Zhang teaches both maintaining
`application in software and reconfiguring
`hardware to match an application
`
`EX1003-12 C1:23-28; see also id. C1:47-C2:36
`
`EX1003-13 C2:44-53, -14 C1:1-2
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 8–9, 13–16
`
`52
`
`Intel Exhibit 1047 - 52
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang does not teach away from instantiation
` Application remaining in software is
`consistent with the ’867 patent
`• As PO’s expert admits, application “carve-
`outs” get compiled into DEL that is loaded
`into reconfigurable processor . . .
`
`EX1001 6:47-57
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 8–9, 10–16
`
`EX1044 53:4-9, 54:11-22
`
`53
`
`Intel Exhibit 1047 - 53
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang does not teach away from instantiation
` Application remaining in software is
`consistent with the ’867 patent
`• “carve-outs” get compiled into DEL that is
`loaded into reconfigurable processor . . .
`• But the software is not removed or deleted
`after compilation
`• Software application remains in memory
`
`EX1044 57:24-58:19
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 8–9, 10–16
`
`EX1044 60:25-61:9
`
`54
`
`Intel Exhibit 1047 - 54
`
`
`
`Combination teaches a “reconfigurable processor”
` Zhang matches per application, not application-class
` Repeatedly references “match an application” “application-specific” and
`improvements “on a per application basis”
`
`EX1003-12
`
`EX1003-12
`
`EX1003-13 to -14
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 13–16
`
`55
`
`Intel Exhibit 1047 - 55
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`56
`
`Intel Exhibit 1047 - 56
`
`
`
`Combination teaches a “data prefetch unit”
` PO’s requirements ≠ claim scope or agreed construction
` PO’s requirements are not in the claims or
`the agreed construction
`• Preclude prefetch after a read miss
`• Always moving data before needed
`• Intentionally moving data before needed
` Agreed construction requires
`• Functional unit
`• Moves data between members of a memory
`hierarchy
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 16–18
`
`PO’s Resp. 39–40
`
`Institution 52
`
`57
`
`Intel Exhibit 1047 - 57
`
`
`
`Combination teaches a “data prefetch unit”
` Combination’s prefetcher does prefetch before needed
` PO’s “read miss” quotes are
`from 1st case study
`
`PO’s Resp. 38–39
`
`EX1003-15 C1:30-C52
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 16–18
`
`58
`
`Intel Exhibit 1047 - 58
`
`
`
`Combination teaches a “data prefetch unit”
` Combination’s prefetcher does prefetch before needed
` PO ignores Zhang’s 2nd case study (used for
`combination)
`• Prefetches by packing/gathering only used fields and
`forwarding directly to cache
`• Not based on read miss
`• Sends only what will be used “during a given
`computation” not speculative
`
`EX1003-16 C1:34-44
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 16–18 ; see, e.g., Petition, Paper 1 at 32–40,
`49–53
`
`59
`
`Intel Exhibit 1047 - 59
`
`
`
`Combination teaches a “data prefetch unit”
` Combination’s prefetcher does prefetch before needed
` But even the 1st case study is prefetching
`• Zhang & Gupta repeatedly refer to “prefetching,”
`“prefetcher” and “prefetch unit
`EX1003 15–17; EX1004 9–11
`• Prefetching was known since 1960s
`EX1016 at 16; EX1044 63:23-64:11
`• PO’s expert agreed that prefetching “all fields” or
`“likely to be traversed” is before needed
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX1044 101:3-19; see also id. 96:12-25, 98:17-99:3
`Petitioner’s Reply, Paper 40 at 16–18
`
`60
`
`Inst. 53
`
`Intel Exhibit 1047 - 60
`
`
`
`Combination teaches a “data prefetch unit”
` PO’s requirements ≠ claim scope or agreed construction
` Even the patent does not require always
`before needed
`• Patent describes data prefetch unit that operates
`after it is needed for computational logic (and PO’s
`expert agrees)
`
`EX1001 7:36–41
`
`EX1044 64:12–67:3
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 16–18
`
`61
`
`Intel Exhibit 1047 - 61
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`62
`
`Intel Exhibit 1047 - 62
`
`
`
`Combination teaches the “only” limitations
` PO’s requirements ≠ claim scope or agreed construction
` PO’s requirements are not in the claims
`• “ensures” that only computational data is retrieved
`• Be “adapted to purposefully load” only computational
`data
` Claim language requires data prefetch unit to
`retrieve (or read/write or transfer) only
`computational data required by algorithm
`
`PO’s Resp. 40–41
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 18–21
`
`63
`
`Inst. 56–57
`
`Intel Exhibit 1047 - 63
`
`
`
`Combination teaches the “only” limitations
` Zhang discloses retrieving only used fields during a given computation
` Zhang’s 2nd case study prefetches “only used
`fields during a given computation”
`
`EX1003-16 C1:25-39
`
`EX1003 Fig. 5
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 18–21; Petition, Paper 1 at Pet. 39–
`40, 49–53, 73
`
`64
`
`Intel Exhibit 1047 - 64
`
`
`
`Combination teaches the “only” limitations
` PO’s “last cache line” argument fails because Zhang teaches otherwise
` PO’s expert speculates that Zhang could retrieve
`entire cache line that is likely filled with extra data
`EX2028 ¶ 74; EX1044 109:5-110:23, 115:5-14
` NO. Zhang’s 2nd case study retrieves only used
`fields (not entire line) and places fields into a split
`cache for prefetched elements only
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`See also EX1004-9 C2:1-9 (prefetch hardware “works well with
`EX1003-16 C1:35-44
`data structures that do not quite fit into a single cache line”)
`Petitioner’s Reply, Paper 40 at 18–21; Petition,
`Paper 1 at 39–41, 51–53, 75–76
`
`65
`
`EX1003 Fig. 5
`
`Intel Exhibit 1047 - 65
`
`
`
`Combination teaches the “only” limitations
` PO’s “last cache line” argument fails because Zhang teaches otherwise
` Prefetching of “whole rows or columns” refers to
`the computational data inputs for sparse matrix
`multiplication, not cache lines.
`
`EX1003-16 C1:35-44
`
`See also EX1004-9 C2:1-9 (prefetch hardware “works well with
`data structures that do not quite fit into a single cache line”)
`
`EX1003 Fig. 5
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 18–21; Petition,
`Paper 1 at 39–41, 51–53, 75–76
`
`66
`
`Intel Exhibit 1047 - 66
`
`
`
`Combination teaches the “only” limitations
` PO’s “last cache line” argument fails because Zhang teaches otherwise
` PO’s expert speculates that Zhang could retrieve
`entire cache line that is likely filled with extra data
`EX2028 ¶ 74; EX1044 109:5-110:23, 115:5-14
`• PO’s expert admits that his opinion directly conflicts with
`Zhang’s express statements
`
`EX1044-121
`
`EX1003-16 C1:34-44 & Fig. 5
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`See also EX1004-9 C2:1-9 (prefetch hardware “works well with
`data structures that do not quite fit into a single cache line”)
`Petitioner’s Reply, Paper 40 at 18–21
`
`67
`
`Intel Exhibit 1047 - 67
`
`
`
`PO’s constructions not used and not supported
` PO mischaracterizes Petitioner’s expert on “last cache line”
` Dr. Shanfield confirms Zhang’s
`second case study uses adjustable
`cache line sizes
`
`EX2029 219:6–11
`
`EX2029 210:11–15
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 20–21
`
`EX2029 225:7–16
`
`68
`
`Intel Exhibit 1047 - 68
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`69
`
`Intel Exhibit 1047 - 69
`
`
`
`Combination teaches “configured to conform” limitations
` PO’s requirements ≠ claim scope or agreed construction
` PO’s requirements are not in the claims
`• match the “exact” needs of the algorithm
`• be configured “as multiple FIFO streams of the
`required width and depth in close proximity to
`multiple computational units”
`
`PO’s Resp. 44-45, 49
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 21–24
`
`70
`
`Inst. 60
`
`Intel Exhibit 1047 - 70
`
`
`
`Combination teaches “configured to conform” limitations
` Zhang’s first memory (L1 cache) is reconfigurable, not “fixed”
` Zhang integrates programmable logic into
`“memory components” (including L1
`cache) to match an application
`• Prefetched data placed in split cache with
`application-specific management policy
`
`EX1003-14 C1:28-30
`See also id.-17 C2:48-51, -18 C1:5-8, Fig 2
`
`EX1003-15 C2:4-5 & Fig. 4
`
`EX1003-15 C2:4-5 & Fig. 4
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 21–24; Petition, Paper 1 at 46–49
`
`71
`
`Intel Exhibit 1047 - 71
`
`
`
`Combination teaches “configured to conform” limitations
` Zhang’s first memory (L1 cache) is reconfigurable, not “fixed”
` Zhang integrates programmable logic into
`“memory components” (including L1
`cache) to match an application
`• Prefetched data placed in split cache with
`application-specific management policy
`• PO’s expert concedes programmable logic is
`integrated into memory components
`themselves, not “separate from the conventional
`memory” as PO contends.
`PO’s Sur-Reply at 9.
`
`EX1003-14 C1:28-30
`See also id.-17 C2:48-51, -18 C1:5-8, Fig 2
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 21–24; Petition, Paper 1 at 30–31, 46–49
`
`72
`
`EX1044 79:15-20
`
`Intel Exhibit 1047 - 72
`
`
`
`Combination teaches “configured to conform” limitations
` Gupta’s L1 cache is also reconfigurable, not fixed
` Gupta likewise teaches “dynamic” cache
`structures and configurability of the cache
`• Gupta’s L1 cache is implemented in FPGA0
`
`EX1004-9 C2:35-37 & Fig. 1
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 21–24; Petition, Paper 1 at 34, 47–49
`
`73
`
`Intel Exhibit 1047 - 73
`
`
`
`Combination teaches “configured to conform” limitations
` Zhang’s cache size matches application, not limited to 32 or 64 bytes
` Table 1 shows simulation parameters
`• Does not limit Zhang to those two sizes
` Zhang teaches using programmable logic to
`customize memory to match an application
`• Advantage of programmable logic is cache line not
`fixed, can be configured to match application
`
`EX1003-15 C1:19-20 & Table1
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`EX2029 210:11-15
`
`EX1003-14 C1:28-30; See also id.-12 C1:20-23, C2:23-26
`Petitioner’s Reply, Paper 40 at 21–24; Petition, Paper 1 at 30–31, 46–49
`
`74
`
`Intel Exhibit 1047 - 74
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary considerations
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`75
`
`Intel Exhibit 1047 - 75
`
`
`
`Combination does not lack “enabling disclosures”
` References in combination disclose and enable the claimed invention
` Under §103, reference need not be enabled; qualifies for whatever is
`disclosed therein
`Amgen Inc. v. Hoechst Marion Roussel, Inc., 314 F.3d 1313 (Fed. Cir. 2003)
` PO’s “enablement” argument ignores Gupta, which PO concedes is a
`prototype of Zhang’s teaching
`PO’s Resp. 12, 18; EX2028 ¶ 99
` Each reference was refereed and accepted for industry recognized
`conferences
`EX1039 12:18-13:3; EX1030 48, 53; EX1031 69, 71-72, 222-23
` PO itself contends technology in each was well-known
`PO’s Resp. 10–12
` Each reference’s level of disclosure at least commensurate with the
`patent’s level of disclosure
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Petitioner’s Reply, Paper 40 at 9; Petition, Paper 1 at 16–87
`
`76
`
`Intel Exhibit 1047 - 76
`
`
`
`Disputed Issues
`
`3.
`
`1. Zhang, Gupta, Chien are prior art
`2. PO’s constructions for “only” limitations are
`irrelevant, not supported, and can be ignored
`Instituted combination:
`A.
`teaches a “reconfigurable processor”
`B.
`teaches a “data prefetch unit”
`C.
`teaches the “only” limitations
`D.
`teaches the “configured to conform” limitations
`E. does not lack enabling disclosures
`4. PO fails to establish secondary con
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
