1111111111111111 IIIIII IIIII 11111 1111111111 11111 111111111111111 IIIII IIIII 1111111111 11111111
`US 20030046530Al
`
`(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2003/0046530 Al
`Mar. 6, 2003
`Poznanovic
`(43) Pub. Date:
`
`(54)
`
`INTERFACE FOR INTEGRATING
`RECONFIGURABLE PROCESSORS INTO A
`GENERAL PURPOSE COMPUTING SYSTEM
`
`(76)
`
`Inventor: Daniel Poznanovic, Colorado Springs,
`CO (US)
`
`Correspondence Address:
`HOGAN & HARTSON LLP
`ONE TABOR CENTER, SUITE 1500
`1200 SEVENTEENTH ST
`DENVER, CO 80202 (US)
`
`(21)
`
`Appl. No.:
`
`10/011,835
`
`(22)
`
`Filed:
`
`Dec. 5, 2001
`
`Related U.S. Application Data
`
`(60)
`
`Provisional application No. 60/286,979, filed on Apr.
`30, 2001.
`
`Publication Classification
`
`Int. Cl.7 ................................ G06F 1/24; G06F 9/00
`(51)
`(52) U.S. Cl. .............................................................. 713/100
`
`(57)
`
`ABSTRACT
`
`The present invention describes a method and system for an
`interface for integrating reconfigurable processors into a
`general purpose computing system. In particular, the system
`resides in a computer system containing standard instruction
`processors, as well as reconfigurable processors. The inter(cid:173)
`face
`includes a command processor, a command list
`memory, various registers, a direct memory access engine, a
`translation look-aside buffer, a dedicated section of common
`memory, and a dedicated memory. The interface is con(cid:173)
`trolled via commands from a command list that is created
`during compilation of a user application, or various direct
`commands.
`
`40
`
`42
`
`43
`
`44
`
`45
`
`46
`47
`48
`
`1----------------------
`: j - - - - - - - -~ 5 2
`(
`
`Control Chip
`
`50
`
`Command Processor
`
`Comlist Memory
`
`DMA Controller
`
`Translation
`Look-Aside Buffer
`
`Data Registers
`Flag Registers
`User Data Registers
`
`User Logic 1
`
`_______________ 1 _________ '
`
`12
`
`On-Board Memory
`
`I
`I
`I
`:
`I
`
`I
`I
`~ 54
`
`User Array
`
`.r; 66 ---
`
`User Logic 2
`
`60 J~-6-2-, --t----rr----6-22___Jt-_ _ _J
`
`~---------------------------
`
`Intel Exhibit 1046 - 1
`
`

`

`Patent Application Publication
`
`Mar.6,2003 Sheet 1 of 6
`
`US 2003/0046530 Al
`
`100
`
`1QQ0A
`
`1000B y
`
`140
`'---._
`
`200
`~
`
`Mux
`
`1100
`
`Processor Boar
`
`280
`_/
`
`110
`
`Micro
`Processor
`
`Micro
`Processor
`
`Bndge
`
`l
`
`Reconfigurable
`Processor
`(MAP)
`
`~--P'----'r=ocessor Board
`
`Micro
`Processor
`
`Micro
`Processor
`
`Reconfigurable
`Processor
`MAP
`
`16
`~
`
`220
`~
`
`18
`
`~ n
`
`26
`
`C
`r
`0
`s
`s
`b
`a
`
`C
`0
`m
`m
`0
`n
`
`M
`e
`m
`0
`r
`y
`
`Figure 1
`
`Intel Exhibit 1046 - 2
`
`

`

`Patent Application Publication Mar. 6, 2003 Sheet 2 of 6
`
`US 2003/0046530 Al
`
`50
`401:----------------------
`1 , - - - - - - - - - - - - - 52
`
`12
`_______________ ( _________ ,
`
`42
`
`43
`44
`
`45
`
`46
`47
`48
`
`Control Chip
`
`Command Processor
`
`Comlist Memory
`
`DMA Controller
`
`Translation
`Look-Aside Buffer
`
`Data Registers
`Flag Registers
`User Data Registers
`
`On-Board Memory
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`~ 54
`
`Jr 66
`~ ....
`
`~
`
`,------.f..--~--....L-~L_-L-~ I I
`User Array
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`User Logic 1
`
`User Logic 2
`
`60 j'----62-1--t----rr--6-2-2-1----
`
`______________ ..,,
`
`~---------------
`
`Figure 2
`
`Intel Exhibit 1046 - 3
`
`

`

`Patent Application Publication Mar. 6, 2003 Sheet 3 of 6
`
`US 2003/0046530 Al
`
`Begin MAP Halt
`
`200
`
`~ - - - - - - ' - - - - -~~
`
`Control Logic Stops Processing
`
`Control state saved in on-board memory
`
`220
`
`~ - - - - -~
`
`Status saved in Status and Control area
`
`Translation Look-aside Buffer stored in memory
`
`240
`~
`
`Direct Stop Command
`Received?
`
`250
`
`252
`
`No
`
`Interrupts enabled?
`
`No-
`
`Abandon Current
`Command/
`Continue
`
`I Execution of next
`
`command
`
`Yes
`
`242
`
`Yes
`
`Map
`Halts
`
`Send interrupt
`
`l
`
`MAP Halts
`
`260
`
`~
`I 270
`
`------<
`
`Figure 3
`
`Intel Exhibit 1046 - 4
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 4 of 6
`
`US 2003/0046530 Al
`
`Begin Execution
`
`Make any required changes to parameters
`
`310
`
`320
`
`No
`
`ontinue executio
`from next
`command?
`
`330
`Continue ~
`
`execution from
`different command
`sequence?
`
`Yes
`
`312
`
`I
`I
`Yes
`
`I
`
`322
`
`Reload parameter
`data
`
`Execute Continue
`command
`
`314
`
`Execute Continue I
`from Saved
`command
`
`Load Parameters
`
`334
`
`336
`
`E,=te D,m:: (
`
`Start command
`
`'
`
`Figure 4
`
`Intel Exhibit 1046 - 5
`
`

`

`Patent Application Publication Mar. 6, 2003 Sheet 5 of 6
`
`US 2003/0046530 Al
`
`Common Memory
`
`/
`
`18
`
`~
`
`0MB
`
`70
`
`v
`
`2MB Command List Area
`
`MAP ID #1 - Comlist 0
`
`MAP ID #1 - Comlist 1
`
`MAP ID #2 - Comlist 0
`
`MAP ID #2 - Comlist 1
`...
`
`MAP ID #n - Com list 0
`
`MAP ID #n - Comlist 1
`
`MAP ID #1 - Status and Control Area (SCA)
`
`MAP ID #2 - Status and Control Area (SCA)
`
`...
`
`721A
`~
`72 1B
`
`r---,
`,.._,
`,......_,
`
`722A
`
`722B
`
`r---,
`
`,......_,
`
`80
`
`,.--,
`
`r---,
`
`,.._,
`
`4MB
`
`SCA Area
`
`MAP ID #n - Status and Control Area (SCA)
`
`~
`
`--
`
`Figure 5
`
`Intel Exhibit 1046 - 6
`
`

`

`Patent Application Publication Mar. 6, 2003 Sheet 6 of 6
`
`US 2003/0046530 Al
`
`400
`
`410
`
`11
`
`
`
`, 420
`
`Load Comlist into Comlist space of
`Common Memory
`
`Send Fetch Command
`
`I
`
`-~'-r
`-~'-r
`~---~'------l(430
`
`Fetch Comlist from Common Memory
`
`I
`
`Store Comlist in Comlist Memory
`
`I 440
`
`Yes
`
`Execute Comlist
`
`I ___ _
`
`Next Comlist available?
`
`460
`
`i
`No
`
`I
`
`Wait for Next
`command
`
`Figure 6
`
`Intel Exhibit 1046 - 7
`
`

`

`US 2003/0046530 Al
`
`Mar. 6, 2003
`
`1
`
`INTERFACE FOR INTEGRATING
`RECONFIGURABLE PROCESSORS INTO A
`GENERAL PURPOSE COMPUTING SYSTEM
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application claims the benefit of U.S. Provi(cid:173)
`sional Patent Application No. 60/286,979 filed Apr. 30,
`2001, and entitled "Delivering Acceleration: The Potential
`for Increased HPC Application Performance Using Recon(cid:173)
`figurable Logic," which is hereby incorporated by reference
`in its entirety.
`
`BACKGROUND OF THE INVENTION
`
`[0002] 1. Field of the Invention
`
`[0003] The present invention relates to a method and
`system for interfacing computer processors. In particular,
`the present invention relates to a computer system interface
`that provides for the integration of reconfigurable processors
`with instruction processors and other reconfigurable proces(cid:173)
`sors.
`
`[0004] 2. Discussion of the Related Art
`
`[0005] Typical computing systems generally include tra(cid:173)
`ditional instruction processors for processing and control(cid:173)
`ling the instructions and data flow of a typical computer
`program. Computer instructions can also be implemented
`with hardware logic. Hardware logic-implemented functions
`can greatly accelerate the processing of application algo(cid:173)
`rithms over those same algorithms implemented in software.
`Sections of code such as compute-intensive algorithms,
`and/or repetitious instructions can benefit from hardware
`implementation. Although computer instructions imple(cid:173)
`mented in hardware logic run much faster than those imple(cid:173)
`mented in software, hardware logic is much more expensive
`to design, develop, and manufacture than an average com(cid:173)
`puter application.
`
`[0006] Recently reconfigurable processors have been
`added to computer systems, allowing for the processing of
`computer software, as well as providing for the hardware
`implementation of a computer program or code segments.
`Any piece of code deemed suitable for hardware perfor(cid:173)
`mance can be segregated from an application program and
`processed by one or more reconfigurable processors. The
`remaining code, the code not converted for hardware imple(cid:173)
`mentation, is simply processed by the standard instruction
`processors.
`
`[0007]
`In such hybrid computer systems the computer
`code is divided into sections, generally during compilation.
`Depending on optimization requirements these sections of
`code can then be processed by one or more instruction
`processors, and/or one or more reconfigurable processors.
`
`[0008] Performance enhancements resulting from recon(cid:173)
`figurable computing can provide orders of magnitude
`improvements in speed for a wide variety of computing
`code. However, the coordination between the instruction
`processors, reconfigurable processors, main memory, and
`various other components can degrade these performance
`improvements. Additionally, the increased number of com(cid:173)
`ponents necessary to coordinate such a hybrid computer
`system can add significantly to the overall cost.
`
`SUMMARY OF THE INVENTION
`
`[0009] Accordingly, the present invention is directed to an
`interface for integrating reconfigurable processors with stan(cid:173)
`dard instruction processors and/or other reconfigurable pro(cid:173)
`cessors into a computer system that substantially obviates
`one or more of the problems due to limitations and disad(cid:173)
`vantages of the related art.
`
`[0010] The present invention includes an interface control
`processor, storage for the interface instructions, data regis(cid:173)
`ters, flag registers, user registers, and a direct memory access
`("DMA") processor.
`
`[0011] The reconfigurable processor interface is an active
`interface. The interface takes direction from instruction
`processors, reconfigurable processors, as well as the user
`logic within a reconfigurable processor, yet is capable of
`control and decision making on its own. This active control
`is defined through a coordinated effort of the various inter(cid:173)
`face registers, specific areas of common memory, the dedi(cid:173)
`cated reconfigurable processor memory, and the user logic of
`the reconfigurable processor with an interface control pro(cid:173)
`gram.
`
`[0012] An object of the present invention is to provide a
`mechanism by which the instruction processors communi(cid:173)
`cate and coordinate with arbitrary user logic in reconfig(cid:173)
`urable processors.
`
`[0013] Another object of the present invention is to pro(cid:173)
`vide an active control that allows instruction processors and
`reconfigurable processors to function autonomously.
`
`[0014] Another object of the present invention is to pro(cid:173)
`vide a means for moving memory contents between com(cid:173)
`mon memory and the dedicated memory of a reconfigurable
`processor.
`
`[0015] A further object of the present invention is to
`provide a flexible interface that can be defined for arbitrary
`instruction processor instruction sequences and arbitrary
`reconfigurable user logic.
`
`[0016] Another object of the present invention is to ensure
`the protected operation of the interface by ensuring that the
`memory to be referred to is only within the boundaries of a
`user program.
`
`[0017] Another object of the present invention is to pro(cid:173)
`vide interaction with a user program without requiring
`operating system services.
`
`[0018] Yet a further object of the present invention is to
`provide a means for the reconfigurable processor to interact
`with input/output services.
`
`[0019] Another object of the present invention is to divide
`application programs among instruction processors and
`reconfigurable processors to achieve optimum performance.
`
`[0020] Another object of the present invention is to allow
`a single-system image to be constructed for a hybrid system
`of instruction processors and reconfigurable processors.
`
`[0021] Another object of the present invention is to allow
`a single-system image to be constructed for a system of
`purely reconfigurable processors.
`
`Intel Exhibit 1046 - 8
`
`

`

`US 2003/0046530 Al
`
`Mar. 6, 2003
`
`2
`
`[0022] A further object of the present invention is to allow
`the construction of a cluster of Symmetric Multi-Processor
`("SMP") hybrid nodes or strictly instruction nodes, or recon(cid:173)
`figurable processor nodes, or various combinations thereof.
`
`[0023] Still a further object of the present invention is to
`allow instruction processors and reconfigurable processors
`to be integrated into a single-system image SMP architecture
`system.
`
`[0024] A further object of the present invention is to allow
`reconfigurable processors to be integrated into a single(cid:173)
`system image SMP.
`
`[0025] Another object of the present invention is to allow
`the user logic of the reconfigurable processor to coordinate
`with the rest of a single-system image SMP system.
`
`[0026] Additional features and advantages of the inven(cid:173)
`tion will be set forth in the description that follows, and in
`part will be apparent from the description, or may be learned
`by practice of the invention. The objectives and other
`advantages of the invention will be realized and attained by
`the structure particularly pointed out in the written descrip(cid:173)
`tion and claims hereof as well as the appended drawings.
`
`[0027] To achieve these and other advantages and in
`accordance with the purpose of the present invention, as
`embodied and broadly described, the interface for integrat(cid:173)
`ing reconfigurable processors into a general purpose com(cid:173)
`puting system provides the ability to coordinate the execu(cid:173)
`tion of an application that combines processor code and
`synthesized logic.
`
`[0028]
`In another aspect, the present invention provides an
`interface for integrating reconfigurable processors into a
`general purpose computing system. The interface includes:
`(1) interface control processor for managing the interaction
`between the at least one reconfigurable processor and the
`computer system; (2) interface control processor instruc(cid:173)
`tions organized into command lists; (3) random access
`memory for storing the current command list; ( 4) registers
`for storing data and settings; (5) common memory; (6) direct
`memory access logic for coordinating the transfer of the
`reconfigurable processor instructions and data; (7) address
`translation buffer for storing translation data and translating
`virtual memory addresses to physical memory addresses;
`and (8) dedicated memory.
`
`[0029]
`In a further aspect, the present invention provides
`a method for processing interface control processor instruc(cid:173)
`tions compiled from a user application. This method
`includes the steps of: (1) storing command lists in a dedi(cid:173)
`cated area of common memory, (2) receiving a fetch com(cid:173)
`mand sent by the user application; (3) fetching a command
`list from the dedicated area; (4) loading the command list
`into a command list memory within the interface; (5)
`processing the command list through an interface control
`processor; ( 6) interacting with user logic to exchange data
`and control signals, and (7) determining if another command
`list is ready for processing, if so, processing the new
`command list; otherwise, waiting for another fetch com(cid:173)
`mand.
`
`[0030]
`It is to be understood that both the foregoing
`general description and the following detailed description
`are exemplary and explanatory and are intended to provide
`further explanation of the invention as claimed.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0031] The accompanying drawings, which are included
`to provide further understanding of the invention and are
`incorporated in and constitute a part of this specification,
`illustrate embodiments of the invention and together with
`the description serve to explain the principles of the inven(cid:173)
`tion. In the drawings:
`[0032] FIG. 1 is a simplified, high level, functional block
`diagram of a multiprocessor computer architecture, includ(cid:173)
`ing reconfigurable processors.
`[0033] FIG. 2 is a representational diagram of a recon(cid:173)
`figurable processor used according to a preferred embodi(cid:173)
`ment of the present invention.
`[0034] FIG. 3 is a flow diagram of the method of halting
`the instruction processing of a reconfigurable processor.
`[0035] FIG. 4 is a flow diagram of the method of restart(cid:173)
`ing the execution of a reconfigurable processor after it has
`been halted.
`[0036] FIG. 5 is a representational diagram of a common
`memory organization according to a preferred embodiment
`of the present invention.
`[0037] FIG. 6 is a flow diagram of the method of pro(cid:173)
`cessing interface control processor instructions.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`[0038] Reference will now be made in detail to the pre(cid:173)
`ferred embodiment of the present invention, examples of
`which are illustrated in the accompanying drawings.
`[0039] The present invention integrates a computer's
`instruction processors, common memory, and reconfigurable
`processors, referred to in the preferred embodiment as
`Multi-Adaptive Processors ("MAPs"). Through the coordi(cid:173)
`nated effort of the various hardware and software compo(cid:173)
`nents of the interface with common memory, instruction
`processor, and MAPs the present invention provides for the
`interaction of instruction processors and reconfigurable pro(cid:173)
`cessors providing enhanced performance to a computer
`system.
`[0040] Referring to FIG. 1, an overview of the computer
`system incorporating MAPs 12 is shown. In the preferred
`embodiment of the present invention the instruction proces(cid:173)
`sor boards 10 and MAPs 12 reside on the trunk 20 and 22
`to the crossbar 16. The MAPs are connected via a multi(cid:173)
`plexer 14. The crossbar 16 is then connected to common
`memory 18 through memory trunk 26. Further embodiments
`of the present invention allow for placing the instruction
`processor 10 and/or the MAPs 12 in any other location,
`including, but not limited to, the memory trunk 26, crossbar
`switch 16, common memory inter-connect, or 1/0 bus 28.
`The instruction processors 100 and MAPs 12 may also be on
`the same or separate circuit boards, or even integrated on the
`same computer chip.
`[0041] Referring to FIG. 2, the reconfigurable MAP 12 is
`described in more specific detail. A MAP 12 is a standalone
`processing unit executing independently of instruction pro(cid:173)
`cessors during normal operation, as well as while loading
`and storing data. Each MAP 12 incorporates various hard(cid:173)
`ware components of the preferred embodiment of the
`
`Intel Exhibit 1046 - 9
`
`

`

`US 2003/0046530 Al
`
`Mar. 6, 2003
`
`3
`
`present invention, including for purposes of illustration only,
`an interface control processor, referred to as a command
`processor 42, command list memory 43, a direct memory
`access ("DMA") controller 44, a translation look-aside
`buffer ("TLB") 45, data registers 46, user data registers 48,
`flag registers 47, and on-board memory 50.
`
`[0042] Each MAP 12 also includes user-configured logic
`known as the user array 60. The user array of the present
`example contains two large Field Programmable Gate
`Arrays ("FPGAs"), referred to as user logic ("U _ Logic")
`62 1-62 2 . During compilation the sections of code deter(cid:173)
`mined to be suitable for optimization through a hardware
`implementation, such as discrete algorithmic sections, are
`segregated out of the program code. The algorithmic sec(cid:173)
`tions of code from the application program are converted to
`provide hardware logic circuits within the user logic 621 -
`622.
`
`[0043] Through the use of an interface control program,
`including a command list, known as the ComList, the
`command processor 42 processes commands, makes control
`decisions, and manages the transfer of data. A ComList is
`also generated during compilation of the user application. A
`ComList is used for controlling a MAP 12 or MAPs 12 1-12N
`(FIG. 1) during normal operation. The ComList contains a
`list of controlling instructions for the MAP's command
`processor 42 and is initially stored in common memory 18
`(FIG. 1) until it is fetched by the MAP's controller 40 into
`the ComList memory 43.
`
`[0044] Common memory addresses specified by com(cid:173)
`mands or generated by user applications are virtual
`addresses. Addresses are translated, virtual to physical, by
`TLB 45 entries with the DMA controller 44.
`
`[0045] Three sets of registers, data registers 46, user data
`registers 48, and flag registers 47, are also used to help
`coordinate the processing of interface instructions. Data
`registers 46 consist of thirty-two, 64-bit registers known as
`DRO through DR31. These registers are generally used to
`hold addresses for both common memory 18 (FIG. 1) and
`on-board memory 50; however, they can hold any needed
`data. By using data registers 46, scalar data can be sent to or
`received from the user array 60. Simple arithmetic opera(cid:173)
`tions, as well as bitwise logic, are supported on these
`registers. The data register contents can be tested for zero/
`non-zero; therefore, tests together with branches provide
`support for loops. For reference purposes, the bits of DRO
`are always 0/clear and the lower order bit of DRl is always
`1/set. DRO contains integer O and DRl contains integer 1.
`Neither register can be overwritten.
`
`[0046] User data registers 48 are thirty-two registers of 64
`bits known as UDRO through UDR31. User data can be sent
`directly from the ComList to the user array 60 without going
`through the data registers 46. A group of user data registers
`48 can be loaded from the ComList. When the last user data
`register of the group is loaded the user array 60 is inter(cid:173)
`rupted. The user array 60 must understand the protocol by
`which user data registers 48 need to be read.
`
`[0047] Flag registers 47 are thirty-two single-bit registers
`FRO through FR31. Commands can test and wait on the state
`of flag registers 47 before execution. Commands can change
`the state of flag registers 47, forcing them set and clear. In
`addition, there are logical instructions that allow combining
`
`flag states (AND, OR, XOR). Other commands allow testing
`and branching on their contents. For control purposes FRO
`is always 0/clear and FRl is always 1/set. Neither of these
`registers can be overwritten.
`
`[0048] The purpose of the flag registers 47 is to support
`coordination between different operations. For example, the
`user logic can coordinate loading and executing a new
`ComList by setting a specified flag register. A command can
`test the flag register and then branch to the end of the
`ComList, indicating that the next ComList may be loaded.
`As a further example, the user logic can coordinate move(cid:173)
`ment of data in or out of on-board memory 50 using flag
`registers and data registers. A DMA instruction can be held
`waiting for a flag register to be set. The user logic can write
`addresses and length into data registers, and then set a
`specified flag register, allowing the DMA instruction to
`execute the movement of data. When the DMA completes,
`another flag register can be set to indicate to the user logic
`that data movement is complete.
`[0049] An additional register visible in the MAP is the
`ComList pointer 49. This register is saved as part of the
`MAP status and indicates the index of the next command
`dispatched in the active ComList. When a MAP is halted the
`pointer indicates the next command to be executed if execu(cid:173)
`tion is restarted.
`[0050] On-board memory 50 consists of six banks of dual
`port 512Kx64-bit static random access memory ("RAM")
`providing a total of 24 MB of available memory. Both the
`DMA controller 44 and the command processor 42 commu(cid:173)
`nicate with the on-board memory 50 via the six control-side
`ports 52. The user array 60 communicates with the on-board
`memory 50 through the six user-side ports 54.
`[0051] The user array 60 portion of a MAP 12 is config(cid:173)
`ured as a hardware implementation of the algorithmic
`requirements of the user application. The user array 60 reads
`from, and writes to, on-board memory 50 through six
`user-side ports 54 and can interact with the control logic and
`the DMA controller 44.
`[0052] DMA operations within the interface of a MAP 12
`run more or less independently of processing within a user's
`logic. Coordination between these control streams is through
`the use of the flag registers 47, data registers 46 and user data
`registers 48.
`
`[0053] The DMA controller 44 is initiated by a DMA
`ComList instruction. The user array 60 writes an address and
`length into the data registers 46 and sets a flag register 47.
`The ComList awaits the user array's signal, setting of the
`flag register, and then executes a DMA instruction that
`references the data registers 46 that have been setup by the
`user array. The DMA controller 44 can then signal its
`completion by setting or clearing a flag register 47 that the
`user array is monitoring.
`[0054] The FPGAs, user logic 621 and 622 , of the user
`array 60 are configured during a fetch configuration com(cid:173)
`mand from data in common memory and not from an
`on-board programmable read only memory ("PROM"). User
`logic 621 and 622 communicate between themselves using
`three dedicated 64-bit data buses 66 without using any
`memory bandwidth. MAP modules can also be connected
`together via a chaining data bus 64. Through the use of
`chaining ports 64 a particular MAP can send partial results
`
`Intel Exhibit 1046 - 10
`
`

`

`US 2003/0046530 Al
`
`Mar. 6, 2003
`
`4
`
`to another MAP, or similarly, can receive such partial results
`from another MAP. The user array 60 provides all logic for
`the chaining ports 64. In a preferred embodiment, the
`chaining ports 64 use Double Data Rate ("DDR") protocol
`that allows each data line to carry two bits of information.
`This provides for two chain input ports and two chain output
`ports. In an alternate embodiment without a DDR protocol
`only single input and output ports would be available on
`each MAP. Chaining data flow is basically unidirectional,
`while the three onboard inter-connecting data buses 66 are
`bi-directional.
`
`[0055] Full system interrupt and semaphore capability is
`available between MAPs l2 0-l2N (FIG. 1) and/or instruc(cid:173)
`tion processors 1000 -lO0N (FIG. 1). MAPs can send inter(cid:173)
`rupts to processors and can also receive a limited set of
`commands directly
`from
`the processors. Commands
`received directly from other processors, which are not
`fetched and executed from a MAP's ComList, are called
`direct commands. Interrupts are sent by a MAP 12 to a given
`processor in a twelve bit serial stream along with twelve
`source synchronous clock pulses.
`
`[0056] FR31 provides a specific system interrupt mecha(cid:173)
`nism. When FR31 is set, MAP status is stored in its status
`and control area and an interrupt is generated. This status
`operation is conditional on an interrupt enable flag taken
`from a control word in the status and control area. In all
`cases, if FR31 sets, MAP execution attempts to halt. For this
`reason, internally 10 detected errors set FR31.
`
`[0057] A Stop switch is provided to add flexibility with
`handling interrupts sent to a MAP. During normal operation
`a MAP will run with Stop enabled. This mode allows
`execution to halt when the MAP is interrupted. However, for
`diagnostic and debugging purposes, a MAP can run in a Stop
`disabled mode, providing the MAP with the ability to
`continue execution of a program, even when it has been
`interrupted.
`
`[0058] Stopping/halting MAP execution can result from
`several sources. In all cases this requires setting or attempt(cid:173)
`ing to set FR31. When there is an attempt to set FR31 either
`directly, or indirectly, and Stop is enabled, execution of the
`MAP is halted.
`
`[0059] Referring to FIG. 3, the MAP can be interrupted in
`the following situations: (1) a direct Stop command is
`received from a processor, (2) FR31 is set from the ComList,
`(2) FR31 is set from the user logic, or ( 4) the command
`processor detects an error, such as an address exception,
`page or memory fault, or some other internal fault. Upon any
`halt or exception, with Stop enabled, the following occurs:
`MAP control logic comes to the most graceful halt it can,
`waiting for execution logic to go quiet step 200. The control
`state is saved in on-board memory addresses 0-31 step 210.
`Status is stored into the MAP's status and control area of
`common memory step 220. The MAP's TLB registers are
`stored into the TLB area step 230. If a direct stop command
`was received step 240 the MAP is stopped step 242, other(cid:173)
`wise if interrupts are enabled step 250, an interrupt is sent
`step 260 and the MAP unit halts step 270. If Stop is disabled
`step 250, the sequence above is executed except that in the
`last step the command that caused the error is abandoned and
`execution continues step 252.
`
`[0060] Referring to FIG. 4, to continue after execution
`halts the following steps are made: any necessary changes to
`the MAP's parameters in the status and control area are
`made, including the TLB entries step 300. Determine if
`processing is to continue from the interrupted command step
`310, the next command step 320, or from another command
`sequence step 330. If continuing execution of the instruction
`that caused the halt, reload all saved parameters step 312 and
`then Continue from Saved step 314. If the halt was not
`caused by an error or TLB miss (so that no instruction is
`partially executed) and the status and control parameters do
`not require changing or updating, then the direct command
`Continue can be sent to the MAP step 322. If a new sequence
`is to be started (for example, a new user or the current user
`with different commands), the proper command sequence
`must be stored in ComList step 332, then direct commands
`are made to load parameters step 334 and Start execution
`step 336.
`[0061] Referring to FIG. 5, MAPs are actively controlled
`through the interface control program. The components of
`the interface control program include a pair of ComList
`pages 72 1A-72rn located in the ComList area 70 of common
`memory 18, a status and control page 82i, located in the
`status and control area 80 in common memory 18, which
`holds status and control information and TLB data. Addi(cid:173)
`tional components, which coordinate to provide interface
`control, include the data registers 46, user data registers 48,
`flag registers 47, on-board memory 50, TLB 45 and user
`array 60.
`[0062] The MAPs interface is controlled by commands in
`the ComList or direct commands issued by an instruction
`processor or another MAP. During compilation an applica(cid:173)
`tion generates code for the standard instruction processor,
`ComLists for the MAP's interface, and hardware logic for
`the MAP's user array. ComLists are generated by the user
`application in order to coordinate data movement and con(cid:173)
`trol between the application code running in the instruction
`processor, and application logic running in the MAP's user
`array. Commands in the ComList correspond directly to
`instructions in a reduced instruction set computer ("RISC")
`processor. These instructions are a small set of simple
`instructions for moving data, testing conditions, and branch(cid:173)
`ing. FPGA control processors can be reconfigured to func(cid:173)
`tion with various instruction sets, depending upon imple(cid:173)
`mentation needs.
`[0063] Each MAP 12 (FIG. 2) is provided with two 4-KB
`ComList pages 72A and 72B from the ComList area 70 in
`common memory 18 providing a maximum useable space
`for each ComList of 512 words. Each ComList page is
`identified through a unique MAP ID number. For each MAP
`12 (FIG. 2), the address of the ComList pages 72 1A, 72rn
`through 72NA, 72NB are specified in conjunction with the ID
`number of the associated MAP 12. Starting at relative
`address OK in each MAP's ComList page 72A+B is the first
`command list, ComList072A, for that MAP. The second
`command list, ComListl 72B, is located at address 4K of that
`MAP's ComList area 72A+B· Two ComList pages 72A and
`72B are used to allow each MAP to work from one ComList
`page while the application software is loading the other
`ComList page. By swapping ComList pages the latencies of
`the processor and DMA are significantly reduced.
`[0064] The first word in each ComList is the ComList
`Length Command that defines the total number of command
`words in the buffer. For example, if there were only one
`additional command in the ComList, the first word, the
`
`Intel Exhibit 1046 - 11
`
`

`

`US 2003/0046530 Al
`
`Mar. 6, 2003
`
`5
`
`Length Command, would have the value 2. This indicates
`that the ComList contains the length command word plus
`one additional command word.
`
`[0070] According to the preferred embodiment of the
`present invention the data fields in the first 8 bytes of a
`ComList command are structured in the following manner:
`
`63
`bit
`size
`field
`width 2
`
`code
`4
`
`a
`
`b
`
`c
`
`d
`
`e
`
`aa bb
`5
`5
`
`cc dd ee
`5
`5
`5
`
`ff
`5
`
`00
`gg hh
`12 10
`
`[0065]