`
`Paper No. 36
`Filed: August 18, 2021
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`INTEL CORPORATION,
`Petitioner
`v.
`FG SRC LLC,
`Patent Owner
`____________________
`CASE NO.: IPR2020-01449
`PATENT NO. 7,149,867
`____________________
`PETITIONER’S OPPOSITION TO PATENT OWNER’S MOTION TO
`AMEND
`
`
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

`

`
`
`IPR2020-01449
`U.S. Patent No. 7,149,867
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`TABLE OF CONTENTS
`
`Page
`I. 
`INTRODUCTION ............................................................................................... 1 
`II.  BACKGROUND ON RELEVANT CLAIM CONSTRUCTION ...................... 2 
`III. ARGUMENT ....................................................................................................... 3 
`A.  Proposed substitute claim 20 should be denied ............................................. 3 
`1.  The data movement amendment enlarges the original claim
`scope ........................................................................................................ 3 
`2.  The data movement amendment does not relate to
`unpatentability ......................................................................................... 6 
`3.  Proposed claim 20 is unpatentable over the prior art .............................. 7 
`a.  The prior art discloses the data movement amendment .................... 7 
`b.  The prior art discloses the data computation amendment ................. 8 
`c.  Trimberger also discloses the data computation
`amendment ...................................................................................... 13 
`B.  Proposed substitute claim 28 should be denied ........................................... 18 
`1.  The data movement amendment enlarges the original claim
`scope ...................................................................................................... 18 
`2.  The data movement amendment does not relate to
`unpatentability ....................................................................................... 20 
`3.  The additional “wherein . . . configured” limitation is
`duplicative ............................................................................................. 20 
`4.  The proposed claim 28 is unpatentable over the prior art ..................... 20 
`a.  The prior art discloses the data movement amendment .................. 20 
`b.  The prior art discloses the “configured” amendment ..................... 21 
`c.  The prior art discloses the data computation amendment ............... 21 
`C.  Proposed substitute claim 32 should be denied ........................................... 21 
`1.  The data movement amendment enlarges the original claim
`scope ...................................................................................................... 21 
`
`2
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`IPR2020-01449
`U.S. Patent No. 7,149,867
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`2.  The data movement amendment does not relate to
`unpatentability ....................................................................................... 22 
`3.  The proposed claim 32 is unpatentable over the prior art ..................... 23 
`a.  The prior art discloses the data movement amendment .................. 23 
`b.  The prior art discloses the data computation amendment ............... 23 
`IV. CONCLUSION .................................................................................................. 24 
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`IPR2020-01449
`U.S. Patent No. 7,149,867
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`TABLE OF AUTHORITIES
`
`Page(s)
`
`
`Cases
`
`Aqua Prods., Inc. v. Matal,
`872 F.3d 1290 (Fed. Cir. 2017) ............................................................................ 3
`In re Cuozzo Speed Techs.,
`793 F.3d 1268 (Fed. Cir. 2015) ...................................................................passim
`Idle Free Sys., Inc. v. Bergstrom, Inc.,
`IPR2012-00027, Paper 26, 5 (PTAB June 11, 2013) ........................... 4, 5, 19, 22
`Koninklijke Philips N.V. v. Google LLC, et al.,
`948 F.3d 1330 (Fed. Cir. 2020), (ii) ................................................................... 11
`Lectrosonics, Inc. v. Zaxcom, Inc.,
`IPR2018-01129, Paper 15 (Feb. 25, 2019) ........................................................... 7
`Realtime Data, LLC, v. Iancu,
`912 F.3d 1368 (Fed. Cir. 2019) .......................................................................... 10
`Statutes and Codes
`
`United States Code
`Title 35 § 102(a) ................................................................................................. 13
`Title 35 § 102(b) ................................................................................................. 13
`Title 35 § 316(d) ................................................................................................... 3
`Title 35 § 316(d)(3) ................................................................................... 4, 20, 22
`Rules and Regulations
`
`Code of Federal Regulations
`Title 37 § 42.121(a)(2)(i) ...................................................................................... 6
`Title 37 § 42.121(a)(2)(ii) ............................................................................. 20, 22
`Title 37 § 42.121(d)(1) ...................................................................................... 4, 6
`
`
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`4
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`IPR2020-01449
`U.S. Patent No. 7,149,867
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`
`TABLE OF EXHIBITS
`
`Description
`Exhibit No.
`Exhibit 1001 U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June
`16, 2004, and issued on December 12, 2006 (the “’867 patent”).
`Exhibit 1002 Prosecution history of the ’867 patent.
`Exhibit 1003 X. Zhang et al., Architectural Adaptation of Application-Specific
`Locality Optimizations, IEEE (1997) (“Zhang”).
`Exhibit 1004 R. Gupta, Architectural Adaptation in AMRM Machines, IEEE
`(2000) (“Gupta”).
`Exhibit 1005 A. Chien and R. Gupta, MORPH: A System Architecture for
`Robust Higher Performance Using Customization,” IEEE (1996)
`(“Chien”).
`Exhibit 1006 Declaration of Stanley Shanfield, Ph.D.
`Exhibit 1007 RESERVED
`Exhibit 1008 RESERVED
`Exhibit 1009 RESERVED
`Exhibit 1010 Declaration of Rajesh K. Gupta
`Exhibit 1011 Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999).
`Exhibit 1012 Declaration of Jacob Munford
`Exhibit 1013 RESERVED
`Exhibit 1014 Order Governing Proceedings - Patent Case by Judge Alan D
`Albright, filed on June 30, 2020 in FG SRC LLC v. Intel
`Corporation, No. 6:20-cv-00315-ADA (W.D. Tex.)
`Exhibit 1015 Scheduling Order by Judge Alan D Albright, filed on August 1,
`2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-00315-
`ADA (W.D. Tex.)
`Exhibit 1016 Plaintiffs SRC Labs, LLC & Saint Regis Mohawk Tribe’s
`Opening Claim Construction Brief, filed on November 5, 2018 in
`SRC Labs, LLC et al. v. Amazon Web Services, Inc. et al., No.
`2:18-cv-00317-JLP (W.D. Was.)
`
`5
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`IPR2020-01449
`U.S. Patent No. 7,149,867
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`
`Description
`Exhibit No.
`Exhibit 1017 Provisional Patent Application No. 60/479,339
`Exhibit 1018 Plaintiff’s Preliminary Infringement Contentions, submitted on
`July 23, 2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-
`00315-ADA (W.D. Tex.)
`Exhibit 1019 Amended Scheduling Order by Judge Alan D Albright, filed on
`December 18, 2020 in UNM Rainforest Innovations v. Dell
`Technologies et al., No. 6:20-cv-00468-ADA (W.D. Tex.)
`Exhibit 1020 Docket Sheet from UNM Rainforest Innovations v. Dell
`Technologies et al., No. 6:20-cv-00468-ADA (W.D. Tex.)
`Exhibit 1021 Scheduling Order by Judge Alan D Albright, filed on November
`19, 2020 in Theta IP, LLC v. Samsung Electronics Co., Ltd. et al.,
`No. 6:20-cv-00160-ADA (W.D. Tex.)
`Exhibit 1022 Agreed Post-Markman Scheduling Order by Judge Alan D
`Albright, filed on December 3, 2020 in Videoshare, LLC v.
`Google LLC and Youtube, LLC, No. 6:19-cv-00663-ADA (W.D.
`Tex.)
`Exhibit 1023 Docket Sheet from H-E-B, LP v. Wadley Holdings, LLC, dba
`nICE Coolers et al., No. 6:20-cv-00081-ADA (W.D. Tex.)
`Exhibit 1024 Western District of Texas Order by Chief Judge Orlando L.
`Garcia
`regarding Court Operations Under
`the Exigent
`Circumstances Created by the COVID-19 Pandemic, filed on
`March 13, 2020 in all cases.
`Exhibit 1025 Western District of Texas Eleventh Supplemental Order by Chief
`Judge Orlando L. Garcia Regarding Court Operations Under the
`Exigent Circumstances Created by the COVID-19 Pandemic,
`filed on December 10, 2020 in all cases.
`Exhibit 1026 December 23, 2020 email from H. Santasawatkul to Counsel
`Exhibit 1027 Declaration of Gordon MacPherson
`Exhibit 1028 Declaration of Eileen D. McCarrier
`Exhibit 1029 Declaration of Austin M. Schnell
`Exhibit 1030 Supplemental Declaration of Rajesh K. Gupta, Ph.D.
`Exhibit 1031 Supplemental Declaration of Jacob Robert Munford
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`IPR2020-01449
`U.S. Patent No. 7,149,867
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`Description
`
`Exhibit No.
`Exhibit 1032 RESERVED
`Exhibit 1033 District Court Claim Construction Order
`Exhibit 1034 Declaration of Stanley Shanfield, Ph.D.
`Exhibit 1035 March 12, 2021 email from M. Shore to B. Nash
`Exhibit 1036 March 31, 2021 email from M. Shore to Court and Counsel
`Exhibit 1037 U.S. Patent No. 5,737,631 to Trimberger, filed April 5, 1995, and
`issued on April 7, 1998 (“Trimberger”).
`Exhibit 1038 Plaintiff FG SRC’s Opening Claim Construction Brief, filed on
`November 17, 2020 in FG SRC LLC v. Intel Corporation, No.
`6:20-cv-00315-ADA (W.D. Tex.)
`
`
`
`LIST OF ABBREVIATIONS
`
`Abbreviation
`Pet.
`
`PRPR
`
`Institution
`
`MTA
`
`Resp.
`
`Description
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 1, Petition
`for Inter Partes Review of U.S. Patent No. 7,149,867
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 11,
`Petitioner’s Reply to Preliminary Response
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 13, Granting
`Institution of Inter Partes Review
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 26, Patent
`Owner’s Motion to Amend
`Intel Corp. v. FG SRC LLC, IPR2020-01449, Paper 34, Patent
`Owner’s Response to Petition
`
`
`
`NOTE ON EMPHASIS: All emphasis in the brief is added unless otherwise
`indicated.
`
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`7
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`INTRODUCTION
`Patent Owner (PO) seeks a first amendment type that affects each
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`IPR2020-01449
`U.S. Patent No. 7,149,867
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`I.
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`independent claim’s restrictions on how the data prefetch unit moves data. PO
`
`characterizes the language as “simplified” or “clarified,” but for each it effectively
`
`removes a requirement of the prefetch unit’s operation from the original claim.
`
`E.g., MTA 7 (replacing “retrieves” with “transfers” in claim 1 to remove
`
`requirement that data prefetch unit “retrieves only computational data”); id. 9-10
`
`(adding “data, including computational data” in a way that removes claim 9’s
`
`restriction that the data prefetch unit read only data required for computations); id.
`
`11-12 (removing claim 13’s requirement for transfers between memory and data
`
`prefetch unit to “transfer only data necessary for computations” by adding
`
`language so this limitation applies only to one-way transfers “to the data access
`
`unit”). PO makes these changes to enlarge the claim scope because, as PO
`
`conceded in district court, Petitioner cannot infringe the claims in their present
`
`form. Thus, these amendments should be denied as improperly broadening.
`
`PO’s second amendment type adds to each claim an FPGA to either perform
`
`computations or implement the computational unit. See MTA 5, 9, 11. But adding
`
`an FPGA does not save the claims. The instituted prior art—Zhang, Gupta, and
`
`Chien—teaches a reconfigurable processor implemented using FPGA with
`
`programmable “processing elements,” e.g., EX1003-12 C2:39-45, -13 C2:44-49, -
`
`1
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`

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`17 C1:22-26 & Fig. 2, and FPGAs were widely known for use in performing
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`complex computations, like sparse matrix multiplication, to persons of ordinary
`
`skill in the art (“POSA”), EX1034 ¶12. Thus, it would have been obvious in view
`
`of the instituted art to use an FPGA to perform computations of the claimed
`
`algorithm or implement the computational unit. In addition, this same art in
`
`combination with U.S. Patent No. 5,737,631 (Trimberger) also renders these added
`
`limitations obvious. Thus, the substitute claims are unpatentable.
`
`II. BACKGROUND ON RELEVANT CLAIM CONSTRUCTION
`
`PO intends with these amendments to fix fatal flaws in its infringement
`
`theory, not to narrow its claims to overcome prior art, as demonstrated by PO’s
`
`argument in district court, the court’s claim construction order rejecting those
`
`arguments, and the statements of PO’s counsel and dismissal in response to the
`
`order. PO asserted two independent claims that each limit the type of information
`
`that the data prefetch unit either retrieves or reads and writes. Claim 1’s data
`
`prefetch unit “retrieves only computational data required by the algorithm.”
`
`EX1001 12:44-45. Similarly, claim 9’s data prefetch unit “read[s] and write[s] only
`
`data required for computations by the algorithm between the data prefetch unit and
`
`the common memory.” Id. 13:17-20. PO added these restrictions to overcome a
`
`Patent Office rejection, see EX1002 179-83 (rejection); id. 197-99 (amendment),
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`and the Examiner relied on these additions in the Notice of Allowance, see id. 231.
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`2
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`

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`In district court, PO advanced constructions that would remove those
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`expressly claimed restrictions. Specifically, PO argued that despite claim 1’s
`
`“only” limitation, the data prefetch unit may retrieve other data or instructions in
`
`addition to computational data required by the algorithm. See EX1033; EX1038 8-
`
`14. PO similarly attempted to expand claim 9 by misconstruing the “only”
`
`limitation. See EX1033; EX1038 14-15. The court rejected those arguments with
`
`constructions that afford “only” its ordinary meaning and preclude the data
`
`prefetch unit from retrieving or reading other data or instructions. EX1033.
`
`Immediately after that order, PO’s counsel stated that “at first glance [the
`
`order] does not appear consistent with [PO]’s infringement read” and “[PO] will
`
`likely seek to amend the claims in the IPR.” EX1035. PO later confirmed to the
`
`district court that “[PO] (and [Petitioner]) believe the Court’s construction
`
`precludes a finding of infringement, so there is no basis to move forward unless
`
`either the claims construction is changed or the claims are amended.” EX1036. PO
`
`subsequently dismissed its suit against Petitioner and filed this Motion to Amend.
`
`III. ARGUMENT
`
`A.
`
`Proposed substitute claim 20 should be denied
`1.
`The data movement amendment enlarges the original claim scope
`PO bears the burden to show it has satisfied 35 U.S.C. § 316(d), see Aqua
`
`Prods., Inc. v. Matal, 872 F.3d 1290, 1341 (Fed. Cir. 2017), including that an
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`amendment “may not enlarge the scope of the claims of the patent or introduce
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`new material.” 35 U.S.C. § 316(d)(3); 37 C.F.R. § 42.121(d)(1). An amendment
`
`enlarges claim scope if the amended claim (i) “is broader in any respect than the
`
`original claim, even though it may be narrowed in other respects” or (ii) “contains
`
`within its scope any conceivable apparatus or process which would not have
`
`infringed the original patent.” In re Cuozzo Speed Techs., 793 F.3d 1268, 1283 &
`
`n.9 (Fed. Cir. 2015); see also Idle Free Sys., Inc. v. Bergstrom, Inc., IPR2012-
`
`00027, Paper 26, 5 (PTAB June 11, 2013) (“[A] substitute claim may not enlarge
`
`the scope of the challenged claim it replaces by eliminating any feature.”).
`
`PO’s amendment enlarges claim 1 by removing restrictions on how the data
`
`prefetch unit moves data. Claim 1 requires that the data prefetch unit “retrieves
`
`only computational data required by the algorithm from a second memory.” The
`
`plain meaning requires the data prefetch unit to perform a data retrieval from a
`
`second memory that only involves computational data required by the algorithm
`
`and nothing else. That is consistent with the patent’s description of the data
`
`prefetch unit prefetching only the required data. E.g., EX1001 8:22-27. This is also
`
`consistent with the use of the terminology “data prefetch unit” as understood by a
`
`POSA at the time, as the term “fetch” implies a retrieval process. EX1034 at ¶9.
`
`PO removes this retrieval requirement by deleting it and replacing it with
`
`“transfer,” MTA 4 (“wherein the data prefetch unit [retrieves] transfers only
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`4
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`computational data required by the algorithm from a second memory . . . and
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`places the [retrieved] computational data in the first memory”).
`
`PO’s change from “retrieves” to “transfers” broadens the claim in two ways.
`
`First, the amended claim no longer requires the data prefetch unit to retrieve the
`
`computational data from a second memory. Instead, another unit altogether could
`
`retrieve the computational data from second memory and the data prefetch unit
`
`could be used merely to affect transfer of that data and its placement in the first
`
`memory. EX1034 ¶7. Such a system would be within the scope of the amended
`
`claim but not the original claim because the original claim requires the data
`
`prefetch unit itself to perform the retrieval. Id. Second, the change allows for the
`
`retrieval of more than just “computational data required by the algorithm.” The
`
`amended claim’s “only” limitation restricts what the data prefetch unit transfers
`
`and places in the first memory, but it does not restrict what is retrieved from the
`
`second memory. Id. ¶10 A system with a data prefetch unit that retrieves
`
`computational data required by the algorithm and other data from a second
`
`memory would be within the amended claim’s scope but not the original claim’s
`
`scope because the original claim requires that the data prefetch unit retrieve “only
`
`computational data required by the algorithm from a second memory.” Id. Thus,
`
`for each of these reasons, PO’s amendment impermissibly enlarges the claim.
`
`Cuozzo Speed, 793 F.3d at 1283 & n.9; Idle Free, IPR2012-00027, Paper 26 at 5.
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`PO relies on its expert’s erroneous opinion that this change is narrowing
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`because it purportedly excludes “a situation where some data is read from the
`
`second memory but not placed in the first memory.” MTA 7. But PO’s expert has
`
`it backwards. As discussed, the original claim guards against PO’s hypothetical
`
`situation because it already requires the data prefetch unit to both retrieve and
`
`place only computational data required by the algorithm and nothing else, EX1001
`
`12:47-48; EX1033, whereas PO’s proposed amendment would permit the data
`
`prefetch unit to retrieve that computational data and other data from a second
`
`memory but place only the computational data in the first memory. EX1034 ¶11.
`
`Thus, PO has not met its burden and the motion should be denied.
`
`2.
`The data movement amendment does not relate to unpatentability
`PO has not met its burden to show that its data movement amendment
`
`“respond[s] to a ground of unpatentability involved in the trial.” 37 C.F.R. §§
`
`42.121(a)(2)(i) & 42.121(d)(1). First, PO makes no argument that the amendment
`
`is responsive, quoting only an unclear statement from its expert that the
`
`amendment “addresses” unspecified prior art examples involving “descriptors,” but
`
`without advancing any relationship to the instituted grounds or prior art. MTA 7.
`
`That quote is thus insufficient to meet PO’s burden. Second, the amendment is
`
`broadening, not narrowing, and thus cannot possibly be responsive to any ground
`
`of unpatentability. See Part III.A.1, supra. Finally, the amendment does not fall
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`within exceptions identified in Lectrosonics, Inc. v. Zaxcom, Inc., IPR2018-01129,
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`IPR2020-01449
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`Paper 15 (Feb. 25, 2019). There, the panel stated additional changes could be
`
`permitted if it “serves the public interest by helping to ensure the patentability of
`
`amended claims.” Id. at 6. Here, PO amends to overcome a construction that
`
`confirmed the data prefetch unit “retrieves only computational data required by the
`
`algorithm” and nothing else. EX1033. PO’s counsel admitted the court’s
`
`construction precludes infringement and indicated PO would seek to amend in IPR.
`
`EX1035; EX1036. But it is unjust to allow PO to amend in IPR to address non-
`
`infringement. Thus, the amendment should be denied on this basis as well.
`
`3.
`Proposed claim 20 is unpatentable over the prior art
`The Petition shows how the instituted combination renders obvious every
`
`limitation of original claim 1, and the below addresses the proposed amendments.
`
`a.
`The prior art discloses the data movement amendment
`PO’s data movement amendment enlarges claim 1’s scope. See Part III.A.1.,
`
`supra. Thus, this amendment is obvious for the same reasons as the original claim.
`
`See Pet. 22-27, 32-41; EX1006 ¶¶122-25, 137-46; Institution 56-57 (“Thus, Zhang
`
`teaches that only used fields of matrix elements during a given computation are
`
`sent from the main memory (second memory) to the cache (first memory, see
`
`Zhang’s Fig. 5), by prefetching using pointer chasing in the memory module
`
`(second memory) and packing/gathering only the used fields of the matrix element
`
`7
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`structure.”). PO argues its change addresses prior art “descriptors,” MTA 7, but
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`nowhere argues the instituted art discusses “descriptors,” let alone a data prefetcher
`
`that reads them.
`
`b.
`The prior art discloses the data computation amendment
`The Zhang-Gupta combination renders obvious PO’s data computation
`
`amendment (i.e., adding “wherein computations performed by the algorithm are
`
`performed by an FPGA”). Zhang teaches integrating “small blocks of
`
`programmable logic into key elements of a baseline architecture, including
`
`processing elements, components of the memory hierarchy, and the scalable
`
`interconnect, to provide architectural adaptation – the customization of
`
`architectural mechanisms and policies to match an application.” EX1003-13
`
`C2:44-49 & Fig. 2 (italic in original). Indeed, Zhang expressly teaches optimizing
`
`matrix multiplication computations in a reconfigurable processor using the
`
`customization provided by its programmable logic. See, e.g., EX1003-12 C1:28-31
`
`(“We present two case studies of architectural customization to enhance latency
`
`tolerance and efficiently utilize network bisection on multiprocessors for sparse
`
`matrix computations.”); id. C2:39-45 (“Using sparse matrix computations as
`
`examples, our results show that customization for application-specific
`
`optimizations can bring significant performance improvement.”); EX1034 ¶14.
`
`Further, Zhang shows integrating programmable logic within the CPU itself, in
`
`8
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`addition to the cache, network interface, and memory. Id.; EX1003 Fig. 2. Thus,
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`Zhang teaches using a reconfigurable processor comprising programmable logic
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`“processing elements”—which Zhang identifies separately from the logic in the
`
`memory hierarchy and interconnect, EX1003-13 C2:44-49—that would have been
`
`understood by a POSA for their use in performing computations in the CPU such
`
`as the sparse matrix multiplication operations described in Zhang. EX1034 ¶13;
`
`see also Pet. 42-43.
`
`Zhang teaches FPGA as an option for implementing its reconfigurability.
`
`EX1003-17 C1:22-26 (teaching implementation with FPGA); EX1034 ¶16.
`
`Indeed, PO does not dispute Zhang teaches implementation of its reconfigurable
`
`logic in FPGAs. Resp. 15 (“Zhang uses programmable logic (FPGA) as a means to
`
`deliver data for use by the CPU.”); MTA 6 (same). Zhang further discloses a
`
`computer architecture that uses programmable logic integrated into key
`
`components (including processing elements) to customize the architecture to match
`
`an application, and a POSA would understand that programmable logic to include
`
`FPGA. EX1003-12, abstract; EX1034 ¶13. FPGAs were widely known in the art to
`
`be used to perform scientific and other complex computations in processors,
`
`including sparse matrix computations, before the patent’s priority date. See
`
`EX1034 ¶12. Gupta confirms that a POSA would understand that Zhang’s
`
`programmable logic, including for its “processing elements,” is implemented in
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`9
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`FPGA. See id. ¶12; EX1004-8 C1:48-51 & Fig. 1. In view of Zhang’s teachings, a
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`POSA thus would have understood Zhang’s programmable logic and
`
`reconfigurability to be implemented with FPGA, such that the “computations
`
`performed by the algorithm” are performed by FPGA programmable logic. See Pet.
`
`11-12, 28-30; EX1006 ¶¶72-73, 155-56; EX1034 ¶15. Thus, the amendment is
`
`obvious in view of a POSA’s understanding of Zhang. See Realtime Data, LLC, v.
`
`Iancu, 912 F.3d 1368, 1372-73 (Fed. Cir. 2019).
`
`To the extent PO argues a POSA would not understand Zhang to use FPGAs
`
`for performing the algorithm’s computations, it would have nevertheless been
`
`obvious to do so based on the combination of Zhang with Gupta and/or the
`
`knowledge of a POSA. Gupta discloses performing computations in programmable
`
`logic such as FPGAs. See EX1004-8 C1:48-51 (“Architectural adaptation refers to
`
`the capability of a machine to support multiple architectural mechanisms and
`
`policies that can be tailored to application and/or data needs … [, including]
`
`tailoring the interaction of processing with I/O, customization of CPU elements
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`(e.g., splittable ALU [arithmetic-logic unit] resources …”) & Fig. 1 (showing
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`implementation in FPGA0, FPGA1 and FPGA2). A POSA would have been
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`motivated to combine Gupta’s teaching of performing computations in FPGA with
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`Zhang’s teaching of optimizing matrix multiplication computations in a
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`reconfigurable processor because, among other things, Zhang is suggestive of
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`doing so in teaching use of programmable processing elements in a reconfigurable
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`parallel processor architecture that performs sparse matrix computations, and
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`Gupta teaches a specific prototype implementation of that architecture and
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`technique, including reconfigurable logic blocks in FPGAs for application-specific
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`cache organization policies, hardware assisted blocking, prefetching, and dynamic
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`cache structures, see EX1004-9 C1:3-12. EX1034 ¶16. Thus, it would have been
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`obvious for a POSA to look to Gupta as one way to implement Zhang’s
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`reconfigurable data processing elements.
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`Moreover, given Zhang’s teaching of optimizing sparse matrix computations
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`and using programmable logic for reconfigurability to adapt to specific
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`applications, e.g., EX1003-12 C1:20-23, -12 C2:23-26, -13 C2:44-48, a POSA
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`would have (i) looked to ways to implement what is taught in Zhang, including
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`using FPGAs, which were well known for use in performing sparse matrix
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`computations, EX1034 ¶15, see Koninklijke Philips N.V. v. Google LLC, et al., 948
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`F.3d 1330, 1332 (Fed. Cir. 2020), (ii) with a reasonable expectation of success
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`because it was well-known to a POSA to perform computations, such as the sparse
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`matrix computations taught in Zhang, using FPGAs. EX1034 ¶15. Indeed, FPGA is
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`one of a finite number of identified, predictable solutions for implementing
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`Zhang’s programmable logic as taught by Zhang itself, which identifies FPGA as
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`one of two options along with LSI logic. EX1003-17 C1:22-26; EX1034 ¶16.
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`Thus, the amendment is obvious in view of Zhang combined with Gupta and/or the
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`knowledge of a POSA.
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`PO argues this amendment is not taught by the instituted combination
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`because the amendment purportedly excludes use of a “conventional CPU,” which
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`PO contends those references use. See Paper 26 5-6. But that argument fails. First,
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`the claim’s use of “comprising” does not preclude having other unclaimed
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`structure. Second, PO’s argument is premised on the unsubstantiated statement of
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`its expert. See id. 5; EX2027 ¶21. Nothing about its amendment, or any other
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`limitation, creates such an exclusion. Third, the definition of a “reconfigurable
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`processor” as “a computing device that contains reconfigurable components such
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`as FPGAs,” EX1001 5:26-29, does not exclude other non-reconfigurable
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`components, such as a conventional CPU, nor does it require fully reconfigurable
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`components. Finally, excluding a conventional CPU would contravene the ’867
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`patent itself, which expressly teaches using its reconfigurable processor with
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`conventional computing platforms. Id. Fig. 2 & 6:15-25 (“In a particular
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`implementation, a number of RPs 100 are implemented within a memory subsystem
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`of a conventional computer . . . . In this manner the RPs 100 can be accessed by
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`memory operations and so coexist well with a more conventional hardware
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`platform.”); EX1034 ¶17; see also PRPR 5-6; Institution 48-50. Thus, PO’s
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`argument that the amended claim excludes a conventional CPU fails. Accordingly,
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`the proposed substitute claim is obvious.
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`c.
`Trimberger also discloses the data computation amendment
`The data computation amendment is also obvious in view of the instituted
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`art (Zhang and Gupta) in further combination with Trimberger (EX1037), which
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`teaches using FPGAs to perform computations of algorithms. Trimberger was filed
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`on April 5, 1995, over eight years before the ’867 patent, and it issued in 1998.
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`Thus, Trimberger is prior art under at least pre-AIA §§ 102(a) and 102(b).
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`Trimberger discloses a technique to improve microprocessor performance
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`that utilizes conventional processor execution units working in parallel with
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`reprogrammable execution units. EX1037 1:7-11 (“The present invention relates to
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`techniques to improve the speed of microprocessors using reprogrammable
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`hardware; and more particularly to the use of reprogrammable execution units in
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`parallel with predefined execution units in a data processing system.”). EX1034
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`¶18. The purpose of the reprogrammable execution units is to perform complex or
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`special-purpose functions that may not be available in the instruction set of a
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`general-purpose processor or that would otherwise require implementing a special-
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`purpose processor to perform, which has a number of drawbacks. EX1037 1:24-35,
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`1:47-50, 1:63-2:2, 2:44-51; EX1034 ¶19. The reprogrammable execution units are
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`implemented in FPGA programmable logic and form a reprogrammable instruction
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`set accelerator (“RISA”) that is configured to accelerate execution of user-defined,
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`special-purpose instructions in general purpose processors for significant
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`performance improvement for a variety of user algorithms for particular
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`applications. EX1037 2:52-59, 5:12-18, 5:65-6:1, 6:36-41; EX1034 ¶19. The RISA
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`can be reprogrammed with different instructions at different times when the user
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`changes from one application to another. EX1037 3:7-9, 4:42-45. The instructions
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`may also be extracted on the fly and used for dynamically reconfiguring the
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`reprogrammable execution unit(s) on the RISA to perform the special functions. Id.
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`4:66-5:6, 6:10-27, 10:3-24; EX1034 ¶19.
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`Thus, Trimberger teaches improving a microprocessor performance by
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`including both conventional execution units for executing conventional processor
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`instructions and a reprogrammable execution unit (RISA) implemented in FPGA
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`for executing special-purpose instructions for a particular user-defined function.
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`EX1037 4:29-31, 8:60-65; EX1034 ¶20. Trimberger teaches that examples of the
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`special-purpose operations performed by the RISA include calculations of complex
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`algorithms for encryption/decryption, polynomial evaluation, and spreadsheet
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`resolution. EX1037 3:10-27; EX1034 ¶20. And Trimberger teaches that the RISA
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`can be reprogramed to adapt to each user program. EX1037 3:28-33, EX1034 ¶20.
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`Trimberger therefore teaches a microprocessor in which computations performed
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`by an algorithm are performed by an FPGA. EX1034 ¶20.
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`Trimberger’s teaching of integrating its RISA FPGA functional units with a
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`conventional microprocessor, e.g. EX1037 5:28-31, 6:63-65, exposes the fallacy of
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`P