UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`INTEL CORPORATION,
`
`Petitioner
`
`v.
`
`FG SRC LLC,
`
`Patent Owner
`
`____________________
`
`CASE NO.: 2020-01449
`PATENT NO. 7,149,867
`____________________
`
`DECLARATION OF EILEEN D. MCCARRIER
`
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`
`Alexandria, VA 22313-1450
`
`
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`I, Eileen D. McCarrier, declare as follows:
`
`1.
`
`I am currently Manager of Research Services at Pillsbury Winthrop
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`Shaw Pittman LLP, where I have worked as a reference librarian and manager of
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`research services for 26 years.
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`2.
`
`I make this declaration based on my own personal knowledge,
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`including my knowledge of library science practices and the evidence cited herein.
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`3.
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`I earned a Master of Arts degree in Library Science from the
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`University of Wisconsin-Madison in 1980, and I have worked as a law librarian for
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`40 years.
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`4.
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`I have prepared this declaration in connection with the above-
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`captioned inter partes review (“IPR”) proceeding for which I obtained library
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`copies of previously filed Exhibits 1003 and 1004. Each of these articles was
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`published by the Institute of Electrical and Electronics Engineers, Inc. (“IEEE”), a
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`widely recognized publisher of technical papers spanning a broad range of
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`technologies including electronics, electrical engineering, telecommunications,
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`computing, and more. The IEEE publishes thousands of conference papers every
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`year, including by making them publicly available via its Xplore digital library.
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`The IEEE’s collection of publications is recognized within the reference library
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`field as an authoritative source of consolidated published papers in electrical
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`engineering, computer science, and related fields.
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`5.
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`The primary holders of the original printed versions of IEEE
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`conference proceedings from the 1996–2000 era are generally university libraries
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`across the United States. However, at the time of the drafting of this declaration,
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`safety protocols relating to COVID-19 continue to restrict the ability of members
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`of the public to physically access many of these institutions. To accommodate
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`these safety procedures, the library copies described below were physically located
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`by library staff, digitally scanned, and then emailed directly to me.
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`2
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`Library copies of Zhang, Exhibit 1003
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`6.
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`X. Zhang et al., Architectural Adaptation for Application-Specific
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`Locality Optimizations, IEEE (1997), published in the Proceedings of the
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`International Conference on Computer Design - VLSI in Computers and
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`Processors (IEEE, October 12–15, 1997), 150–156 (“Zhang”) was filed as Exhibit
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`1003 with the petition in the above-captioned IPR proceeding.
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`7.
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`A true and correct copy of Zhang obtained from the Library of the
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`Missouri University of Science and Technology, Rolla, Missouri, part of the
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`University of Missouri system, is attached as Appendix EDM01. I personally
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`received this copy as a pdf from the interlibrary loan department of C. L. Wilson
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`Library.
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`Library copies of Gupta, Exhibit 1004
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`8.
`
`R. Gupta, Architectural Adaptation in AMRM Machines, Proceedings
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`of the IEEE Computer Society Workshop on VLSI 2000 (IEEE, April 27–28,
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`2000), 75–79 (“Gupta”) was filed as Exhibit 1004 with the above-captioned IPR
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`petition.
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`9.
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`A true and correct copy of Gupta obtained from the Georgia Tech
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`Library, Georgia Institute of Technology is attached as Appendix EDM02. I
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`personally received this copy as a pdf from the library’s Interlibrary Loan Office.
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` I
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` declare under penalty of perjury that the foregoing is true and correct.
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`
`
`
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`Date: March 31, 2021
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`
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`____________________________
`Eileen D. McCarrier
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`3
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`Appendix EDM01
`Appendix EDMOl
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`111iti1iiii11
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`050-102823580
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`LIBRARY
`UNIVERSITY OF MISSOURI-ROLLA
`1870 MINER CIRCLE
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`DEMCO ✓
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`

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`Proceedings
`
`International Conference on
`Computer Design
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`VLSI in Computers and Processors
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`

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`Proceedings
`
`Tl<
`717f
`.Ilf3
`/997
`
`International Conf ere nee on
`Con1puter Design
`
`VLSI in Computers and Processors
`
`October 12-15, 1997
`Austin, Texas
`
`Sponsored by
`IEEE Computer Society Technical Committee on Design Automation
`IEEE Circuits and Systems Society
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`IEEE~
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`COMPUTER
`SOCIETY
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`Los Alamitos, California
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`Brussels
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`Copyright © 1997 by The Institute of Electrical and Electronics Engineers, Inc.
`All rights reserved
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`Table of Contents
`
`ICCD '97 Conference Program
`
`1997 Technical Program
`Welcome to ICCD'97 ................................................................................................................. xiv
`Program Committee ................................................................................................................ xvi
`Additional Referees ................................................................................................................. xix
`
`Session 1.1: Keynote Speech
`Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures ................... 2
`D. Patterson, K. Asanovic, A. Brown, R. Fromm, J. Golbus, B. Gribstad,
`K. Keeton, C. Kozyrakis, D. Martin, S. Perissakis, R. Thomas, N. Treuhaft,
`and K Yelick, University of California at Berkeley, California
`
`Session 1.2: CAD Plenary
`Chair: Andreas Kuehlmann, IBM T. J. Watson Research Center
`A Brief History of the Future of Semiconductor Electronic Design Automation ..................... 10
`Ron Rohrer, TBD Consultants
`
`Concurrent Sessions 1.3
`
`Session 1.3.1: Special Session: Industrial Applications of Formal Verification
`Organizer and Chair: Andreas Kuehlmann, IBM T. J. Watson Research Center
`Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264
`Microprocessor .............................................................................................................................. 16
`G.P. Bischoff, K.S. Brace, S. Jain, and R. Razdan
`Intertwined Development and Formal Verification of a 60x bus Model ................................... 25
`M. Kaufmann and C. Pixley
`Formally Specifying and Mechanically Verifying Programs for the Motorola Complex
`Arithmetic Processor DSP ............................................................................................................ 31
`B.C. Brock and W.A Hunt, Jr.
`BIST-Based Fault Diagnosis in the Presence of Embedded Memories ..................................... 37
`J. Savir
`Built-in Self Test for Content Addressable Memories ................................................................ 48
`Y.-S. Kang, J.-C. Lee, and S. Kang
`Pseudo-Random Pattern Testing of Bridging Faults ........................ ......................................... 54
`N.A Touba and E.J. McCluskey
`
`Session 1.3.3: Simulation and Power Estimation
`Chair: Teng-Sheng Moh, Silicon Valley Research, Inc.
`Novel Simulation ofDeep-Submicron MOSFET Circuits ............... ........................................... 62
`S. Bruma and R.H.J.M. Otten
`Time-Stamped Transition Density for the Estimation of Delay Dependent
`Switching Activities ...................................................................................................................... 68
`H. Choi and S.H. Hwang
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`Power Compiler: A Gate-Level Power Optimization and Synthesis System ............................ 74
`B. Chen and I. Nedelcheu
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`Session 1.3.4: Branch Prediction
`Chair: Jim Bondi, Texas Instruments
`Elastic History Buffer: A Low-Cost Method to Improve Branch
`Prediction Accuracy ...................................................................................................................... 82
`M.-D. Tarlescu, KB. Theobald, and G.R. Gao
`Design Optimization for High-Speed Per-address Two-level Branch Predictors ..................... 88
`I.-C.K. Chen, C.-C. Lee, M.A. Postiff, and T.N. Mudge
`PA-8000: A Case Study of Static and Dynamic Branch Prediction ........................................... 97
`C. Burch
`
`Concurrent Sessions 1.4
`
`Session 1.4.1: New Techniques for Gate-Sizing and Retiming
`Chair: Derek Beatty, Motorola, Inc.
`Discrete Drive Selection for Continuous Sizing ........................................................................ 110
`R. Haddad, L.P.P.P. van Ginneken, and N. Shenoy
`Continuous Retiming: Algorithms and Applications ................................................................ 116
`P.Pan
`Optimal Clock Period Clustering for Sequential Circuits with Retuning ............................... 122
`A.K. Karandikar, P. Pan, and C.L. Liu
`
`Session 1.4.2: Circuit Modeling
`Chair: Sandip Kundu, IBM Corp.
`Comparison between nMOS Pass-Transistor logic style vs. CMOS
`Complementary Cells ................................................................................................................. 130
`R. Mehrotra, M. Pedram, and X Wu
`Circuit-Based Description and Modeling of Electromagnetic Noise Effects
`in Packaged Low-Power Electronics .......................................................................................... 136
`A. C. Cangellaris, W. Pinello, and A. Ruehli
`Transistor-Level Sizing and Timing Verification of Domino Circuits in the
`Power PC Microprocessor ........................................................................................................... 143
`A. Dharchoudhury, D. Blaauw, J . Norton, S. Pullela, and J. Dunning
`
`Session 1.4.3: Novel Architectures
`Chair: Greg Fisher, Printronix Corporation
`Architectural Adaptation for Application-Specific Locality Optimization .............................. 150
`X Zhang, A. Dasdan, M. Schulz, R.K. Gupta, and A.A. Chien
`A New Processor Architecture for Digital Signal Transport Systems .................................... 157
`M. Inamori, K Ishii, A. Tsutsui, K. Shirakawa H. Nakada, and T. Miyazaki
`
`Short Papers
`PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia .......................... 164
`J.A. Leijten, J.L. van Meerbergen, A.A. Timmer, and J.A.G. Jess
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`Enhanced Compression Techniques to Simplify Program Decompression
`and Execution ............................................................................................................................. 170
`M. Breternitz, Jr. and R. Smith
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`Session 1.4.4: Low Power Architectures
`Chair: Tim Brodnax, IBM
`A Low Power Approach to Floating Point Adder Design ............................... , ......................... 178
`R. V.K. Pillai, D. Al-Khalili, and A.J. Al-Khalili
`Design and Implementation of Low-Power Digit-Serial Multipliers ...................................... 186
`Y.-N. Chang, J.H. Satyanarayana, and K.K. Parhi
`On Complexity Reduction of FIR Digital Filters Using Constrained
`Least Squares Solution ............................................................................................................... 196
`K. Muhammad and K. Roy
`
`Concurrent Session 1.5
`
`Session 1.5.1: Timing Optimization for Deep Submicron Technology
`Chair: Masahiro Fujita, Fujitsu Laboratories of America
`An Integrated Placement and Synthesis Approach for Timing Closure of
`Power PC™ Microprocessors ....................................................................................................... 206
`S. Hojat and P. Villarrubia
`Post-Layout Circuit Speed-up by Event Elimination ............................................................... 211
`H. Vaishnav, C.-K. Lee, and M. Pedram
`Clustering and Load Balancing for Buffered Clock Tree Synthesis ........................................ 217
`A.D. Mehta, Y.-P. Chen, N. Menezes, D.F. Wong, and L. T. Pileggi
`CMOS Gate Delay Models for General RLC Loading .............................................................. 224
`R. Arunachalam, F. Dartu, and L. T. Pileggi
`
`Session 1.5.2: Special Session: The G4 S/390 Microprocessor
`Organizer: Andreas Kuehlmann, IBM T. J. Watson Research Center
`Chair: Sumit Dasgupta, IBM
`Design Methodology for the High-Performance G4 S/390 Microprocessor ............................. 232
`K.L. Shepard, S. Carey, D.K. Beece, R. Hatch, and G. Northrop
`A High-Frequency Custom CMOS S/390 Microprocessor ........................................................ 241
`C.F. Webb and J.S. Liptay
`High Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor .................. 247
`J. Warnock, L. Sigal, B. Curran, and Y. Chan
`A 400 MHz, 144Kb CMOS ROM MACRO for an IBM S/390-Class Microprocessor ............... 253
`A. Tuminaro
`
`Session 1.5.3: Multiprocessor Communication
`Chair: Wai-Chi Fang, Jet Propulsion Laboratory
`A Comparative Evaluation of Hierarchical Network Architecture of the
`HP-Convex Exemplar ................................................................................................................. 258
`R. Castaneda, X. Zhang, and J.M. Hoover, Jr.
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`Effect of Message Length and Processor Speed on the Performance of the Bidirectional
`Ring based Multiprocessor ......................................................................................................... 267
`H. Oi and N. Ranganathan
`An Approach to Network Caching for Multimedia Objects ..................................................... 273
`M.A. Kozuch, W. Wolf, and A. Wolfe
`Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip .......................... 279
`W.K. Luk, Y. Katayama, W. Hwang, M. Wordeman, T. Kirihata, A. Satoh,
`S. Munetoh, H. Wong, B. El-Kareh, P. Xio, and R . Joshi
`
`Session 1.5.4: Asynchronous Architectures
`Chair: Eric Chou, Hewlett-Packard ULSI Labs
`TITAC-2: An asynchronous 32bit microprocessor based on Scalable -Delay-
`Insensitive model ........................................................................................................................ 288
`A. Takamura, M. Kuwako, M. Ima, T. Fujii, M. Ozawa, I. Fukasaku,
`Y. Ueno, and T. Nanya
`An Evaluation of Asynchronous and Synchronous Design for Superscalar
`Architectures ............................................................................................................................... 295
`A. Davey and D. Loyd
`Synthesis of High Speed Delay-Insensitive Combinational Iterative Tree Circuits .............. 301
`F.-C. Cheng
`Asynchronous Wrapper for Heterogeneous Systems ............................................................... 307
`D.S. Bormann and P. Y.K. Cheung
`
`Concurrent Session 1.6
`
`Session 1.6.1
`Panel: The War of the Roses: Designers versus Tool Developers ........................................... 317
`Organizer: Andreas Kuehlmann, IBM T. J. Watson Research Center
`Moderator: Daniel Beece, IBM T. J. Watson Research Center
`Panelists:
`Barbara Chappell, Intel Corp.
`Robert Damiano, Synopsys, Inc.
`Charlie Malley, Hewlett-Packard
`Yiannos Manoli, University of Saarland
`David F. Reed, Advanced Micro Devices
`Steven E. Schulz, Texas Instruments
`
`Session 1.6.2
`Panel: If Software is King for Systems-on-Silicon, What's New in Compilers? ..................... 322
`Organizer: Nikil Dutt, University of California at Irvine
`Moderator: Sharad Malik, Princeton University
`Panelists:
`Lex Augusteijn, Philips Research Laboratory
`Beatrice Fu, Intel Corporation
`Alex Nicolau, University of California at Irvine
`Constantine Polychronopoulus, University of Illinois at Urbana-Champaign
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`Session 2.1 Design and Test Plenary
`Chair: Magdy Abadir, Motorola, Inc.
`Design and Test: The Lost World .............................................................................................. 328
`W. Joyner, IBM T. J. Watson Research Center
`
`Concurrent Sessions 2.2
`
`Session 2.2.1: Binary Decision Diagrams
`Chair: B. Bischoff, Digital Equipment Corporation
`Equivalence Checking Using Abstract BDDs .......................................................................... 332
`S. Jha, Y. Lu, M. Minea, and E.M. Clarke
`Speeding up Variable Reordering ofOBDDs ............................................................................ 338
`C. Meinel and A. Slobodova
`Dynamic Reordering in a Breadth-First Manipulation Based BDD
`package: Challenges and Solutions ........................................................................................... 344
`R.K. Ranjan, W. Gosti, R.K. Brayton, and A. Sangiovanni-Vincentelli
`Timed Binary Decision Diagrams .............................................................................................. 352
`Z. Li, Y. Zhao, Y. Min, and R.K. Brayton
`
`Session 2.2.2: Advanced Test Topics
`Chair: Magdy Abadir, Motorola
`Vector Restoration Based Static Compaction of Test Sequences for Synchronous
`Sequential Circuits ..................................................................................................................... 360
`I. Pomeranz and S.M. Reddy
`Nonenumerative Path Delay Fault Coverage Estimation with
`Optimal Algorithms .................................................................................................................... 366
`D. Kagaris, S. Tragoudas, and D. Karayiannis
`Properties of the Input Pattern Fault Model.. .......................................................................... 372
`R.D. (Shawn) Blaton and J.P. Hayes
`A new approach for Initialization Sequences Computation for Synchronous
`Sequential Circuits ..................................................................................................................... 381
`F. Corno, P. Prinetto, M. Rebaudengo, M.S. Reorda, and G. Squillero
`
`Session 2.2.3: Embedded Software and Systems
`Chair: Rolf Ernst, Technische Universitaet Braunschweig, Germany
`Real Time Operating Systems for Embedded Computing ....................................................... 388
`Y. Li, M. Potkonjak and W. Wolf
`Allocation and Data Arrival Design of Hard Real Time Systems ........................................... 393
`D.L. Rhodes and W. Wolf
`Improving Design Turnaround Time Via Two-Levels Hw/Sw Co-Simulation ....................... 400
`A. AUara, S. Filipponi, W. Fomaciari, F. Salice, and D. Sciuto
`
`Session 2.2.4: Low Power Issues
`Chair: Jose L. Cruz-Rivera, University of Puerto Rico-Mayaguez
`Power Constrained Design of Multiprocessor Interconnection Networks .............................. 408
`C.S. Patel, S .M. Chai, S. Yalamanchili, and D.E. Schimmel
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`Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder ........................ 417
`P. Soderquist and M. Leeser
`Asynchronous Transpose-Matrix Architectures ....................................................................... 423
`J.A. Tierno and P. Kudva
`A Low Power Smart Vision System Based on Active Pixel Sensor
`Integrated with Programmable Neural Processor ................................................................... 429
`W.-C. Fang, G. Yang, B. Pain, and B.J. Sheu
`
`Concurrent Sessions 2.3
`
`Session 2.3.1: Formal Verification Methods
`Chair: Warren Hunt, Jr., Computational Logic, Inc.
`Formal Verification of the HAL Sl System Cache Coherence Protocol .................................. 438
`A.J. Hu, M. Fujita, and C. Wilson
`A Survey of Techniques for Formal Verification of Combinational Circuits .......................... 445
`J. Jain, A. Narayan, M. Fujita, and A. Sangiovanni-Vincentelli
`Checking Formal Specifications under Simulation .................................................................. 455
`W. Canfield, E.A. Emerson, and A. Saha
`
`Session 2.3.2: Mixed Signal Design and Test
`Chair: Yervant Zorian, Logic Vision
`Built-In Temperature Sensors for On-line Thermal Monitoring of
`Microelectronic Structures ......................................................................................................... 462
`K. Arabi and B. Kaminska
`Develop of Hierarchical Testability Design Methodologies for Analog/ Mixed-Signal
`Integrated Circuits ..................................................................................................................... 468
`C.-P. Wang and C.-L. Wey
`AN ovel Test Set Design for Parametric Testing of Analog and Mixed-Signal Circuits ........ 4 7 4
`J. Chen and A. Ramachandran
`
`Session 2.3.3: FPGA Design
`Chair: Paul Franzon, North Carolina State University
`On the Construction of Universal Series-Parallel Functions for Logic Module Design ......... 482
`F. Y. Young and D.F. Wong
`An Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs ......................... 489
`J. Stohmann and E. Barke
`Channel Segmentation Design for Symmetrical FPGAs ......................................................... 496
`W.-K. Mak and D.F. Wong
`
`Session 2.3.4: Cache Technology I
`Chair: Mauricio Breternitz, Motorola Inc.
`Multi-Column Implementations for Cache Associativity ......................................................... 504
`C. Zhang, X. Zhang, and Y. Yan
`Design and Performance Evaluation of a Cache Assist to Implement
`Selective Caching ........................................................................................................................ 510
`L.K. John and A. Subramanian
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`On Effective Data Supply for Multi-Issue Processor ................................................................ 519
`J.A. Riuers, E.S. Tam, and E.S. Davidson
`
`Concurrent Sessions 2.4
`
`Session 2.4.1: Embedded Tutorial
`Practical Issue of Interconnect Analysis in Deep Submicron Integrated Circuits ................. 532
`Chair: Andreas Kuehlmann, IBM T. J. Watson Research Center
`Presenter: Kenneth L. Shepard, IBM T. J. Watson Research Center
`
`Session 2.4.2: Fault Diagnosis
`Chair: Raj Raina, Motorola, Inc.
`First Results of System Level Fault Tolerant Design Validation Through
`Laser Fault Injection .................................................................................................................. 544
`W. A. Moreno, F.J. Falquez, J.R. Samon Jr., and T. Smith
`Integrated Diagnostics for Embedded Memory Built-in Self Test
`on PowerPC™ Devices ................................................................................................................ 549
`C. Hunter
`A TSC Evalution Function for Combinatorial Circuits ............................................................ 555
`C. Bolchini, D. Sciuto, and F. Salice
`
`Session 2.4.3: Special Session: Low Power Design Issues
`Chair: Sanna Vrudhula, University of Arizona
`An Architectural Power Optimization Case Study Using High-level Synthesis .................... 562
`C.-T. Chen and K. Kucukcakar
`High-Level Design Synthesis of Low Power, VLIW Processor for the IS-54
`VSELP Speech Encoder ............................................................................................................. 571
`R. Henning and C. Chakrabarti
`
`Session 2.4.4: Cache Technology Il
`Chair: Michael Stumm, University of Toronto
`Fast Cache Access with Full-Map Block Directory ................................................................. 578
`J.-K. Peir, W.W. Hsu, H. Young, and S. Ong
`A Data Alignment Technique for Improving Cache Performance ........................................... 587
`P.R. Panda, H. Nakamura, N.D. Dutt, and A. Nicolau
`Instruction Prefetching Using Branch Prediction Information ............................................... 593
`1.-C.K. Chen, C.-C. Lee, and T.N. Mudge
`
`Session 3.1: Architecture & Algorithm Plenary
`Chair: J. Robert Jump, Rice University
`Is Wireless Data Dead? ............................................................................................................. 604
`Randy Katz, Uniuersity of California at Berkeley, California
`
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`Concurrent Sessions 3.2
`
`Session 3.2.1: Layout Partitioning and Synthesis
`Chair: Georg Pelz, Gerhard-Mercator-University-GB, Duisburg, Germany
`An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits ................... 608
`X. Tan, J. Tong, P. Tan, N. Park, and F. Lombardi
`Partitioning Under Timing and Area Constraints ................................................................... 614
`G. Tumbush and D. Bhatia
`A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement ....... 621
`J .A. Chandy, and P. Banerjee
`Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation ............................... 628
`H. Zhou and D.F. Wong
`
`Session 3.2.2: Design for Testability & Test Synthesis
`Chair: Sujit Dey, NEC
`High Level Test Synthesis Across the Boundary of Behavioral and Structural
`Domains ...................................................................................................................................... 636
`K. Lai, C.A. Papachristou, and M. Baklashov
`Power Driven Partial Scan ......................................................................................................... 642
`J .-Y . Jou and M.-C. Nien
`Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan .................. 648
`R .C. Tekumalla and P.R. Menon
`Application of a Testing Framework to VHDL Descriptions at Different
`Abstraction Levels ...................................................................................................................... 654
`M. Bacis, G. Buonanno, F. Ferrandi, F. Fummi, L. Gerli, and D. Sciuto
`
`Session 3.2.3: Embedded Tutorial
`Practical Advances in Asynchronous Design ................... ........................................................ 662
`Chair: Rob Roy, NEC, Inc.
`Presentors:
`Eric Brunvand of University of Utah
`Steve Nowick of Columbia University
`Kenneth Yun of University of California at San Diego
`
`Session 3.2.4: Arithmetics
`Chair: Joe Cavallaro, Rice University
`Benchmarking and Analysis of Architectures for CAD Applications ...................................... 670
`A. Mehrotra, S. Qadeer, R.K. Ranjan, and R.H. Katz
`Fast Low-Energy VLSI Binary Addition ................................................................................... 676
`K.K. Parhi
`A Floating-Point Divider using Redundant Binary Circuits and an Asynchronous
`Clock Scheme .............................................................................................................................. 685
`H. Suzuki, H. Mankino, K. Mashiko, and H. Hamano
`Parallel-Array Implementations of A Non-Restoring Square Root Algorithm ....................... 690
`Y. Li and W. Chu
`
`xii
`
`Intel Exhibit 1028 - 16
`
`

`

`Concurrent Session 3.3
`
`Session 3.3.1: Asynchronous Design
`Chair: Daniel Saab, Case Reserve Western University
`Optimizing CMOS Implementations of C-element ................................................................... 700
`M. Shams, J.C. Ebergen, and M.I. Elmasry
`A Doubly-Latched Asynchronous Pipeline ................................................................................ 706
`R. Kol and R. Ginosar
`A Pulse-To-Static Conversion Latch With a Self-Timed Control Circuit ................................ 712
`W. Hwang, R.V. Joshi, and W.H. Henkels
`
`Session 3.3.2: Special Session: Interconnect Modeling & Repeater Methodologies
`Chair: Byron Krauter, IBM Corp.
`Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect ........ 720
`N. Chang, V. Kanevsky, O.S. Nakagawa, K. Rahmat, and S.-Y. Oh
`A Repeater Optimization Methodology for Deep Sub-Micron, High-Performance
`Processor .................................................................................................................................... 726
`D. Li, A. Pua, P. Srivastava, and U. Ko
`Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family .................................... 732
`Z. Zhu and B.S. Carlson
`
`Session 3.3.3: Finite-State Machine and High-Level Synthesis
`Chair: Ramin Hojati, University of California at Berkeley
`Divide and Conquer: A Strategy for Synthesis of Low Power Finite State Machines ........... 740
`A. Dasgupta and S. Ganguly
`Estimation of Maximum Power for Sequential Circuits Considering
`Spurious Transitions .................................................................................................................. 7 46
`C.-Y. Wang and K. Roy
`Dynamic Bounding of Successor Force Computations in the Force Directed
`List Scheduling Algorithm ......................................................................................................... 752
`S. Govindarajan and R. Vemuri
`
`Author Index ............................................................................................................................ 758
`
`xiii
`
`Intel Exhibit 1028 - 17
`
`

`

`Architectural Adaptation for Application-Specific Locality Optimizations
`
`Xingbin Zhang*
`
`Ali Dasdan* Martin Schulzt
`
`Rajesh K. Gupta+
`
`Andrew A. Chien*
`
`'Department of Computer Science
`University of Illinois at Urbana-Champaign
`{ zhang, dasdan, achien} @cs. uiuc. edu
`
`tJ:nstitut fiir Informatik
`Technische Universitat Mtinchen
`schulzm@ inf ormatik. tu-muenchen. de
`
`+Information and Computer Science, University of California at Irvine
`rgupta@ics. uci. edu
`
`Abstract
`
`We propose a machine architecture that integrates pro(cid:173)
`grammable logic into key components of the system with
`the goal of customizing architectural mechanisms and poli(cid:173)
`cies to match an application. This approach presents
`an improvement over traditional approach of exploiting
`programmable logic as a separate co-processor by pre(cid:173)
`serving machine usability through software and over tra(cid:173)
`ditional computer architecture by providing application(cid:173)
`specific hardware assists. We present two case studies of
`architectural customization to enhance latency tolerance
`and efficiently utilize network bisection on multiproces(cid:173)
`sors for sparse matrix computations. We demonstrate that
`application-specific hardware assists and policies can pro(cid:173)
`vide substantial improvements in performance on a per ap(cid:173)
`plication basis. Based on these preliminary results, we pro(cid:173)
`pose that an application-driven machine customization pro(cid:173)
`vides a promising approach to achieve high performance
`and combat performance fragility.
`
`1 Introduction
`
`Technology projections for the coming decade [I] point
`out that system performance is going to be increasingly
`dominated by intra-chip interconnect delay. This pre