Trials@uspto.gov
`571-272-7822
`
`Paper 13
`Date: March 3, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`IPR2020-01449
`Patent 7,149,867 B2
`
`
`
`
`
`
`
`
`
`Before KALYAN K. DESHPANDE, GREGG I. ANDERSON, and
`KARA L. SZPONDOWSKI, Administrative Patent Judges.
`SZPONDOWSKI, Administrative Patent Judge.
`
`
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`INTRODUCTION
`I.
`Intel Corporation (“Petitioner”) filed a Petition (Paper 1, “Pet.”) to
`institute an inter partes review of claims 1–19 of U.S. Patent 7,149,867 B2,
`issued on December 12, 2006 (Ex. 1001, “the ’867 patent”). FG SRC LLC
`(“Patent Owner”) filed a Preliminary Response (Paper 9, “Prelim. Resp.”) to
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`IPR2020-01449
`Patent 7,149,867 B2
`the Petition. With our authorization (Paper 10), Petitioner filed a Reply to
`the Preliminary Response (Paper 11, “Reply”) and Patent Owner filed a Sur-
`Reply (Paper 12, “Sur-Reply”). We have jurisdiction under 35 U.S.C.
`§ 314.
`Institution of an inter partes review is authorized when “the
`information presented in the petition . . . and any response . . . shows that
`there is a reasonable likelihood that the petitioner would prevail with respect
`to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
`Based on the current record, and for the reasons explained below, we
`determine that Petitioner has established a reasonable likelihood that it
`would prevail with respect to at least one challenged claim. Accordingly,
`we institute an inter partes review as to the challenged claims and grounds
`raised in the Petition.
`
`II. BACKGROUND
`A. Real Parties in Interest
`Petitioner identifies Intel Corporation as the sole real party in interest.
`Pet. 2. Patent Owner identifies FG SRC LLC as the sole real party in
`interest. Paper 4, 2.
`B. Related Matters
`The parties advise that the ’867 patent is the subject of the following
`district court litigations:
`FG SRC LLC v. Intel Corporation, 6:20-cv-00315-ADA (W.D. Tex.)
`filed April 24, 2020 (“the parallel district court litigation”);
`FG SRC LLC v. Xilinx, Inc., 1:20-cv-00601-LPS (D. Del), filed April
`30, 2020; and
`SRC Labs, LLC et al., v. Amazon Web Services, Inc., et al., 2:18-cv-
`00317-JLR (W.D. Wash.), filed February 26, 2018.
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`IPR2020-01449
`Patent 7,149,867 B2
`Pet. 2; Paper 4, 2. Petitioner also advises that the ’867 patent was the
`subject of IPR2019-00103 (institution denied on May 10, 2019). Pet. 2
`C. The ’867 Patent (Ex. 1001)
`The ’867 patent issued from Application No. 10/869,200 filed June
`16, 2004, and claims the benefit of Provisional Application No. 60/479,339,
`filed June 18, 2003. Ex. 1001, codes [21], [22], [60]. The ’867 patent is
`titled “System and Method of Enhancing Efficiency and Utilization of
`Memory Bandwidth in Reconfigurable Hardware” and is generally directed
`to “enhancing the efficiency and utilization of memory bandwidth in
`reconfigurable hardware” and “implementing explicit memory hierarchies in
`reconfigurable processors that make efficient use of off-board, on-board,
`on-chip storage and available algorithm locality.” Id. at code [57], 1:15–24.
`1. Background and Summary of the Problem
`The ’867 patent explains that microprocessors “have enjoyed annual
`performance gains averaging about 50% per year,” where most of the gains
`were attributable to higher clock processor speeds, more memory bandwidth,
`and increasing utilization of instruction level parallelism (“ILP”) at
`execution time. Id. at 1:26–30. However, as microprocessor speeds
`increased, designing memory hierarchies that could keep up became
`challenging. Id. at 1:31–33. Therefore, “there has been significant effort
`spent on the development of memory hierarchies that can maintain high
`bandwidth efficiency and utilization with faster microprocessors.” Id. at
`1:48–50.
`The ’867 explains that one approach to improving bandwidth
`efficiency and utilization in memory hierarchies is the utilization of cache
`memories. Id. at 1:51–53. In designing cache memories, there are a number
`of considerations to take into account, such as the width of the cache line,
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`cache associativity, how cache lines are replaced due to a capacity or
`conflict miss, the write policy for the cache, and the size and speed of the
`cache. Id. at 1:59–3:15. For example, wide cache lines are more efficient
`for programs that exhibit a high degree of spatial locality (i.e., it is likely
`that other data within the same cache line will be needed). Id. at 1:64–2:4.
`However, narrow cache lines are more efficient for programs that have low
`levels of spatial locality. Id. at 2:4–7. The ’867 patent states that the various
`considerations and tradeoffs makes cache design challenging for a
`multipurpose computer that executes a wide variety of programs in that “it is
`very difficult to design a single cache structure that is optimized for many
`different programs.” Id. at 3:28–30. Cache designers try to derive the
`program behavior of the “average” program, and optimize the cache for the
`“average” program. Id. at 3:32–36. As a result, the cache is sub-optimal for
`most programs, because most programs that actually run on the
`microprocessor are not “average.” Id. at 3:36–39.
`2. The Claimed Invention of the ’867 Patent
`According to the ’867 patent, because of the foregoing issues, there
`was a growing need to develop improved memory hierarchies that limited
`overhead of a memory hierarchy without also reducing bandwidth efficiency
`and utilization. Id. at 3:57–60. To address this need, the ’867 patent
`describes a system including a memory hierarchy and a reconfigurable
`processor that includes a data prefetch unit. Id. at 4:4–10, 5:60–62, 6:9–13,
`7:34–48. The ’867 patent states that a “Reconfigurable Processor” is “a
`computing device that contains reconfigurable components such as FPGAs
`[(field programmable gate arrays)] and can, through reconfiguration,
`instantiate an algorithm as hardware.” Id. at 5:26–29. The ’867 patent states
`that a “Data prefetch Unit” is “a functional unit [a set of logic that performs
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`a specific operation] that moves data between members of a memory
`hierarchy [a collection of memories],” where such “movement may be as
`simple as a copy, or as complex as an indirect indexed strided copy into a
`unit stride memory.” Id. at 5:34–43.
`Figure 1 of the ’867 patent, reproduced below, shows a reconfigurable
`processor (RP) 100 of the claimed invention. Id. at 4:38–40.
`
`
`Figure 1 depicts a reconfigurable processor (RP) 100. Id. at 4:38–40.
`Figure 1 depicts reconfigurable processor 100, which “may be
`implemented using field programmable gate arrays (FPGAs) or other
`reconfigurable logic devices, that can be configured and reconfigured to
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`contain functional units and interconnecting circuits, and a memory
`hierarchy comprising on-board memory banks 104, on-chip block RAM 106,
`registers wires, and a connection 108 to external memory.” Id. at 6:5–11. In
`addition, “on-chip reconfigurable components 102 create memory structures
`such as registers, FIFOs, wires and arrays using block RAM.” Id. at 6:11–
`14. “Dual-ported memory 106 is shared between on-chip reconfigurable
`components 102.” Id. at 6:14–15. “The reconfigurable processor 100 also
`implements user-defined computational logic . . . constructed by
`programming an FPGA to implement a particular interconnection of
`computational functional units.” Id. at 6:15–19. “In a particular
`implementation, a number of RPs 100 are implemented within a memory
`subsystem of a conventional computer, such as on devices that are
`physically installed in dual inline memory module (DIMM) sockets of a
`computer.” Id. at 6:19–23. “In this manner the RPs 100 can be accessed by
`memory operations and so coexist well with a more conventional hardware
`platform.” Id. at 6:23–25. The ’867 patent explains that “[u]nlike
`conventional static hardware platforms . . . the memory hierarchy provided
`in a RP 100 is reconfigurable” and “through the use of data access units and
`associated memory hierarchy components, computational demands and
`memory bandwidth can be matched.” Id. at 7:17–22.
`One or more data prefetch units are used to improve the memory
`hierarchy and bandwidth efficiency and utilization. Id. at 3:58–60, 8:62–65.
`Fig. 4 of the ’867 patent, reproduced below, depicts a logic block 300 with
`an addition of a data prefetch unit 401. Id. at 4:44–46.
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`Figure 4 illustrates a logic block 300 (a block composed of computational
`functional units capable of taking data and producing results with each clock
`pulse) with the addition of a data prefetch unit 401. Id. at 7:6–8, 7:34–35.
`
`Logic block 300 includes computational functional units
`(computational logic) 301, 302, and 303, a control, and data access
`functional units 403 that present data to computational logic 301, 302, and
`303. Id. at 7:25–48, Fig. 4. Data prefetch unit 401 moves data from one
`member of the memory hierarchy 305 to another 308 (a block RAM
`memory). Id. at 7:34–37, Fig. 4. Data prefetch unit 401 operates
`“independently of other functional units 301, 302, and 303 and can therefore
`operate prior to, in parallel with, or after computational logic,” this
`“independence of operation permit[ting] hiding the latency associated with
`obtaining data for use in computation.” Id. at 7:37–42. In addition, data
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`Patent 7,149,867 B2
`prefetch unit 401 may be “operated independently of logic block 300 that
`uses prefetched data.” Id. at 7:45–48. Data prefetch unit 401 deposits data
`into the memory hierarchy, where computational logic 301, 302, and 303
`can access it through data access units. Id. at 7:42–44.
`The ’867 patent explains:
`An important feature of the present invention is that many
`types of data prefetch units can be defined so that the
`prefetch hardware can be configured to conform to the
`needs of the algorithms currently implemented by the
`computational logic. The specific characteristics of the
`prefetch can be matched with
`the needs of
`the
`computational logic and the format and location of data in
`the memory hierarchy.
`Id. at 7:49–55. The ’867 patent provides an example of configuring a data
`prefetch unit depending on the needs of the computational logic. Id. at 7:52–
`62, Figs. 9A–9B (showing an external memory organized into a 128 byte (16
`word) block structure that is optimized for stride 1 access of the cache, and
`explaining that a stride 128 access can result in an inefficient use of
`bandwidth from the memory, since an extra 120 bytes of data is moved for
`every 8 bytes of requested data yielding a 6.25% bandwidth efficiency).
`The ’867 patent also provides an example in which
`data prefetch units 601 are configured to communicate with an
`intelligent memory controller 603 in FIG. 6 and can extract only
`the desired 8 bytes of data, discard the remainder of the memory
`block, and transmit to the data prefetch unit only the requested
`portion of the stride 128 data. The prefetch units 601 then
`delivers that data to the appropriate memory components within
`the memory hierarchy of the logic block 300. . . . An onboard
`memory bank data access unit 303 then delivers the data to
`computational logic 301 when required. The data prefetch units
`[] couple with an intelligent memory controller . . . that supports
`a strided reference pattern, which yields a 100% bandwidth
`efficiency in contrast to the 6.25% efficiency.
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`Patent 7,149,867 B2
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`
`Id. at 8:3–21.
`D. Illustrative Claims
`Among the challenged claims, claims 1, 9, and 13 are independent.
`Independent claims 1, 9, and 13 are reproduced below, with brackets noting
`Petitioner’s identifiers.
`1. [preamble] A reconfigurable processor that instantiates
`an algorithm as hardware comprising:
`[1(a)] a first memory having a first characteristic memory
`bandwidth and/or memory utilization; and
`[1(b)] a data prefetch unit coupled to the first memory,
`[1(c)] wherein the data prefetch unit retrieves only computational
`data required by the algorithm from a second memory of second
`characteristic memory bandwidth and/or memory utilization and
`places the retrieved computational data in the first memory [1(d)]
`wherein the data prefetch unit operates independent of and in
`parallel with logic blocks using the computional[sic] data, and
`[1(e)] wherein at least the first memory and data prefetch unit are
`configured to conform to needs of the algorithm, and [1(f)] the
`data prefetch unit is configured to match format and location of
`data in the second memory.
`
`
`
` [preamble] A reconfigurable hardware system,
`9.
`comprising:
`[9(a)] a common memory; and
`[9(b)] one or more reconfigurable processors that can
`instantiate an algorithm as hardware coupled to the common
`memory, [9(c)] wherein at least one of the reconfigurable
`processors includes a data prefetch unit to read and write only
`data required for computations by the algorithm between the data
`prefetch unit and the common memory [9(d)] wherein the data
`prefetch unit operates independent of and in parallel with logic
`blocks using the computational data, and [9(e)] wherein the data
`prefetch unit is configured to conform to needs of the algorithm
`and [9(f)] match format and location of data in the common
`memory.
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`IPR2020-01449
`Patent 7,149,867 B2
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`13. [preamble] A method of transferring data comprising:
`[13(a)] transferring data between a memory and a data
`prefetch unit in a reconfigurable processor; and
`[13(b)] transferring the data between a computational unit
`and a data access unit, [13(c)] wherein the computational unit
`and the data access unit, and the data prefetch unit are configured
`to conform to needs of an algorithm implemented on the
`computational unit and transfer only data necessary for
`computations by the computational unit, and [13(d)] wherein the
`prefetch unit operates independent of and in parallel with the
`computational unit.
`Ex. 1001, 12:39–54; 13:13–26; 14:1–11.
`E. Evidence
`Petitioner relies on the following references (see Pet. 4–5).
`Reference Exhibit
`Patent/Printed Publication
`Zhang
`1003
`Xingbin Zhang et al., Architectural Adaptation
`for Application-Specific Locality Optimizations,
`published in the Proceedings of the International
`Conference on Computer Design - VLSI in
`Computers and Processors (IEEE, October 12–
`15, 1997), 150–156
`Rajesh Gupta, Architectural Adaptation in
`AMRM Machines, Proceedings of the IEEE
`Computer Society Workshop on VLSI 2000
`(IEEE, April 27–28, 2000), 75–79
`Andrew A. Chien et al., MORPH: A System
`Architecture for Robust High Performance
`Using Customization (An NSF 100 TeraOps
`Point Design Study), Proceedings of Frontiers
`’96 – The Sixth Symposium on the Frontiers of
`Massively Parallel Computing (IEEE, October
`27–31, 1996), 336–345
`
`
`
`10
`
`Gupta
`
`1004
`
`Chien
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`1005
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`IPR2020-01449
`Patent 7,149,867 B2
`F. Prior Art and Asserted Grounds
`Petitioner asserts that claims 1–19 are unpatentable on the following
`grounds (Pet. 5):
`Claims Challenged
`1, 2, 4–8, 13–19
`3, 9–12
`
`References
`Zhang, Gupta
`Zhang, Gupta, Chien
`
`35 U.S.C. §
`103
`103
`
`
`
`III. ANALYSIS
`A. Discretion to Deny Institution Under § 35 U.S.C. 314(a)
`Patent Owner contends that the Board should deny institution under
`35 U.S.C. § 314(a) because of the parallel district court litigation. Prelim.
`Resp. 2–9.
`Under § 314(a), the Director has discretion to deny institution of an
`inter partes review. See 37 C.F.R. § 42.4(a) (“The Board institutes the trial
`on behalf of the Director.”); see Harmonic Inc. v. Avid Tech., Inc., 815 F.3d
`1356, 1367 (Fed. Cir. 2016) (“[T]he [Office] is permitted, but never
`compelled, to institute an [inter partes review] proceeding.”). In exercising
`that discretion, the Board may consider the state of a parallel district court
`proceeding, among other considerations, as a “factor that weighs in favor of
`denying the Petition under § 314(a).” NHK Spring Co. v. Intri-Plex Techs.,
`Inc., IPR2018-00752, Paper 8 at 20 (PTAB Sept. 12, 2018) (precedential)
`(“NHK”); Apple Inc. v. Fintiv, Inc., IPR2020-00019, Paper 11 at 5–6 (PTAB
`Mar. 20, 2020) (precedential) (hereafter “Fintiv”). When considering the
`impact of parallel litigation, the Board seeks, among other things, to
`minimize the duplication of work to resolve the same issue. See NHK, Paper
`8 at 19–20.
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`The Board has identified a nonexclusive list of factors “relat[ing] to
`whether efficiency, fairness, and the merits” favor discretionary denial in
`view of parallel district court litigation. Fintiv, Paper 11 at 6. The factors
`include: 1) whether the court granted a stay or evidence exists that one may
`be granted if a proceeding is instituted; 2) proximity of the court’s trial date
`to the Board’s projected statutory deadline for a final written decision;
`3) investment in the parallel proceeding by the court and the parties;
`4) overlap between issues raised in the petition and in the parallel
`proceeding; 5) whether the petitioner and the defendant in the parallel
`proceeding are the same party; and 6) other circumstances that impact the
`Board’s exercise of discretion, including the merits. Id. at 5–6. In
`evaluating the factors, we take “a holistic view of whether efficiency and
`integrity of the [patent] system are best served by denying or instituting
`review.” Id. at 6.
`1. Factual Background
`On April 24, 2020, Patent Owner filed a complaint against Petitioner
`in the parallel district court litigation alleging, among other things,
`infringement of the ’867 patent. Pet. 2; Ex. 2004. A case management
`conference was held on July 30, 2020, and a Scheduling Order issued on
`August 1, 2020. Ex. 1015. The Petition in this case was filed on August 10,
`2020. Pet. 89. The District Court issued an Amended Scheduling Order on
`November 23, 2020 which, among other things, moved the date of the
`Markman Hearing from February 19, 2021 to March 5, 2021. Ex. 2023 at 2.
`According to the Amended Scheduling Order, fact discovery opens on
`March 6, 2021, and the “Parties [are] to propose [the] remaining schedule
`within two weeks after [the] Markman Hearing.” Id. at 3.
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`2. Analysis
`a) Factor 1: Whether the court granted a stay or evidence exists
`that one may be granted if a proceeding is instituted
`Patent Owner argues that this factor favors denying institution
`because (1) Petitioner has not yet requested a stay; (2) Petitioner has not
`provided any evidence demonstrating that the parallel district court litigation
`would be stayed if this IPR is instituted; and (3) “all available evidence
`indicates that [the District Court] would deny such a stay even if trial were
`instituted.” Prelim. Resp. 3–5; see Sur-Reply 1. In support of its arguments,
`Patent Owner cites several cases before the same District Court where a
`motion to stay was denied. Prelim. Resp. at 3–4. For example, Patent
`Owner contends the facts are the same as those in Kerr Machine Co. d/b/a
`Kerr Pumps v. Vulcan Industrial Holdings, LLC., where the District Court
`denied a stay pending post-grant review. Id. (citing Exs. 2016, 2019, 2020).
`Petitioner asserts “[t]he first Fintiv factor is at least neutral” and
`Patent Owner’s arguments and evidence do not support speculating how the
`District Court might rule here if a stay were to be requested. Reply 1; Pet. 7.
`Petitioner also contends that Kerr is irrelevant because the District Court set
`a trial date by order, and the stay motion was filed before institution. Reply
`1. Petitioner also argues that, despite the stay, in Kerr, the Board did not
`exercise discretion to deny institution under 35 U.S.C. § 324(a). Id. (citing
`Cizion, LLC, d/b/a/ Vulcan Industrial Manufacturing, v. Kerr Machine Co.,
`PGR2020-00065, Paper 10, 21–30.
`We weight this factor as neutral. Currently there is no stay in place,
`and a stay has not been requested. We decline to speculate whether the
`District Court would grant a stay, should Petitioner request one. The District
`Court ruling on motions to stay in other cases provides little bearing on
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`whether it will stay this litigation. Moreover, unlike in Kerr, the District
`Court has not set a trial date by order. See Ex. 2020. Accordingly, in these
`circumstances we will not speculate as to the likelihood of a stay. Therefore,
`we do not find that this factor weighs for or against exercising our discretion
`to deny institution.
`b) Factor 2: proximity of the court’s trial date to the Board’s
`projected statutory deadline for a final written decision
`The parties dispute whether a trial date has been set in the parallel
`district court litigation. See Prelim. Resp. 5; Pet. 7; Reply 1–2; Sur-Reply 1.
`Patent Owner contends, based on an email sent by the District Court on
`August 3, 2020, that trial has been set for November 8, 2021. Prelim. Resp.
`5; Sur-Reply 1; Ex. 2022. Patent Owner, therefore, argues that this factor
`favors denying institution because the “the Final Written Decision would not
`be due until at least February 17, 2022,” so the District Court “would thus
`resolve the relevant validity issues first.” Prelim. Resp. 5.
`Petitioner contends that this factor weighs against denying institution
`because (1) the Amended Scheduling Order does not set a trial date; (2) the
`email only provides an estimated trial date; (3) the date of the Markman
`Hearing has been moved back by about a month since that email was sent;
`and (4) and the estimated trial date is uncertain because the same date has
`been set for at least four other patent cases and the Austin courthouse has
`been closed to trials due to COVID-10. Reply 1–2.
`This factor requires us to consider the proximity in time between two
`dates—the parallel district court litigation’s trial date and the Board’s
`projected statutory deadline for issuing the final written decision. This
`inquiry is a proxy for the likelihood that the trial court will reach a decision
`on validity issues before the Board reaches a final decision. Here, we can
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`only be certain as to one of these dates—the Board’s projected statutory
`deadline for issuing a final written decision.
`Neither the original Scheduling Order (Ex. 1015) nor the Amended
`Scheduling Order (Ex. 2023) explicitly sets a trial date in the parallel district
`court litigation. Both Orders state, “Parties to propose remaining schedule
`within two weeks after Markman Hearing.” See Ex. 2023 at 3; Ex. 1015 at
`3. The email sent by the District Court on August 3, 2020 states “the Court
`has started a new practice of setting the estimated trial date at the [Case
`Management Conference]. Given the number of patents, the Court will set
`the trial date for November 8, 2021. To the extent that the parties would like
`to move the trial date (to an earlier or later date), please feel free to raise that
`at the Markman hearing.” Ex. 2022 (emphasis added).
`We determine that there is no trial date scheduled for the parallel
`district court proceeding. The Amended Scheduling Order does not set a
`trial date, and the email from the District Court, which was sent prior to the
`Amended Scheduling Order, indicates that the November 8, 2021 date is
`“estimated” and may be changed. Whether the parallel district court
`litigation’s trial takes place before, contemporaneously with, or after our
`final written decision statutory deadline involves speculation. Moreover,
`here, where the trial is only estimated to occur about four months before the
`final written decision, concerns about the Board duplicating efforts in
`relation to the parallel district court litigation are diminished. Therefore, we
`find this factor weighs slightly against exercising our discretion to deny
`institution.
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`c) Factor 3: investment in the parallel proceeding by the court
`and the parties
`Patent Owner argues this factor favors denying institution because
`Petitioner has answered the Complaint, the parties have exchanged
`infringement and invalidity contentions, the parties have produced technical
`and financial documents, claim construction proceedings are underway, and
`the Markman hearing is scheduled for March 5, 2021. Prelim. Resp. 6.
`Patent Owner also argues that, like in Fintiv, the Petition was filed between
`the initial case management conference and the Markman hearing. Id.
`Petitioner argues this factor weighs against denying institution
`because the District Court has not issued substantive orders, the institution
`decision will precede the Markman hearing, fact discovery is stayed until
`after the Markman hearing, and the parties will only have provided initial
`invalidity and infringement contentions before an institution decision. Reply
`2; Pet. 7.
`This factor generally focuses on the investment by the District Court
`and the parties at the time of the institution decision. See Fintiv, Paper 11 at
`9 (“The Board also has considered the amount and type of work already
`completed in the parallel litigation by the court and the parties at the time of
`the institution decision.”); see also Sand Revolution II, LLC v. Continental
`Intermodal Grp.–Trucking LLC, IPR2019-01393, Paper 24 at 10–11 (PTAB
`June 16, 2020) (informative) (analyzing the district court’s investment of
`time and resources prior to the institution decision).
`According to the Amended Scheduling Order in the parallel district
`court litigation, preliminary infringement contentions were to be served by
`July 23, 2020, preliminary invalidity contentions were to be served by
`September 17, 2020, the Markman hearing is scheduled for March 5, 2021,
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`and fact discovery opens on March 6, 2021. Ex. 2023 at 2–3. The Amended
`Scheduling Order states that the parties are to propose the remaining
`schedule by March 19, 2021. Id. at 3. As such, dates for expert discovery
`and dispositive motions have not been scheduled at this time. Further, there
`is no evidence in the record that the District Court has substantively
`considered any of the invalidity arguments set forth in the Petition or issued
`any substantive orders related to the ’867 patent. See Fintiv at 9–10 (“If, at
`the time of the institution decision, the district court has not issued orders
`related to the patent at issue in the petition, this fact weighs against
`exercising discretion to deny institution.”). Accordingly, although some
`investment in the parallel district court proceeding has occurred, much
`substantive work towards the invalidity issue remains.
`The timing of filing the petition is also relevant to the analysis. See
`Fintiv, Paper 11 at 11–12. If the petitioner, “faced with the prospect of a
`looming trial date, waits until the district court trial has progressed
`significantly before filing a petition,” that decision “may impose unfair costs
`to a patent owner.” Id. at 11. On the other hand, “[i]f the evidence shows
`that the petitioner filed the petition expeditiously, such as promptly after
`becoming aware of the claims being asserted, this fact has weighed against
`exercising the authority to deny institution.” Id. Here, the Petition was filed
`less than four months after the Complaint was filed in the parallel district
`court litigation, and less than a month after the preliminary infringement
`contentions were served. See Pet. 6; Ex. 2023 at 2. Accordingly,
`Petitioner’s diligence in filing the Petition weighs against exercising
`discretion to deny institution of inter partes review.
`Weighing the facts in this particular case, including the time invested
`in the parallel district court litigation by the parties and the District Court,
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`the schedule in that case, and the timing of the filing of the Petition, we find
`that this factor weighs against exercising our discretion to deny institution.
`d) Factor 4: overlap between issues raised in the petition and in
`the parallel proceeding
`This factor evaluates “concerns of inefficiency and the possibility of
`conflicting decisions” when substantially identical prior art arguments are
`submitted in both the district court and the inter partes review proceedings.
`Fintiv at 12. In particular, “if the petition includes the same or substantially
`the same claims, grounds, arguments, and evidence as presented in the
`parallel processing, this fact has favored denial.” Id. (citing Next Caller, Inc.
`et al. v. Trust ID, Inc. et al., IPR2019-00963, Paper 8 at 11‒12 (PTAB Oct.
`28, 2019) (same grounds asserted in both cases); ZTE (USA) Inc. v. Fractus,
`S.A., IPR2018-01451, Paper 12 at 20 (PTAB Feb. 19, 2019) (same prior art
`and identical evidence and arguments in both cases)).
`Petitioner argues the Petition challenges all claims of the ’867 patent,
`whereas the parallel district court litigation only involves claims 1, 3, 4, 9,
`11, and 12, making this IPR an efficient use of the Board’s resources. Pet. 7
`(citing Ex. 1018). Petitioner also submits “there will not be an overlap in
`issues” because “Petitioner stipulates that if IPR is instituted, Petitioner will
`not raise these same Grounds in the district court proceeding.” Id.
`Patent Owner argues this factor favors denying institution because
`Petitioner’s stipulation does not eliminate the possibility that substantially
`similar art and arguments will be raised by Petitioner in the parallel district
`court litigation, because “Petitioner and its expert argue that the three
`references are related to the ‘same project,’ and it has not committed to drop
`its reliance on that project.” Prelim. Resp. 6 (citing Ex. 1006 ¶ 122).
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`Petitioner’s stipulation somewhat minimizes concerns of duplicative
`efforts between the District Court and the Board, as well as potentially
`conflicting decisions. See Sand Revolution, Paper 24 at 11–12 (a stipulation
`not to pursue overlapping patentability arguments in district court may
`mitigate to some degree the concerns of potential overlap between
`arguments in parallel proceedings). Petitioner’s stipulation is very similar to
`the stipulation proposed by the petitioner in Sand Revolution to address
`concerns regarding duplicative efforts. See Sand Revolution, Paper 24 at
`11–12. Thus, we find that this factor weighs marginally against exercising
`our discretion to deny institution.
`e) Factor 5: whether the petitioner and the defendant are the
`same in the parallel proceeding
`Petitioner and the defendant in the parallel district court litigation are
`the same party. Prelim. Resp. 6; Pet. 2. Therefore, we find that this factor
`weighs in favor of exercising our discretion to deny institution.
`f) Factor 6: other circumstances that impact the Board’s
`exercise of discretion, including the merits
`The final factor is a catch-all that takes into account any other relevant
`circumstances. The decision whether to exercise discretion to deny
`institution under § 314(a) is based on “a balanced assessment of all relevant
`circumstances in the case, including the merits.” Patent Trial and Appeal
`Board Consolidated Trial Practice Guide (November 2019) at 58.1
`Patent Owner argues this factor favors denial because (1) the merits of
`the Petition are too weak to overcome the remaining factors, because, for
`example, Petitioner has failed to establish that the asserted references are
`printed publications, and (2) “[g]iven the substantial overlap between the
`
`1 Available at https://www.uspto.gov/TrialPracticeGuideConsolidated.
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`district court action and this IPR, this proceeding is not an effective and
`appropriate use of the Board’s resources.” Prelim. Resp. 8. Patent Owner
`also argues that “[e]ven if the merits of the asserted grounds were to favor
`institution, ‘the efficiency and integrity of the system . . . taking into account
`the consis