I IIIII IIIIIIII Ill lllll lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`US007446338B2
`
`c12) United States Patent
`Shirasaki et al.
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,446,338 B2
`Nov. 4, 2008
`
`(54) DISPLAY PANEL
`
`(75)
`
`Inventors: Tomoyuki Shirasaki, Higashiyamato
`(JP); Tsuyoshi Ozaki, Fuchu (JP); Jun
`Ogura, Fussa (JP)
`
`(73) Assignee: Casio Computer Co., Ltd., Tokyo (JP)
`
`2003/0146693 Al
`2003/0151355 Al
`2003/0168992 Al
`2003/0193056 Al
`2004/0003939 Al
`2004/0160170 Al
`2004/0165003 Al
`2004/0256617 Al
`
`8/2003
`8/2003
`9/2003
`10/2003
`1/2004
`8/2004
`8/2004
`12/2004
`
`Ishihara et al.
`Hosokawa
`Noguchi et al.
`Takayama et al.
`Nishi et al.
`Sato et al.
`Shirasaki
`Yamada et al.
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 86 days.
`
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`CN
`
`1434668 A
`
`8/2003
`
`(Continued)
`
`OTHER PUBLICATIONS
`
`Related U.S. Appl. No. 11/235,605, filed Sep. 26, 2005; Inventors:
`Satoru Shimoda et al; Title: Display Panel.
`
`(Continued)
`
`Primary Examiner-Long Pham
`(7 4) Attorney, Agent, or Firm-Frishauf, Holtz, Goodman &
`Chick, P.C.
`
`(57)
`
`ABSTRACT
`
`A display panel includes a transistor array substrate which
`has a plurality of pixels and is formed by providing a plurality
`of transistors for each pixel, each of the transistor having a
`gate, a gate insulating film, a source, and a drain. A plurality
`of interconnections are formed to project to a surface of the
`transistor array substrate and arrayed in parallel to each other.
`A plurality of pixel electrodes are provided for each pixel and
`arrayed between the interconnections on the surface of the
`transistor array substrate along the interconnections. Each of
`a plurality of light-emitting layers is formed on each pixel
`electrode. A counter electrode is stacked on the light-emitting
`layer.
`
`22 Claims, 13 Drawing Sheets
`
`(21) Appl. No.: 11/235,579
`
`(22) Filed:
`
`Sep.26,2005
`
`(65)
`
`Prior Publication Data
`
`US 2006/0066535 Al
`
`Mar. 30, 2006
`
`(30)
`
`Foreign Application Priority Data
`
`Sep.29,2004
`
`(JP)
`
`............................. 2004-283824
`
`(51)
`
`Int. Cl.
`HOJL 29/04
`(2006.01)
`(52) U.S. Cl. .............................. 257/72; 257/40; 257/79
`( 58) Field of Classification Search . ... ... ... ... .. ... . 257 / 40,
`257/72, 79
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,684,365 A
`6,297,589 Bl
`6,717,357 B2
`6,839,057 B2
`7,358,529 B2
`7,402,948 B2
`2003/0047730 Al
`2003/0137325 Al
`
`11/1997 Tang et al.
`10/2001 Miyaguchi et al.
`4/2004 Okuyama et al.
`1/2005 Iguchi
`4/2008 Childs et al.
`7/2008 Yamazaki et al.
`3/2003 Konuma
`7/2003 Yamazaki et al.
`
`4
`,------A----..
`YgYb Yr
`C ! )
`111111
`
`9P
`I
`
`~
`(
`..
`
`r-p
`91 ' '
`--3
`,_
`Pg
`,,
`X
`89
`
`Pb
`:~ z
`90
`
`Pr
`91 '
`3-
`Pg
`X '
`89
`
`Pb
`
`I
`
`-
`
`I
`
`R
`
`G
`
`B
`
`-
`
`R
`
`G
`
`B
`
`1
`
`/
`
`R
`
`G
`
`B
`
`R
`
`G
`
`B
`
`-
`
`4
`,------A----..
`YgYb Yr
`/)
`111111
`··n ,
`'I I
`
`·1 f,
`
`I.
`'I I.
`~i
`'I I.
`
`·1 I
`
`I
`1!
`
`·n
`
`Pr
`
`Pg
`
`-3
`
`Pb
`
`Pr
`
`Pg
`-3
`
`Pb
`
`I
`n
`
`i
`
`IPR2020-01275
`Apple EX1001 Page 1
`
`

`

`US 7,446,338 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`2005/0062409 Al
`2005/0073264 Al
`2005/0088086 Al
`2005/0258741 Al
`2006/0066219 Al
`
`3/2005 Yamazaki et al.
`4/2005 Matsumoto
`4/2005 Park et al.
`11/2005 Kim et al.
`3/2006 Shimoda et al.
`
`FOREIGN PATENT DOCUMENTS
`
`CN
`EP
`EP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`1437177 A
`1 331 666 A2
`1 349 208 Al
`8-330600 A
`2002-195008 A
`2002-352963 A
`2003-076327 A
`2003-186420 A
`2003-288994 A
`2003-317971 A
`2004-258172 A
`
`8/2003
`7/2003
`10/2003
`12/1996
`7/2001
`12/2002
`3/2003
`7/2003
`10/2003
`11/2003
`9/2004
`
`KR
`KR
`TW
`TW
`TW
`TW
`WO
`WO
`
`2002-0000875 A
`10-2004-0051611 A
`591574 A
`521336 A
`584824 A
`594628 A
`WO 03/079441 Al
`2004/019314 Al
`
`1/2002
`6/2004
`5/2002
`2/2003
`4/2004
`6/2004
`9/2003
`3/2004
`
`OTHER PUBLICATIONS
`
`Japanese Office Action (and English translation thereof) dated Apr.
`30, 2008, issued in a counterpart Japanese Application.
`Chinese Office Action (and English translation thereof) dated Jun. 6,
`2008, issued in a counterpart Chinese Application.
`Chinese Office Action (and English translation thereof) dated Jun. 6,
`2008, issued in related U.S. Appl. No. 11/235,605 in counterpart
`Chinese Application No.2005800156930.
`Japanese Office Action (and English translation thereof) dated Jun.
`10, 2008, issued in related U.S. Appl. No. 11/235,605 in counterpart
`Japanese Application No. 2004-283963.
`
`IPR2020-01275
`Apple EX1001 Page 2
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 1 of 13
`
`US 7,446,338 B2
`
`1 /
`
`4
`,---A---,.
`Yg Yb Yr
`90
`Z
`,)
`T
`l
`7 7
`--------------n f1-H™-- -----------··n
`
`1
`
`=~:1~":I..IITI:rr::====~R======~==-LJP! TIIII~~~R~===~:J.J~-Pr
`i I
`i
`I !
`I
`: I
`fl---Pg
`~ -3
`
`: I
`I :
`z ~ I_++++++-------------
`I
`I!'-++++··--·-----------
`~HH+------------··n fr11t+++- -----------··n
`:~=Ii:
`I!
`i I
`I !
`~~Pg
`ig~H
`: I
`II- -3
`
`11:
`i
`i
`x,~
`89 ~~~~~~~~~~~~~~~~
`1 I
`. I
`.
`Ii
`Pb-,:'
`~~~_JI:
`I
`
`R
`
`G
`
`B
`
`t-Pr
`i
`I
`
`~-Pb
`
`R
`
`G
`
`B
`
`I\
`
`t
`
`I'
`
`11 I
`
`I I
`
`· · - - · - - - - - - - '--tttHt--------------
`
`FIG.1
`
`Pb-v-
`
`B
`
`B
`
`-Pb
`I.I:
`rf'-
`
`90~~~~~~~~~~~~~~~~
`
`I
`
`1-l.+
`
`:g-~
`
`X,I\
`89
`
`G
`
`G
`
`11:
`j
`
`11
`
`IPR2020-01275
`Apple EX1001 Page 3
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 2 of 13
`
`US 7,446,338 B2
`
`89
`
`-----F 90
`
`Y·
`J
`
`22g
`
`22s
`
`23d
`/23
`
`21g
`
`21d
`
`A
`
`L
`
`21s
`
`;
`
`21
`
`24
`
`24A
`
`23g
`
`23s
`
`248
`A
`
`~P-·
`1,J
`
`ls
`
`20
`
`20c
`
`91
`
`FIG.2
`
`IPR2020-01275
`Apple EX1001 Page 4
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 3 of 13
`
`US 7,446,338 B2
`
`C\I
`C\I
`
`l:!1_:_ -
`
`;_ ---~ ----------------------------------:
`( ~
`
`i;; ~ -
`
`~ ) '. _________ _
`
`II~ : -------------
`- ·
`
`C\I
`M .----- - ----
`0)
`
`~
`----- ~
`
`---- - -- --""\- - ------- - - -- - - - -- ------- "I
`
`--
`
`i
`:
`:
`
`C)
`M--=:::.._::::t,-t----l-.l..1.1....ll-l-l
`-----i-
`C\I
`
`-LL
`
`'
`
`~
`
`U, _/LA
`
`N
`~
`co
`1
`)
`~__/
`~f ---i:++-+~H+-+e-~~--+~-- -~ ~ ~--8
`aaa. _ ill ex,
`..__
`i
`L.;a._ - ~
`
`C) a.
`
`IPR2020-01275
`Apple EX1001 Page 5
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 4 of 13
`
`US 7,446,338 B2
`
`><~" 'f I
`;;;~=------ V
`' --------------------------------------- C.J ti' ---:./----------
`~ ~ :::::::::: -6/
`gi ---- _ ... ; . _ .... -· . \fi: ' '
`, '
`{: ' ....
`- < ( l
`-----'
`
`en N
`CIO en
`~ )
`
`N
`N
`
`./gi
`
`I
`
`-
`
`,
`
`-
`
`N
`Nc,u,
`
`/
`
`-
`
`N
`
`,i::t
`,i::t
`N N
`
`~
`
`;
`
`!I
`~
`
`'
`
`i
`C)
`('I) """"8 .... __
`:
`~I-----·
`N
`~
`
`:
`
`U)
`('I) --,:c.,
`N
`
`r
`:
`
`N\.. r ----· C
`
`i--__
`
`'
`:
`
`t-...._--
`
`"'-'
`
`-LL
`
`' ' ' '
`
`'
`
`co
`CO
`)
`'
`i ,__r-tl___,'-,
`1 LJ---1+--t~
`
`co
`CO
`)
`._rtl--t--,
`
`c,_.)-t
`~
`N
`'C _..,.--
`N
`
`co
`
`(0
`0)
`
`~r-: 4 ---+11-Hj Hl-+++-+L_J---++------
`ill
`
`~
`
`0) --.
`
`i
`
`:
`
`i
`
`:
`
`-
`
`~ ~ ~::::~! ::::::::::
`.c
`----------
`>-
`
`)
`... a.
`
`~.: --~:--- - l====J ,'
`, / 1() -~:~~~~ ~t==========:j
`'
`)
`.0 a.
`
`)
`C) a.
`
`IPR2020-01275
`Apple EX1001 Page 6
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 5 of 13
`
`US 7,446,338 B2
`
`~ ___,,,,==t=t:ttt---hHrn
`N
`,
`' ' ' '
`'
`
`'
`' ' ·-·
`
`,..
`N~
`
`Lt)
`•
`
`(!J -LL
`
`' ' '' '' '' : :
`
`:_J
`
`u,
`
`)
`
`.c
`a.
`
`IPR2020-01275
`Apple EX1001 Page 7
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 6 of 13
`
`US 7,446,338 B2
`
`.c
`c..~
`
`T"" c.o
`T""
`O'>
`
`Lt)
`Lt)
`
`X
`
`T""
`N
`
`N
`M
`
`T""
`M
`
`M
`N
`
`C'CS
`T""
`N
`
`co
`•
`c.:, -u.
`
`0
`Lt)
`
`IPR2020-01275
`Apple EX1001 Page 8
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 7 of 13
`
`US 7,446,338 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi, 1 TO Pi, n
`
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME!
`
`LIGHT EMISSION
`PERIOD OF PIXEL
`! CIRCUITS Pi, 1 TO Pi, n
`
`OF SCAN LINE Xi _11_1
`
`VOLTAGE LEVEL
`
`-
`
`VOLTAGE LEVEL OF FEED VH
`INTERCONNECTION 90
`AND SUPPLY LINE Zi
`
`V_L _____ :
`
`:
`
`Ii
`Ii
`;-----;,--------
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT Pi, i
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi, i
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi+1
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINE Zi+1
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi+1, i
`
`LIGHT EMISSION
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1, 1 TO Pi+1, n
`
`LIGHT EMISSION
`PERIOD OF PIXEL
`;
`!CIRCUITS Pi+1 1 TO Pi+1 n
`'
`'
`'
`
`LIGHT EMISSION
`
`FIG.7
`
`IPR2020-01275
`Apple EX1001 Page 9
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 8 of 13
`
`US 7,446,338 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi, 1 TO Pi, n
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME
`OF PIXEL CIRCUITS
`Pi, 1 TO Pi, n
`
`!
`
`LIGHT EMISSION PERIOD OF
`GIVEN FRAME OF PIXEL
`CIRCUITS Pi, 1 TO Pi, n
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
`
`VH
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINES
`Z1 TO Zm
`
`VL
`
`I
`
`___ I
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT Pi, i
`
`CURRENTVALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi,i
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi+1
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT Pi+1, i
`
`LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`-
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1, 1 TO Pi+1, n
`
`.. ,
`
`LIGHT EMISSION
`j
`:
`PERIOD OF
`PRECEDING FRAME !
`OF PIXEL CIRCUITS j
`Pi+1, 1 TO Pi+1, n
`:
`
`LIGHT EMISSION
`PERIOD OF GIVEN
`FRAME OF PIXEL
`CIRCUITS Pi+1 1 TO
`Pi+1,n
`'
`
`CURRENT VALUE OF - - -.... ._ __ .... - - ._ _ ____,1E~l~rlbNl __ _.l
`
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi+1, j
`
`FIG.8
`
`IPR2020-01275
`Apple EX1001 Page 10
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 9 of 13
`
`US 7,446,338 B2
`
`1.ox10-6
`
`6.ox10-6
`
`s.ox10-6
`
`Id [A]
`
`4.0X1 o-6
`
`3.ox10-6
`
`2.ox10-6
`
`1.ox10-6
`
`0
`0
`
`~
`
`:
`
`)11
`J/
`
`)
`
`'(
`
`/
`
`1
`
`2 3
`
`4
`
`5
`
`6 7
`
`8
`
`VP1 VP2'VP2
`VP3vp3,
`I
`I
`)
`. . .
`//
`I
`. . .
`.
`\
`\J ~ .
`'1
`--v Li
`\ .
`. . . .
`T
`/ I Ji 'I
`.
`. .
`I
`. . . . .
`I/ I
`I
`I
`.
`. .
`J
`J
`I
`i ~/
`!./
`/-;-
`~· ........ ~/ ~
`l
`. . . . .
`/
`1/,'
`.. /
`l I
`.
`..
`.,.
`I~
`./
`/'
`\ ...
`,•
`9 10 11 12 13 14 15
`
`:
`
`P4
`V
`
`.
`
`V
`P4'
`
`·--
`
`:---4
`
`Vds [V]
`
`---lds_max
`- - - · - lds_mid
`•••·•··•····•••· lel
`---·-···- Vds=Vgs:Vpo+Vth
`-"-··-Vpo
`
`FIG.9
`
`IPR2020-01275
`Apple EX1001 Page 11
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 10 of 13
`
`US 7,446,338 B2
`
`5
`
`4
`
`3
`
`2
`
`1
`
`MAXIMUM
`VOLTAGE
`DROP [V]
`
`32-INCH PANEL
`
`......
`
`.... ,..i--
`...... ....
`.....
`.....
`..... ......
`,_ .. ......
`
`...... .....
`.....
`......
`...... ......
`..... ~ ...
`......
`
`0
`0
`
`1
`
`2
`
`3
`
`6
`5
`4
`p/S [Q/cm]
`
`7
`
`8
`
`9
`
`10
`
`FIG.10
`
`IPR2020-01275
`Apple EX1001 Page 12
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 11 of 13
`
`US 7,446,338 B2
`
`32-INCH PANEL
`
`1.ox107
`
`1.ox106
`
`CURRENT
`DENSITY
`[A/cm2]
`
`1.0X105
`
`\ '
`. .
`,.
`' ~
`~"""
`
`I
`
`'
`
`I
`
`r-... ...... ~
`""""
`
`I
`
`--
`
`1.ox104
`
`1.0X103
`
`0
`
`50
`
`100
`150
`200
`SECTIONAL AREA S [µm2]
`
`250
`
`FIG.11
`
`IPR2020-01275
`Apple EX1001 Page 13
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 12 of 13
`
`US 7,446,338 B2
`
`40-INCH PANEL
`
`5
`
`4
`
`3
`
`2
`
`1
`
`MAXIMUM
`VOLTAGE
`DROP [V]
`
`,, , ..
`,,
`,,
`.,
`
`,-,,
`,,,,
`
`~, -~
`
`,,,
`,,
`,,
`
`,,,;
`
`L•,
`i.,'
`,i..,
`.,,i.,
`
`_,i.,
`
`,., i,'
`
`, i, i,
`_,
`
`0
`0
`
`1
`
`2
`
`3
`
`6
`5
`4
`p/S [Q/cm]
`
`7
`
`8
`
`9
`
`10
`
`FIG.12
`
`IPR2020-01275
`Apple EX1001 Page 14
`
`

`

`U.S. Patent
`
`Nov. 4, 2008
`
`Sheet 13 of 13
`
`US 7,446,338 B2
`
`1.0X107
`
`1.ox106
`
`I ' 1
`\
`
`'
`'
`
`CURRENT
`DENSITY
`[A/cm2]
`
`1.0X105
`
`1.0X104
`
`1.0X103
`
`0
`
`40-INCH PANEL
`
`'" "-.........
`
`...... ........
`
`--... ~ ..... ..... ~ ~ -
`
`50
`
`150
`200
`100
`SECTIONAL AREA S [µm2]
`
`250
`
`FIG.13
`
`IPR2020-01275
`Apple EX1001 Page 15
`
`

`

`US 7,446,338 B2
`
`1
`DISPLAY PANEL
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is based upon and claims the benefit of
`priority from prior Japanese Patent Application No. 2004-
`283824, filed Sep. 29, 2004, the entire contents of which are
`incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a display panel using a
`light-emitting element.
`2. Description of the Related Art
`Organic electroluminescent display panels can roughly be
`classified into passive driving types and active matrix driving
`types. Organic electroluminescent display panels of active
`matrix driving type are more excellent than those of passive 20
`driving type because of high contrast and high resolution. In
`a conventional organic electroluminescent display panel of
`active matrix display type described in, e.g., Jpn. Pat. Appln.
`KOKAI Publication No. 8-330600, an organic electrolumi(cid:173)
`nescent element (to be referred to as an organic EL element 25
`hereinafter), a driving transistor which supplies a current to
`the organic EL element when a voltage signal corresponding
`to image data is applied to the gate, and a switching transistor
`which performs switching to supply the voltage signal corre(cid:173)
`sponding to image data to the gate of the driving transistor are 30
`arranged for each pixel. In this organic electroluminescent
`display panel, when a scan line is selected, the switching
`transistor is turned on. At this time, a voltage of level repre(cid:173)
`senting the luminance is applied to the gate of the driving
`transistor through a signal line. The driving transistor is 35
`turned on. A driving current having a magnitude correspond(cid:173)
`ing to the level of the gate voltage is supplied from the power
`supply to the organic EL element through the drain-to-source
`path of the driving transistor. The organic EL element emits
`light at a luminance corresponding to the magnitude of the 40
`current. In the period from the end of scan line selection to the
`next scan line selection, the level of the gate voltage of the
`driving transistor is continuously held even after the switch(cid:173)
`ing transistor is turned off. Hence, the organic EL element
`emits light at a luminance corresponding to the magnitude of 45
`the driving current corresponding to the voltage.
`To drive the organic electroluminescent display panel, a
`driving circuit is provided around it to apply a voltage to the
`scan lines, signal lines, and power supply lines laid on the
`organic electroluminescent display panel.
`In the conventional organic electroluminescent display
`panel of active matrix driving type, interconnections such as
`a power supply line to supply a current to an organic EL
`element are patterned simultaneously in the thin-film transis-
`tor patterning step by using the material of a thin-film tran- 55
`sistor such as a switching transistor or driving transistor.
`More specifically, in manufacturing the organic electrolumi(cid:173)
`nescent display panel, a conductive thin film as a prospective
`electrode of a thin-film transistor is subjected to photo lithog(cid:173)
`raphy and etching to form the electrode of a thin-film transis- 60
`tor from the conductive thin film. At the same time, an inter(cid:173)
`connection connected to the electrode is also formed. For this
`reason, when the interconnection is formed from the conduc(cid:173)
`tive thin film, the thickness of the interconnection equals that
`of the thin-film transistor.
`However, the electrode of the thin-film transistor is
`designed assuming that it functions as a transistor. In other
`
`2
`words, the electrode is not designed assuming that it supplies
`a current to a light-emitting element. Hence, the thin-film
`transistor is thin literally. If a current is supplied from the
`interconnection to a plurality of light-emitting elements, a
`5 voltage drop occurs, or the current flow through the intercon(cid:173)
`nection delays due to the electrical resistance of the intercon(cid:173)
`nection. To suppress the voltage drop or interconnection
`delay, the resistance of the interconnection is preferably low.
`If the resistance of the interconnection is reduced by making
`10 a metal layer serving as the source and drain electrodes of the
`transistor or a metal layer serving as the gate electrode thick,
`or patterning the metal layers considerably wide to suffi(cid:173)
`ciently flow the current through the metal layers, the overlap
`area of the interconnection on another interconnection or
`15 conductor when viewed from the upper side increases, and a
`parasitic capacitance is generated between them. This retards
`the flow of the current. Alternatively, in a so-called bottom
`emission structure which emits EL light from the transistor
`array substrate side, light emitted from the EL elements is
`shielded by the interconnections, resulting in a decrease in
`opening ratio, i.e., the ratio of the light emission area. If the
`gate electrode of the thin-film transistor is made thick to lower
`the resistance, a planarization film ( corresponding to a gate
`insulating film when the thin-film transistor has, e.g., an
`inverted stagger structure) to eliminate the step of the gate
`electrode must also be formed thick. This may lead to a large
`change in transistor characteristic. When the source and drain
`electrodes are formed thick, the etching accuracy of the
`source and drain electrodes degrades. This may also
`adversely affect the transistor characteristic.
`
`BRIEF SUMMARY OF THE INVENTION
`
`50
`
`It is an object of the present invention to satisfactorily drive
`a light-emitting element while suppressing any voltage drop
`and signal delay.
`A display panel according to a first aspect of the present
`invention comprises: a transistor array substrate which has a
`plurality of pixels and is formed by providing a plurality of
`transistors for each pixel, each of the transistor having a gate,
`a gate insulating film, a source, and a drain;
`a plurality of interconnections which are formed to project
`to a surface of the transistor array substrate and arrayed in
`parallel to each other;
`a plurality of pixel electrodes which are provided for each
`pixel and arrayed between the interconnections on the surface
`of the transistor array substrate along the interconnections;
`a plurality oflight-emitting layers each of which is formed
`on each pixel electrode; and
`a counter electrode which is stacked on the light-emitting
`layer.
`A display panel according to a second aspect of the present
`invention comprises: a plurality of pixel electrodes;
`a plurality of light-emitting layers which are provided for
`said plurality of pixel electrodes, respectively;
`a counter electrodes which is provided for said plurality of
`light-emitting layers respectively;
`a plurality of driving transistors which are connected to
`said plurality of pixel electrodes, respectively;
`a plurality of switch transistors each of which supplies a
`write current between a source and drain of a corresponding
`one of said plurality of driving transistors;
`a plurality of holding transistors each of which holds a
`voltage between the source and a gate of a corresponding one
`65 of said plurality of driving transistors;
`a plurality of feed interconnections which are formed from
`a conductive layer different from a layer serving as sources,
`
`IPR2020-01275
`Apple EX1001 Page 16
`
`

`

`US 7,446,338 B2
`
`10
`
`20
`
`3
`drains, and gates of said plurality of driving transistors, said
`plurality of switch transistors, and said plurality of holding
`transistors and connected to the drains of said plurality of
`driving transistors;
`a plurality of select interconnections each of which selects 5
`the switch transistor; and
`a plurality of connnon interconnections each of which is
`connected to the counter electrode.
`A display panel according to a third aspect of the present
`invention comprises: a plurality of pixel electrodes;
`a light-emitting layer which is provided for each of said
`plurality of pixel electrodes;
`a counter electrode which is provided for the light-emitting
`layer;
`a driving transistor which is connected to each of said 15
`plurality of pixel electrode;
`a switch transistor which supplies a write current between
`a source and drain of the driving transistor;
`a holding transistor which holds a voltage between the
`source and gate of the driving transistor;
`a select interconnection which selects the switch transistor;
`a connnon interconnection which is formed from a con(cid:173)
`ductive layer different from a layer serving as sources and
`drains and a layer serving as gates of the driving transistor, the
`switch transistor, and the holding transistor and connected to 25
`the counter electrode; and
`a feed interconnection which is formed from a conductive
`layer different from the layer serving as the sources, drains,
`and gates of the driving transistor, the switch transistor, and
`the holding transistor and connected to the drain of the driving 30
`transistor and is thicker than the common interconnection.
`A display panel according to a fourth aspect of the present
`invention comprises: a transistor array substrate which is
`formed by providing a plurality of transistors for each pixel,
`each transistor having a gate, a gate insulating film, and a 35
`source/ drain;
`a plurality of pixel electrodes which are provided in a
`plurality of rows on the transistor array substrate;
`a first light-emitting layer which is provided on each of said
`plurality of pixel electrodes of a first row to emit light of a first 40
`color;
`a second light-emitting layer which is provided on each of
`said plurality of pixel electrodes of a second row to emit light
`of a second color;
`a third light-emitting layer which is provided on each of 45
`said plurality of pixel electrodes of a third row to emit light of
`a third color;
`a counter electrode which is provided on the first light(cid:173)
`emitting layer, the second light-emitting layer, and the third
`light-emitting layer;
`a select interconnection which has a top higher than first
`light-emitting layer, the second light-emitting layer, and the
`third light-emitting layer and selects at least one of said plu(cid:173)
`rality of transistors;
`a connnon interconnection which has a top higher than first 55
`light-emitting layer, the second light-emitting layer, and the
`third light-emitting layer and is connected to the counter
`electrode; and
`a feed interconnection which has a top higher than first
`light-emitting layer, the second light-emitting layer, and the 60
`third light-emitting layer and is connected to said plurality of
`pixel electrodes of said plurality of transistors.
`According to the present invention, since the interconnec(cid:173)
`tions can be made thick, the resistance of the interconnections
`can be reduced. When the resistance of the interconnections 65
`decreases, the signal delay and voltage drop can be sup(cid:173)
`pressed.
`
`4
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`FIG. 1 is a plan view showing four pixels ofa display panel
`
`1;
`
`FIG. 2 is an equivalent circuit diagram of a sub-pixel P of
`the display panel 1;
`FIG. 3 is a plan view showing the electrodes of a red
`sub-pixel Pr;
`FIG. 4 is a plan view showing the electrodes of a green
`sub-pixel Pg;
`FIG. 5 is a plan view showing the electrodes of a blue
`sub-pixel Pb;
`FIG. 6 is a sectional view taken along a line VI-VI in FIGS.
`3 to 5;
`FIG. 7 is a timing chart for explaining a driving method of
`the display panel 1;
`FIG. 8 is a timing chart for explaining another driving
`method of the display panel 1;
`FIG. 9 is a graph showing the current vs. voltage charac(cid:173)
`teristic of a driving transistor 23 and organic EL element 20 of
`each sub-pixel;
`FIG. 10 is a graph showing the correlation between the
`maximum voltage drop and the interconnection resistivity
`p/sectional area S of a feed interconnection 90 and common
`interconnection 91 of a 32-inch display panel 1;
`FIG. 11 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec(cid:173)
`tion 90 and connnon interconnection 91 of the 32-inch dis(cid:173)
`play panel 1;
`FIG. 12 is a graph showing the correlation between the
`maximum voltage drop and the interconnection resistivity
`p/sectional area S of the feed interconnection 90 and common
`interconnection 91 of a 40-inch display panel 1; and
`FIG. 13 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec(cid:173)
`tion 90 and connnon interconnection 91 of the 40-inch dis(cid:173)
`play panel 1.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`The best mode for carrying out the present invention will be
`described below with reference to the accompanying draw(cid:173)
`ings. Various kinds oflimitations which are technically pref(cid:173)
`erable in carrying out the present invention are added to the
`embodiments to be described below. However, the spirit and
`scope of the present invention are not limited to the following
`embodiments and illustrated examples. In the following
`description, the term "electroluminescence" will be abbrevi-
`50 ated as EL.
`
`[Planar Layout of Display Panel]
`FIG. 1 is a schematic plan view showing adjacent four of a
`plurality of pixels 3 provided on an insulating substrate 2 of a
`display panel 1 which is operated by the active matrix driving
`method. In the display panel 1, as for the pixels in the column
`direction, a plurality of red sub-pixels Pr are arrayed in the
`horizontal direction (row direction). A plurality of green sub(cid:173)
`pixels Pg are arrayed in the horizontal direction. A plurality of
`blue sub-pixels Pb are arrayed in the horizontal direction. As
`for the sequence in the vertical direction ( column direction),
`the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb
`are repeatedly arrayed in this order. The 1-dot red sub-pixel
`Pr, 1-dot green sub-pixel Pg, and 1-dot blue sub-pixel Pb are
`combined to form one pixel 3. Such pixels 3 are arrayed in a
`matrix. In the following description, an arbitrary one of the
`red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb is
`
`IPR2020-01275
`Apple EX1001 Page 17
`
`

`

`US 7,446,338 B2
`
`5
`
`6
`direction between the select interconnection 89 and the adja(cid:173)
`cent feed interconnection 90. When an insulating film which
`is sufficiently thick so no parasitic capacitance is generated is
`inserted between the signal line group 4 and the electrode or
`interconnection located above the signal line group 4, the
`signal line group 4 may overlap the sub-pixel electrode 20a
`connected to it when viewed from the upper side. In addition,
`the signal line group 4 may overlap the sub-pixel electrode
`20a of one sub-pixel adjacent to the sub-pixel connected to
`10 the signal line group 4 when viewed from the upper side.
`When the display panel 1 has a bottom emission structure, the
`signal line group 4 preferably does not overlap the sub-pixel
`electrode 20a when viewed from the upper side.
`When m and n are integers (m~2, n~2), m pixels 3 are
`15 arrayed in the vertical direction, and n pixels 3 are arrayed in
`the horizontal direction, the sub-pixel electrodes 20a equal in
`number to the sub-pixels of one colunm, i.e., (3xm) sub-pixel
`electrodes 20a are arrayed in the vertical direction. The sub(cid:173)
`pixel electrodes 20a equal in number to the sub-pixels of one
`20 row, i.e., n sub-pixel electrodes 20a are arrayed in the hori(cid:173)
`zontal direction. In this case, n signal line groups 4 are
`arranged, and m scan lines X, m supply lines Z, m select
`interconnections 89, m feed interconnections 90, and m com(cid:173)
`mon interconnections 91 are arranged. The total number of
`25 select interconnections 89, feed interconnections 90, and
`common interconnections 91, which also serve as partition
`walls to prevent leakage of an organic compound-containing
`solution as a perspective organic EL layer 20b of the organic
`EL element 20 (to be described later) from the sub-pixels of
`30 one row, is (3xm). To partition the organic compound-con(cid:173)
`taining solution in all rows for the sub-pixels of each row, the
`total number of select interconnections 89, feed interconnec(cid:173)
`tions 90, and common interconnections 91 must be (3xm+ 1 ).
`To do this, a (3xm+l)th partition dummy interconnection
`35 having the same height and same length as the common
`interconnection 91 is arranged in the row direction in parallel
`to the select interconnections 89, feed interconnections 90,
`and common interconnections 91. The select interconnec(cid:173)
`tions 89, feed interconnections 90, and common interconnec-
`40 tions 91 are used as partition walls, their top portions are
`higher than the organic EL layer 20b and the liquid level of the
`organic compound-containing solution.
`
`5
`represented by a sub-pixel P. The description of the sub-pixel
`P applies to all the red sub-pixel Pr, green sub-pixel Pg, and
`blue sub-pixel Pb.
`Three signal lines Yr, Yg, and Yb running in the vertical
`direction form one set. The combination of the three signal
`lines Yr, Yg, and Yb is called a signal line group 4. In each
`signal line group 4, the three signal lines Yr, Y g, and Yb are
`arranged close to each other. The interval between the adja(cid:173)
`cent signal line groups 4 is wider than that between the adja(cid:173)
`cent signal lines Yr, Yg, and Yb in each signal line group 4.
`One signal line group 4 is provided in correspondence with
`one colunm of pixels 3 in the vertical direction. That is, the
`sub-pixels Pr, Pg, and Pb in one colunm arrayed in the vertical
`direction are connected to the signal lines Yr, Y g, and Yb of
`one signal line group 4, respectively.
`The first signal line Yr supplies a signal to all the red
`sub-pixels Pr of the colunm of pixels 3 in the vertical direc(cid:173)
`tion. The second signal line Y g supplies a signal to all the
`green sub-pixels Pg of the colunm of pixels 3 in the vertical
`direction. The third signal line Yb supplies a signal to all the
`blue sub-pixels Pb of the colunm of pixels 3 in the vertical
`direction.
`A plurality of scan lines X run in the horizontal direction.
`A plurality of supply lines Z, a plurality of select intercon(cid:173)
`nections 89, a plurality of feed interconnections 90, and a
`plurality of common interconnections 91 are provided in
`parallel to the scan lines X. One scan line X, one supply line
`Z, one feed interconnection 90, one select interconnection 89,
`and one common interconnection 91 are provided in corre(cid:173)
`spondence with one line of pixels 3 in the horizontal direc(cid:173)
`tion. More specifically, the common interconnection 91 is
`arranged between the red sub-pixel Pr and the green sub-pixel
`Pg which are adjacent in the vertical direction. The scan line
`X and select interconnection 89 are arranged between the
`green sub-pixel Pg and the blue sub-pixel Pb which are adja(cid:173)
`cent in the vertical direction. The supply line Z and feed
`interconnection 90 are arranged between the blue sub-pixel
`Pb and the red sub-pixel Pr of the adjacent pixel 3. The select
`interconnections 89 and feed interconnections 90 have the
`same thickness.
`The scanlineX supplies a signal to all the sub-pixels Pr, Pg,
`and Pb of the pixels 3 of one line arrayed in the horizontal
`direction. The supply line Z also supplies a signal to all the
`sub-pixels Pr, Pg, and Pb of the pixels 3 of one line arrayed in
`the horizontal direction.
`When viewed from the upper side, the select interconnec(cid:173)
`tion 89 overlaps the scan line X in the running direction and is
`thus electrically connected to the scan line X. The feed inter(cid:173)
`connection 90 overlaps the supply line Zin the running direc(cid:173)
`tion and is thus electrically connected to the supply line Z.
`The color of each the sub-pixels Pr, Pg, and Pb is deter(cid:173)
`mined by the color of light emitted from an organic EL
`element 20 (FIG. 2) (to be described later). The position of
`each of the sub-pixels Pr, Pg, and Pb, which is represented by
`a rectangle long in the horizontal direction in FIG.1, indicates 55
`the position of a sub-pixel electrode 20a (in FIG. 2) serving as
`an anode of the organic EL element 20. More specifically,
`when the entire display panel 1 is viewed from the upper side,
`the plurality of sub-pixel electrodes 20a are arrayed in a
`matrix. The 1-dot sub-pixel Pis determined by one sub-pixel 60
`electrode 20a. Hence, the plurality of sub-pixel electrodes
`20a are arrayed in the horizontal direction between the feed
`interconnection 90 and the adjacent common interconnection
`91. Said plurality of sub-pixel electrodes 20a are arrayed in
`the horizontal direction between the common interconnection 65
`91 and the adjacent select interconnection 89. Said plurality
`of sub-pixel electrodes 20a are arrayed in the horizontal
`
`45
`
`[Circuit Arrangement of Sub-Pixel]
`The circuit arrangement of the first to third sub-pixels Pr,
`Pg, and Pb will b