CMOS RF Receiver Design for Wireless LAN Applications
`
`Behzad Razavi
`Electrical Engineering Department
`University of California, Los Angeles
`
`S N R = 174 dBm - IOlog(22 MI-Iz) - 80 dBm = 20.6 dB.
`Assuming S N K R, 10 dB for the required FER and 2 dB of
`loss in the front-end band-select filter, we arrive at a noise
`figure of 8.6 dB for the receiver.
`Another specification of the standard is an adjacent channel
`(blocker) rejection of 40 dB when the desired channel is at
`-74 dBm. This translates to a 1-dB compression point o f
`roughly -30 dBm.
`
`111. ARCHITECTURE AND CIRCUIT DESIGN
`The receiver employs a direct-conversion architccture, a
`choice particularly suited to the DS-SS standard because of
`the wide channel bandwidth. The two principal difficulties
`of direct conversion, namely, dc offsets and nicker noise, are
`treated so as to impact the performance negligibly. Other
`issues [2, 31 are resolved by circuit techniques. Note that local
`oscillator (LO) leakage to theantenna is less troublesome here
`if it does not desensitize other receivers because it simply
`appears as a “jammer” and its cffect is suppressed by the
`spread-spectrum nature of the communication scheme.
`Fig. I shows the receiver architecture. In addition to a Iow-
`
`Baseband
`-..~ .
`
`Abstract
`This paper describes design techniques for RE’ CMOS re-
`ceivers operating in the 2.4-GHz band. A direct-conversion
`receiver targetting spread-spectrum wireless LAN applica-
`tions employs partial channel selection filtering, dc offset
`removal, and baseband amplification. Fabricated in a 0.6-
`pm CMOS technology, the receiver achieves a noise figure
`of8.3dB, 1 4 of-9dBm, IPzoft22dBm,andvoltagegain
`of 34 dB while dissipating 80 mW from a 3-V supply. Dy-
`namic range and linearity requirements of A/D converters
`used in RE’ receivers are also presented.
`I. INTRODUCTION
`Wireless local areanetworks (WLANs) in the2.4-GHzrange
`have rapidly emerged in the consumer market. Providing flex-
`ibility and reconfigurability, WLAN standards allow data rates
`of several megabits per second and serve as high-speed links
`in office buildings, hospitals, factories, etc. For high-volume
`portable applicalions such as laptop computers, both cost and
`power dissipation of WLAN transceivers become critical, ne-
`cessitating compact, efficient solutions.
`This paper describes design techniques for RF CMOS re-
`ccivers to be used in WLAN applications. In order to target
`realistic specifications, the IEEE 802.11 standard [I] is con-
`sidered as the framework. Section I1 reviews the standard
`and its circuit design implications. Section 111 presents the
`architecture and circuit details of a 2.4-GHz receiver designed
`for this standard and Section IV summarizes the experimen-
`tal results obtained from the fabricated prototype. Section V
`deels with the dynamic range and linearity requirements of
`analog-to-digital converters (ADCs) used in RF receiveFs.
`11. IEEE 802.11 STANDARD
`The IEEE 802.11 R F link incorporates spread-spectrum (SS)
`techniques in the 2.4-GHz range. The standard offers two
`SS formats: frequency-hopped with Gaussian minimum shift
`keying (GMSK) modulation and direct sequence (DS) with
`A. RF Section
`quadrature phase shift keying (QPSK) modulation. The re-
`The design of the LNA and the mixers is determined by
`ceiver reported herein is designed for the latter type.
`The DS-SS standard spreads a 2-MHz channel by a factor of
`not only noise, linearity, and gain requirements, but also cC
`I I , generating an output channel 22 MHz wide. The required
`fects related to direct conversion: LO leakage to the antenna
`sensitivity across this bandwidth is -80 dBm for a frame error
`and second-order distortion in the R F path. The configura-
`tion depicted in Fig. 2 addresses these issues. The cascode
`rate (FER) of 8 x IO-2, indicating that the sum of the noise
`figure ( N F ) and the signal-to-noise ratio ( S N R ) is: N F +
`LNA reduces the LO leakage while the inductive loading in
`27 s
`
`LNA
`
`Vl,
`
`Channel-Select
`
`Amplifier
`
`Channel-Select
`
`I
`
`Q
`
`Fig. I . Receivernrchitecture.
`noise amplifier (LNA) and quadrature downconversion mixers,
`the circuit incorporates partial channel-selection filtering, ac
`coupling, and baseband amplification.
`
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`

`fiers. To relax thisconstraint, partial channel selection filtering
`is interposed between the mixers and the baseband amplifiers,
`thus lowering the magnitude of adjacent-channel interferers.
`The channel-select filter must contribute little Hicker noise and
`tolerate several tens of millivolts of dc offset that appears at
`the output of the mixer due to the self-mixing of the LO. A
`filter topology satisfying these conditions is the Sallen and
`Key configuration depicted in Fig. 4(a), where the amplifier
`is connected in unity gain and can therefore withstand large
`C1 H-
`
`(a) ~lp;~~voull
`
`jLs L
`
`
`
`(1-Mixet To
`
`Fig. 2. LNAImixer circ~iit.
`
`the LNA and capacitive degeneration in the mixer minimize
`the products of second-order nonlinearity. The value of C2
`is chosen such that it exhibits a negligible impedance at 2.4
`GHz but ii relatively high impedance at frequencies below I I
`MHz. As illustrated in Fig. 3, if two large interferers accom-
`pany the desired signal, then second-order distortion in the
`
`r'
`
`M5
`
`7 V L O
`
`zcz
`
`V0"W
`
`(b)
`Fig. 4. (a) Simple Sallen and Key Iiller, (b) filter merged with output of mixer.
`dc offsets. The amplifier must introduce few devices in the
`signal path so as to achieve low flicker noise, but it must also
`exhibit high linearity. For this reason, the amplifier is realized
`as a source follower incorporating a relatively large transistor
`( W / L = 1OOOpm/1.2/m).
`The interface between the mixer and the subsequent fil-
`ter would typically require a buffer stage with low output
`impedance so that the filter characteristics remain unaltcrcd,
`but at the cost of substantial noise and power dissipation due
`to the buffer. We recognize that, since the output signal of the
`mixer is available in the current domain, the input network of
`the filter can be replaced by a Norton equivalent and merged
`with the mixer. Depicted in Fig. 4(b), this technique obvi-
`ates theneed for interstage buffers. The bottom-plateparasitic
`of C1 is placed at nodes X and Y so as to suppress the LO
`feedthrough, which would otherwise desensitize the source
`follower.
`The dc offsets resulting from the self-mixing of LO must
`be removed so as to avoid saturating the baseband amplifier.
`However, since QPSK signals translated to the baseband con-
`tain significant energy in the vicinity of zero frequency, the dc
`notch filter must providea very low corner frequency, fc Thus,
`the choice of fc is determined by three questions: (I) How
`does the notch filter affect the downconverted signal? (2) How
`high can fc be without excessive degradation of the signal?
`(3) How can a notch filer with such a low fc be integrated?
`
`.. : ::. :.
`-A&
`
`Pig. 3. Effect alseeond-orderdislorlion in IW path.
`RF path creates a low-frequency beat that, in the presence of
`asymmetries in the mixer, experiences direct feedthrough to
`the baseband without frequency translation [4]. If the spacing
`between the interferers is less than I1 MHz, then the direct
`feedthrough component falls in the baseband, thereby corrupt-
`ing thedownconverted signal. In thisdesign,on theother hand,
`low-frequency beats generated by the LNA are suppressed by
`both L , and C;. Furthermore, the input transistor of themixer,
`M4, creates negligible beat components because of the large
`impedance of C, at low frequencies. The effectiveness of these
`techniques is evident from the measured second intercept point
`( I & ) (+22 dBm).
`
`B. Baseband Section
`The LNNmixer combination exhibits a gain of approxi-
`mately 24 dB, mandating high linearity in the baseband ampli-
`
`2:
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`The first two questions are answered by simulations of a
`QPSK signal (with raised-cosine filtering) that is translated to
`dc and applied to a first-order high-pass RC filter. Shown in
`Fig. 5 , the output waveforms reveal that the dc notch filter
`
`fer from enormous capacitance to the substrate, much greatcr
`than 10 pF! To resolve this issue, we employ MOS devices
`operating in deep triode rcgion with a well-co,itrul/ed gate-
`source overdrive voltage. Illustrated in Fig. 6(b), the idea is
`based on the observation that, for long-channel deviccs, the
`
`VDD
`
`'b w $ g r n l
`
`1.0
`
`2.0
`(a)
`
`3.0
`
`I
`4.0
`
`-2,010
`
`1.0
`
`2.0
`(b)
`
`3.0
`
`4.0
`
`1.0
`
`2.0
`
`3.0
`
`I
`4.0
`
`( C )
`Fig. 5 . Effect of high-pass filtering on QPSK data translated to baseband:
`(a) ideal QPSK waveform. (b) high-pass filtered data with a corner frequcncy
`equal to Ill00 of the data rate, (c) high-pass filtered data wilh a corner fre-
`quency equal to 1/1000 of the data rate.
`introduces intersymbol interference (ISI), quite excessively if
`fc is on the order of O.Olrs, where rs is the symbol rate. For
`fc 5 O.OOIrs, on the other hand, the eye is quite open and
`the residual IS1 can be removed by the equalizer in the digital
`domain.
`This design incorporates a high-pass filter with a nominal
`fc of 10 kHz. Setting the maximum allowable value of the
`coupling capacitor to 10 pF (i.e., a total of 40 pF for differen-
`tial I and Q signals), we arrive at a resistance of 1.G Mi2 [.Fig.
`6(a)]. Even using n-well material, such a resistor would suf-
`
`r
`
`(C)
`
`Fig. 6 . (a) Simple high-pass filter with coiner liequcncy of 10 kHz, (b)
`topology yieliliiig no,,* = y,:,
`(c) high-pass filler alone wit11 hiscbnnd
`arnplificr.
`transconductance of a saturated MOSFET (MI) is expressed
`by the same equation, grnl = /LC,,(W/L)(VGS - Vrpf), as
`the inverse of the on-resistance of a similar device i n deep tri-
`oderegion(M2): R,f, = pC'o,c(W/L)(V~,s - I/TII). That is,
`if a saturated device and a linear dcvice have equal overdrive
`voltages and equal dimensions, the on-resistance of the latter
`is equal to the inverse transconductance of the former. Sincc
`the transconductance of MOSFETs can be defined by means of
`various analog techniques, this observation makes it possible
`to achieve a very high on-resistance.
`The design of Fig. 6(b) must nonetheless deal with two
`issues. First, the threshold voltage mismatch between Dl1 and
`M2 yields some inaccuracy in the dcfinition of R,,,z. For
`this reason, an overdrive voltage of 200 mV is chosen for
`the transistors, suppressing the effect ofmismatches. Second,
`the variation of the on-resistance of M2 with the input signal
`level leads to distortion. Fortunately, however, the tolewble
`in-channel distortion is quite high (several perccnt) bccause
`of the nature of the signal waveform, and the out-of-channel
`distortion is low because the coupling capacitor exhibits a IOW
`impedance at adjacent-channel frequencics. Simulated and
`measured in-channel and out-of-channel two-tone tests of the
`receiver confirm these results. Fig. 6(c) shows the differen-
`tial implementation of the high-pass filter and the baseband
`amplifier. In this design, (W/L)l = Z(1.5 pm/40 pin) and
`(W/L)z,, = 1.5 pm/40 pm.
`The flicker noise in the baseband section corrupts the down-
`converted signal. However, since the baseband signal occu-
`
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`pies a bandwidth of I I MHz, tlicker noise corner frequencies
`as high as several hundred kilohertz affect the performance
`negligibly. With a corner frequency of 200 kHz, we can write:
`S,/,(200 kHz) = Stb, where Si,/ and S t h denote the power
`spectral densities of I/f noiseand thermal noise, respectively.
`Assuming SI/, = K / f > where I< = (200 kHz) x Sth, and
`integrating the total noise from 200 kHz to I1 MHz as in Fig.
`7, we have
`
`...........
`
`Edge Of
`
`center Of
`Adjacent Channel
`
`-10
`
`..........................
`
`: .......
`
`Fig. 7. Contribution of flicker noise to thc overall S N f l
`
`1 1 MHz
`
`200 kHz
`
`(1)
`
`( 2 )
`
`- v,,z = 1 "Y+/ Sthdf
`
`~
`
`200 kHz
`, 10 k H Z f
`( I 1.4 MHz),St/,.
`
`%
`
`By contrast, if the circuit suffered from no flicker noise, the
`total noise power would be V , = (1 1 MHz)&, only 0.2 dB
`lower. Note that even if flicker noise frequencies as low as 100
`Hz are taken into account, the maximum degradation in S N R
`is less than 0.6 dB. This is a pessimistic estimate because,
`owing to the relatively high gain in the RF section, the I/ f
`noise corner in the baseband is expected to bequite lower than
`200 kHz.
`
`IV. EXPERIMENAL RESULTS
`
`The receiver has been fabricated in a 0 . 6 - p 1 CMOS tech-
`nology in an area of 680 pmx980 pm. Both inductors used
`in the cascade LNA are integrated on-chip with no process
`modifications. The circuit is tested with a 3-V supply.
`Table I summarizes the measurement results. The out-of-
`
`Input Frequency
`Noise Figure
`
`In-Channel IP3
`1-dB Compression Polnt
`Out-of-Cnannel
`IP3
`Voltage Gain
`LO Leakage
`-
`Offset Voltage
`0 ~ 1 ~ ~ 1
`Power Dlssipallon
`
`2.4 GHz
`8.3 dB
`+22 dBm
`-9 dBm
`-21 dBm
`-4 dBm
`
`-47 dBm
`7 mV
`80 mW
`
`Table I. Measured pcrformanceafrecciver at 1.4 CHI
`channel IP3 is measured by applying two tones 22 MHz apart
`such that thcy fall at 22 MHz and 44 MHz after downcon-
`version and their intermodulation product appears near zero
`frequency. Fig. 8 plots the measured transfer function of the
`baseband section, obtained by sweeping the RF input. Note
`that the corner frequency of the baseband dc notch filter is
`approximatelyequal to 7 kHz, confirming the feasibilityof the
`circuit topology shown in Fig. 6(c).
`
`Fig. 8. Measwed baseband tmnsfcr function. (Axes not to scale)
`V. ADC REQUIREMENTS
`The digitization of the received signal can in principle take
`place at the antenna, at the intermediate frequency (IF), or i n
`the baseband. The required performance of the ADC in eacli
`case is determined by the signal dynamic range as well as the
`number and power of the interferers. Thus, both automatic
`gain control (AGC) and channel-selection filtering can relax
`the ADC specifications.
`The ADC parameters of interest in an R F receiver include
`resolution, linearity, full-scale voltage, noise floor (quantiza-
`tion, thermal, and tlicker noise), sampling rate, and power
`dissipation. For our subsequent calculations, we review the
`definitions of linearity in analog design and RF design.
`Assuming a fully-differential architecture for thc ADC and
`representing its inputloutput characteristic by
`Kut(t) M w % f L ( q + N3V23n(l)>
`(3)
`we define the integral nonlinearity (INL) as the maximum
`deviation of V,,,t from a straight line passed through the end
`points of the characteristic (Fig. 9). Here, the end points
`are given by the full-scale voltage Vp.9: (+Vps, +rul VFS +
`
`Pig. 9. Dcflnilion of INL.
`WV;s) and (-VFS, -alVr..s - cqV;,). Thus, the straight
`line can be expressed as
`
`2
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`

`Subtracting V,,,,l from K,, and taking the derivative of the
`result with respect to V,,, we obtain the input level K,,o at
`= V ~ s / \ / s , and
`which the nonlinearity is maximum: !&o
`the maximum nonlinearity as I N L = 2 1 ~ ~ 3 I V > ~ / ( 3 f i ) . Ap-
`proximating the output full scale by 2 a l V ~ s and normalizing
`IINI,I to this value, we have:
`
`_
`
`,
`
` ,
`
`noiseis approximately 20dB below the minimum signal level.
`Thus, lOlog(V&,/Af) = -118 dBm - 1010g(200 kHz) =
`-171 dBm/I-Iz, suggesting that an cxtremely low noise floor
`is required.
`(0.629 nV/d%)
`The full-scale voltage of the ADC is given by the maximum
`input level. In the simple test of Fig. 10, the two interferers
`generate a maximum swing of approximately -50 dBm +6
`( 5 ) dB = -44 dBm (3.99 mVp, in a SO-Q system). Note that this
`means 2 V ~ s = 3.99 mV in Fig. 9.
`The abovecalculations reveil that an ADC digitizinga GSM
`signal along with -SO-dBm interferers at the antenna would
`require an LSB of 0.995 p V and a full-scale voltage of 3.99
`mV, i.e., a resolution of approximately 12 bits.
`ADC Linearity. In order to determine the linearity required
`of the ADC, we assume the two interferers must create an
`intermodulation product at least 20 dB below the signal level.
`From (6), the signal-to-intermodulation ratio at the output can
`be expressed as:
`
`Note that the concept of full scale is central to the definition of
`nonlinearity in analog design but not utilized in R F design.
`The most significant effect of (odd-order) nonlinearity from
`the RF design point of view is intermodulation. If two in-
`terferers xnt1(t) = V,,tcosw~I and !4,,2(1) = lintcoswzt
`experience the nonlinearity described by (3), then the inter-
`modulation products are given by
`V,,t,,u = --V,,,[COS(~W~ - wz)t + C O S ( ~ W ~ - W I ) ~ ] . (6)
`303 3
`4
`Equations ( 5 ) and (6) prove useful in our subsequent deriva-
`tions.
`
`A. Digitizationat RF
`As a simple case, we first assume the ADC directly digi-
`tizes the signal and the interferers at the antenna. In order to
`compute the resolution, full scale, and linearity, we consider
`a typical test for GSM receivers. Thc results can easily be
`scaled for other standards as well. As shown in Fig. 10, a
`-98-dBm signal is accompanied by two interferers located
`
`Number " "+' n + 4
`
`Channel
`
`Pig. IO. lnterrnadulaliantest in GSM.
`two and four channels away. GSM requires that in such a test
`the signal-to-noise ratio at the end of the receiver be at least
`9 dB, restricting both the noise figure and intermodulation be-
`havior of the overall receiver. For simplicity, we assume each
`interferer has a magnitude of -50 dBm.
`ADC Resolution. The resolution is determined by the min-
`imum signal level. To ensure that the ADC corrupts the signal
`negligibly, we assume the quantization noise must be approx-
`imately 20 dB below the signal level, arriving at a resolution
`of about 3 bits. This yields a least significant bit (LSB) equal
`(in a 50-9 system).
`to 0.995 ~ I V
`The thermal noise floor of the ADC is also critical. For a
`channel bandwidth of 200 kHz in GSM, we calculate the input-
`referred thermal noise density of the ADC such that the total
`
`Signal
`Intermodulation
`
`- la1 IVmin
`-
`(3/4)lo31V,i, '
`
`(7)
`
`denotes the peak amplitude of the minimum input
`where V,i,
`signal level, i.e., the receiver sensitivity. Setting (7) equal to
`IO yields D3/011 = 2Vmi,/( 154il). It follows from ( 5 ) that
`
`This equation expresses the maximum allowable nonlinearity
`in terms of the sensitivity, full-scale voltage, and interferer
`levels. In a S O - 9 system, each of the -50-dBm interferers has
`apeakamplitudeof Knt 4 1 mV and theminimum inputlevel
`has a peak amplitude of V,i, 3 4 pV. Thus, with ~ V F S = 4
`= 4.11 x
`mV, we have INL,,,
`i.e., a linearity of
`approximately 11.3 bits.
`An important result ot'(9) is that the required linearity does
`not change with preamplification because both the numerator
`and the denominator scale by the third power of the voltage
`gain. For this reason, amplifier stages interposed between the
`antenna and the ADC relax the noise floor and offset require-
`ments but not the linearity requirement.
`In summary, our simple GSM example demands an ADC
`with a resolutionof 12 bits, an LSB size of 0.995 AIV, a thermal
`noise floor of 0.629 nV/&,
`and a linearity of 11.3 bits.
`While the necessary dynamic range and linearity do not seem
`prohibitive, the small magnitudes of the LSB and the input-
`referred noise present great difficulty in the design.
`In practice, both the resolution and the linearity may need
`to be higher than those calculated above. Depending on the
`type of AGC, the maximum received signal level may demand
`a greater full scale. Also, more than two interferers may be
`received, necessitating a higher linearity. This is particularly
`important in time-division duplexing (TDD) systems such as
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`DECT and IEEE 802.11, where thestrong signals transmitted
`by all of the users fall in the receive band. In these cases,
`the foregoing methods can be used in conjunction with the
`statistics of the interference levels to predict the resolution and
`linearity.
`
`B. Digitizarion at IF
`In order to achieve acceptable image rejection by means of
`low-loss, low-cost filters, modern receivers typically employ
`a relatively high IF - from approximately 50 MHz to 200 MHz
`[5]. Thus, thesamplingrateand input bandwidtbof an IFdigi-
`tizer would still be quite high. More importantly, even high-Q
`off-chip filters used at the IF to perform channel-selection be-
`come incapable of suppressing adjacent-channel interferers as
`the IF increases. For example, for the NDK248SM01 (a SAW
`filter with a passband of 260 kHz centered around 248 MHz
`and an insertion loss of 6 dB), the attenuation is equal to 6 dB
`at 260 kHz offset and 26 dB at 520 kHz offset.
`Effect of Partial Channel-Selection Filtering. Since IF
`filters attenuate the interferers by only a moderate amount,
`it is important to quantify the effect of such filtering on the
`required ADC performance. The results also apply to base-
`band channel-selection filtering as well, revealing trade-offs
`between the filter design and the ADC design.
`11, the IF filter provides a
`Suppose, as shown in Fig.
`suppressionofAI < 1 in thecenteroftheadjacent channeland
`
`1 .... . . . . . . .. . . . . .
`Channel Channel Channel
`A1 ._______.
`...... _____........._
`.____.
`_____..I .______ _____.
`
`_____....______
`Ap _________...._____
`
`w
`
`0 2
`0 1
`Fig. 11. Baodpass filter frequency response
`Az < 1 in the center of the alternate adjacent channel. Since
`the additive amplitude of the two interferers is reduced by the
`filter, the full-scalevoltageand hence theresolution ofthe ADC
`can be lowered. More importantly, smaller interferers allow
`higher nonlinearity in the ADC input/output characteristic.
`-
`Assuming two equal interferers translated to the IF can be
`expressed as V,,, cos w l t + E,,, cos wzt, we can write the out-
`
`put ofthe filter asA1I4,t c o s ( w ~ l + d ~ ) + A z K ~ t cos(wzt+dn),
`and $2 denote the phase shift introduced by the fil-
`where
`ter at W I and W Z , respectively. The peak-to-peak value of this
`waveform gives the full scale: VFS = (Al +Az)I&,
`relaxing
`the ADC resolution by a factor of 2/(AI + Az). For the NDK
`filter example, A , = 0.5 and Az = 0.05, indicating that the
`necessary resolution drops by 2/0.55, i.e., 1.9 bits.
`To compute the required linearity, we apply the output of
`the filter to the ADC input/output characteristic [Eq. (3)] and
`obtain the intermodulation component:
`A9V3 COS[(ZWI - wz)t + 241 - 421
`I - rnt
`3Q3 2
`-A
`V I M ( ~ ) =
` + 242 - 411.10)
`+ -AIA~K:, 3a3
`
`C O S [ ( ~ W Z - ~ j ) t
`4
`
`The first term in (IO) gives the in-channel intermodulation
`product, which is lower than that in (6) by a factor ofA:A2.
`Thus, a3 can berelaxed byA:AZ. Noting that Vr.7 hasdropped
`by 2/(A1 + Az), we can modify Eq. (9) as:
`
`With the above numbers for AI and Az, INI,,,,,:,
`by a factor of 6.05, i.e., 2.6 bits.
`
`i s relaxed
`
`C. Digitization in Baseband
`Thecost, size, and loss ofexternal IF filters make it desirable
`to perform channel-selection filtering by means of monolithic
`implementations. At high IFS, however, it is quite difficult
`to design integrated passive or active filters that attenuate the
`adjacent channels significantly. The precision and speed re-
`quired of the IFdigitizer in this case are still problematic, often
`necessitating that AID conversion be moved to the vicinity of
`the baseband.
`Our foregoing calculations of the effect of filters hint that
`even a moderate attenuation of interferers may lead to a rea-
`sonable demand on the ADC performance. This is important
`because complete channel selection in the analog domain typi-
`cally entails high power dissipation and many large capacitors.
`We consider two types of low-pass filters (LPFs) here.
`First-Order LPF. A first-order filter can readily be incorpo-
`rated in downconversion mixers by simply placing a capacitor
`between the differential outputs. The key property of this ap-
`proach is that the filter does not contribute additional noise.
`For such a filter, the attenuation factors in the two adjacent
`channels are A I = 0.447 and A2 = 0.243. Thus, the required
`full-scale voltage drops by 1.5 bits and, from Eq. (II), the
`INL is relaxed by a factor of 2.45, i.e., 1.3 bits.
`Sallen and Key Filter. For maximally-flat response, we
` = Rz = R a n d C ~ = 2C2,0btainiiigAl =
`chooseinFig. ~ R I
`0.243 and A2 = 0.0624. As a result, both the resolution and
`the INL are relaxed by 2.7 bits. This configuration is thcrefore
`an attractive solution even though its transfer characteristics
`are relatively sensitive to component variations.
`REFERENCES
`[I] IEEE, P802.11. UraJ Sraiidard for Wi,r/ess LAN Medieiii Ac-
`cess Conrrol (MAC) and Physical Layer (PIIY) Specijicotion,
`IEEE Standards Dept., 1997.
`[2] A. A. Abidi, “Direct-conversion radio transceivers for digital
`cornmunicstions,” IEEE Journal of So/id-Slurc Circiiils, vol.
`30,pp. 1399-1410,Dec. 1995.
`[3] B. Razavi, “Design Considerations for Direct-Conversion Rc-
`ccivers,” IEEE Trans. Circuirs and Systems, Parr 11, vol. 44,
`pp, 428-435, June 1997.
`[4] B. Raravi, HF Microekcrronics, Upper Saddle River,
`NJ:Prentice Hall, 1998.
`[SI T. D. Stetzler era/, “A 2.7-4.5 V Single Chip CSM Transceiver
`RF Integrated Circuit,” IEEE Journal of Solid-Stare Circuits,
`vol. 30, pp. 1421-1429,Dec. 1995.
`
`280
`
`ParkerVision Ex. 2013
`Intel Corp. v. ParkerVision, Inc.
`IPR2020-01265
`
`