(12) United States Patent
`Kawasaki et al.
`
`I 1111111111111111 11111 111111111111111 1111111111 lllll 111111111111111 11111111
`US006281552Bl
`US 6,281,552 Bl
`Aug. 28, 2001
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) THIN FILM TRANSISTORS HAVING LDD
`REGIONS
`
`(75)
`
`Inventors: Ritsuko Kawasaki, Kanagawa;
`Hidehito Kitakado, Hyogo; Kenji
`Kasahara, Kanagawa; Shunpei
`Yamazaki, Tokyo, all of (JP)
`
`(73) Assignee: Semiconductor Energy Laboratory
`Co., Ltd. (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/532,690
`Mar. 22, 2000
`(22) Filed:
`Foreign Application Priority Data
`
`(30)
`
`Mar. 23, 1999
`
`(JP) ................................................. 11-078715
`
`(51)
`
`Int. Cl.7 ........................... H0lL 29/04; H0lL 31/20;
`H0lL 27/01; HOlL 27/12; H0lL 31/0392
`(52) U.S. Cl. .............................. 257/350; 257/59; 257/72;
`257/344; 257/408
`(58) Field of Search ................................ 257/59, 72, 350,
`257/344, 392, 408
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.......................... 257/40
`9/1993 Friend et al.
`5,247,190
`............................ 437/1
`3/1995 Friend et al.
`5,399,502
`1/1997 Konuma et al. ..................... 349/122
`5,594,569
`7/1997 Ohtani et al. .......................... 437/88
`5,643,826
`7/1999 Ohtani et al. ........................ 438/150
`5,923,962
`5,998,841 * 12/1999 Suzawa ................................ 257/350
`6,046,479 * 4/2000 Young et al.
`........................ 257/350
`6,166,397 * 12/2000 Yamazaki et al. ..................... 257/59
`6,166,414 * 12/2000 Miyazaki et al. .................... 257/369
`6,172,671 * 1/2001 Shibuya et al. ...................... 345/205
`6,180,982 * 1/2001 Zhang et al. ......................... 257/347
`FOREIGN PATENT DOCUMENTS
`
`7-130652
`10-092576
`WO 90/13148
`
`5 /1995 (JP) .
`4/1998 (JP) .
`11/1990 (WO) .
`
`OTHER PUBLICATIONS
`
`Hatano, M. et al, "A Novel Self-Aligned Gate-Overlapped
`LDD Poly-Si TFT with High Reliability and Performance,"
`IEDM Technical Digest 97, pp. 523-526.
`Shimokawa, R. et al, "Characterization of High-Efficiency
`Cast-Si Solar Cell Wafers by MBIC Measurement," Japa(cid:173)
`nese Journal of Applied Physics, vol. 27, No. 5, pp.
`751-758, May, 1988.
`Yoshida, T. et al, "A Full-Color Thresholdless Antiferro(cid:173)
`electric LCD Exhibiting Wide Viewing Angle with Fast
`Response Time," SID 97 Digest, pp. 841-844, 1997.
`Furne, H. et al, "Characteristics and Driving Scheme of
`Polymer-Stabilized Monostable FLCD Exhibiting Fast
`Response Time and High Contrast Ratio with Gray-Scale
`Capability," SID 98 Digest, pp. 782-785, 1998.
`Schenk, H. et al, "Polymers for Light Emitting Diodes,"
`Eurodisplay '99, Proceedings of the 19th International
`Display Research Conference, Berlin, Germany, Sep. 6-9,
`1999, pp. 33-37.
`re Japanese patent application No.
`English abstract
`7-130652, published May 19, 1995.
`English abstract
`re Japanese patent application No.
`10---092576, published Apr. 10, 1998.
`* cited by examiner
`
`Primary Examiner-Ngan V. Ng6
`(74) Attorney, Agent, or Firm-Cook, Alex, McFarron,
`Manzo, Cummings & Mehler, Ltd.
`
`(57)
`
`ABSTRACT
`
`To improve the operation characteristic and reliability of a
`semiconductor device by optimizing the structure of bottom
`gate type or inverted stagger type TFTs arranged in circuits
`of the semiconductor device in accordance with the function
`of the respective circuits. At least LDD regions that overlap
`with a gate electrode are formed in an N channel type TFT
`of a driving circuit, and LDD regions that do not overlap
`with the gate electrode are formed in an N channel type TFT
`of a pixel matrix circuit. The concentration of the two kinds
`of LDD regions is differently set from each other, to thereby
`obtain the optimal circuit operation.
`
`20 Claims, 16 Drawing Sheets
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`

`

`US 6,281,552 Bl
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`20
`
`1
`2
`THIN FILM TRANSISTORS HAVING LDD
`A TFT structure known as useful in reducing OFF current
`REGIONS
`is the lightly doped drain (LDD) structure. According to this
`structure, a region doped with an impurity element in a low
`BACKGROUND OF THE INVENTION
`concentration is formed between a channel formation region
`Field of the Invention
`5 and a source region, or a drain region, that is doped with a
`high concentration of impurity element. This lightly doped
`The present invention relates to a semiconductor device
`region is called LDD region.
`that has circuits formed from thin film transistors
`Also known as measures for preventing the degradation
`(hereinafter referred to as TF1) on a substrate having an
`brought by hot carriers is a 'GOLD' structure (Gate-drain
`insulating surface, and to a method of manufacturing the
`10 Overlapped LDD) in which the LDD region is arranged so
`same. More specifically, the present invention is suitably
`applied to an electro-optical device represented by a liquid
`as to overlap with a gate electrode through a gate insulating
`crystal display device in which a pixel portion ( or, a pixel
`film. These structures release the high electric field in the
`matrix circuit) and a driver circuit provided in the periphery
`vicinity of the drain to prevent the hot carrier injection, and
`thereof are formed on the same single substrate, and to an
`hence is effective in preventing the degradation phenomena.
`electronic equipment equipped with such electro-optical
`15 For instance, an article written by Mutuko Hatano, Hajime
`device. Incidentally, the 'semiconductor device' in this
`Akimoto and Takeshi Sakai in IEDM97 TECHNICAL
`specification refers to devices in general which utilizes
`DIGEST on pages 523 to 526 in 1997 discloses a GOLD
`semiconductor characteristics to function and, therefore, the
`structure formed from side walls of silicon, which verifies
`electro-optical device and the electronic equipment
`that very excellent reliability can be obtained with the
`equipped with the electro-optical device mentioned above
`GOLD structure compared to TFTs having other structure.
`are contained in the category.
`Required characteristics, however, is not always the same
`The progress has been made in developing a semicon(cid:173)
`for the pixel TFT of the pixel portion and for the TFTs of the
`ductor device that has circuits formed from TFTs on sub(cid:173)
`driver circuit, such as the shift register or the buffer circuit.
`strates having an insulating surface. Active matrix liquid
`To give an example, a large reverse bias (negative voltage in
`crystal display devices are well known as a typical example 25 the N channel TFT) is applied to the gate in the pixel TFT
`of such semiconductor device. In particular, great effort is
`while the TFTs of the driver circuit do not basically operate
`put into the development of the electro-optical device with
`under the reverse bias state. Also, the pixel TFT operates at
`TFTs whose active layers are made of crystalline silicon
`a speed ½oo times the operation speed of the TFTs in the
`films (hereinafter referred to as crystalline silicon TFT)
`driver circuit.
`integrally formed on the same single substrate, for these 30
`In addition, GOLD structures have a problem in that,
`TFTs are high in field effect mobility and hence afford to
`though high in the effect to prevent the degradation of ON
`form various functional circuits.
`current value, OFF current value is larger than in usual LDD
`For instance, an active matrix liquid crystal display device
`structures. Thus the GOLD structures are not preferable in
`is provided with a pixel portion displaying an image, a driver
`application to the pixel TFT. On the other hand, usual LDD
`circuit used to display an image, etc. The driver circuit is
`35 structures are high in the effect to suppress OFF current
`comprised of circuits formed by using CMOS circuits as the
`value but is low in the effect to release the electric field in
`base, such as a shift register circuit, a level shifter circuit, a
`the vicinity of the drain and prevent the degradation due to
`buffer circuit, and a sampling circuit. Those circuits are
`hot carriers. It is thus not always preferable to form all TFTs
`mixedly mounted on the same single substrate.
`to have the same structure in a semiconductor device that has
`When taking a look at those circuits separately, one does 40
`a plurality of integrated circuits different from one another
`not always share its operation condition with others, which
`in the operation condition, as in active matrix liquid crystal
`causes no small difference in characteristics required for the
`display devices. The problem as such comes to the front
`TFTs. For example, the pixel portion is comprised of a pixel
`especially as the characteristics of crystalline silicon TFTs
`TFT formed from an N channel TFT and of a holding
`are enhanced and more is demanded for the performance of
`capacitor, and is driven by applying voltage to liquid crystal 45
`active matrix liquid crystal display devices.
`while using the pixel TFT as a switching element. Since
`liquid crystal is driven with alternating current, a system
`called frame inversion driving is often used. In this system,
`characteristic required for the pixel TFT to keep power
`consumption low is to reduce sufficiently the OFF current 50
`value (drain current flowing at the time of OFF operation of
`the TFT). On the other hand, in the driver circuit, the
`withstand voltage has to be enhanced lest its buffer circuit to
`which a high driving voltage is applied is broken upon
`application of the high voltage. Also, securing enough ON 55
`current (drain current flowing at the time of OFF operation
`of the TF1) is required to enhance current drive perfor(cid:173)
`mance.
`However, there is a problem in that the OFF current of
`crystalline silicon TFTs tend to take a large value. In 60
`addition, degradation phenomena such as lowering of ON
`current value are observed in crystalline silicon TFTs, simi-
`lar to MOS transistors used in ICs and the like. The main
`cause of the phenomena could be hot carrier injection: it is
`surmised that hot carriers generated by the high electric field 65
`in the vicinity of the drain bring about the degradation
`phenomena.
`
`SUMMARY OF THE INVENTION
`The present invention involves techniques for solving the
`problems above, and an object of the present invention is to
`improve operation characteristics and reliability of a semi(cid:173)
`conductor device by optimizing the structure of TFTs
`arranged in various circuits of the semiconductor device in
`accordance with the function of the respective circuits.
`In order to attain the above object, according to the
`present invention, a semiconductor device having a pixel
`portion and a driver circuit for the pixel portion on the same
`single substrate is characterized in that:
`each of the pixel portion and the driver circuit is provided
`with at least an N channel type TFT that has an active
`layer, LDD regions formed in the active layer, a gate
`insulating film formed between the active layer and the
`substrate, and a gate electrode formed between the gate
`insulating film and the substrate;
`the LDD region in the N channel type TFT of the pixel
`portion is arranged so as not to overlap with the gate
`electrode in the N channel type TFT of the pixel
`portion;
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 018
`
`

`

`US 6,281,552 Bl
`
`4
`positional relationship between a gate electrode and an LDD
`region in a bottom gate type or inversed stagger type TFT
`that has an active layer, LDD regions formed in the active
`layer, a gate insulating film formed between the active layer
`and said substrate, and the gate electrode formed between
`the gate insulating film and said substrate.
`FIG. SA shows a structure in which a gate insulating film
`502 and a gate electrode 501 are formed under an active
`layer having a channel formation region 503, an LDD region
`504 and a drain region 505. The LDD region 504 is formed
`so as to overlap with the gate electrode 501 through the gate
`insulating film 502. The LDD region as such is referred to
`as Lov in this specification. The Lov has an effect to release
`the high electric field generated in the vicinity of the drain
`15 to prevent degradation due to hot carriers, and hence is
`suitable for use in the N channel type TFT of the driver
`circuit.
`In FIG. SB, a channel formation region 508, an LDD
`region 509 and a drain region 510 are formed in an active
`layer on an gate insulating film 507. The LDD region 509 is
`formed so as not to overlap with a gate electrode 506. The
`LDD region as such is referred to as Loff in this specifica(cid:173)
`tion. The Loff is effective in reducing OFF current value, and
`is suitable for use in the N channel type TFT of the pixel
`portion.
`As described above, the present invention is characterized
`in that a semiconductor device having a pixel portion and a
`driver circuit thereof takes a structure in which the pixel
`portion is provided with an N channel type TFT with Loff
`while the driver circuit is provided with an N channel type
`TFT with Lov, and in that the TFTs are of bottom gate type
`or inversed stagger type.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`3
`the LDD region in the N channel type TFT of the driver
`circuit is arranged so as to overlap with the gate
`electrode in the N channel type TFT of the driver
`circuit; and
`the LDD region in the N channel type TFT of the driver 5
`circuit contains a higher concentration of impurity
`element for imparting N type than the LDD region in
`the N channel type TPT of the pixel portion does.
`The semiconductor device is also characterized in that the
`LDD region in the N channel type TFT of the driver circuit 10
`contains an impurity element for imparting N type in a
`concentration two or more times higher than the LDD region
`in the N channel type TFT of the pixel portion does, but the
`concentration in the former LDD region does not exceed ten
`times the concentration in the latter LDD region.
`The semiconductor device is also characterized in that an
`organic resin film is formed on, at least, the N channel type
`TFT of the pixel portion, and in that a capacitor is comprised
`of a light-shielding film formed on the organic resin film, a
`dielectric film formed in close contact with the light shield- 20
`ing film, and a pixel electrode that is formed so as to partially
`overlap with the light-shielding film and is connected to the
`N channel TFT of the pixel portion.
`In order to attain the above object, according to the
`present invention, a method of manufacturing a semicon- 25
`ductor device having a pixel portion and a driver circuit for
`the pixel portion on the same single substrate is character(cid:173)
`ized in that:
`a step of forming an N channel TFT in each of the pixel
`portion and the driver circuit is included, the N channel 30
`TFT having an active layer, LDD regions formed in the
`active layer, a gate insulating film formed between the
`active layer and the substrate, and a gate electrode
`formed between the gate insulating film and the sub-
`strate;
`the LDD region in the N channel type TFT of the pixel
`portion is arranged so as not to overlap with the gate
`electrode in the N channel type TFT of the pixel
`portion;
`the LDD region in the N channel type TFT of the driver
`circuit is arranged so as to overlap with the gate
`electrode in the N channel type TFT of the driver
`circuit; and
`the LDD region in the N channel type TFT of the driver 45
`circuit is doped with a higher concentration of impurity
`element for imparting N type than the LDD region in
`the N channel type TFT of the pixel portion.
`The method of manufacturing a semiconductor device is
`also characterized in that the LDD region in the N channel 50
`type TFT of the driver circuit contains an impurity element
`for imparting N type in a concentration two or more times
`higher than the LDD region in the N channel type TFT of the
`pixel portion does, but the concentration in the former LDD
`region does not exceed ten times the concentration in the 55
`latter LDD region.
`The method of manufacturing a semiconductor device is
`also characterized in that a capacitor is formed through the
`steps of: forming an organic resin film on, at least, the N
`channel type TFT of the pixel portion; forming a light- 60
`shielding film on the organic resin film; forming a dielectric
`film in close contact with the light shielding film; and
`forming a pixel electrode that partially overlaps with the
`light-shielding film and is connected to the N channel TFT
`of the pixel portion.
`FIGS. SA and SB are explanatory views showing the
`structure of the present invention. The figures illustrate the
`
`35
`
`FIGS. lA to lC are sectional views showing a process of
`manufacturing a pixel portion and a driver circuit of
`Embodiment 1;
`FIGS. 2A to 2C are sectional views showing the process
`of manufacturing the pixel portion and the driver circuit of
`40 Embodiment 1;
`FIGS. 3A and 3B are sectional views showing another
`process of manufacturing a pixel portion and a driver circuit
`of Embodiment 2;
`FIGS. 4A and 4B are sectional views showing the process
`of manufacturing the pixel portion and the driver circuit of
`Embodiment 2;
`FIGS. SA and SB are explanatory views each illustrating
`the positional relationship between a gate electrode and an
`LDD region of the present invention;
`FIG. 6 is a structural diagram showing in section an active
`matrix liquid crystal display device of Embodiment 6;
`FIG. 7 is a perspective view showing an active matrix
`liquid crystal display device of Embodiment 6;
`FIG. 8 is a top view of a pixel portion of Embodiment 6;
`FIGS. 9A to 9C are sectional views showing the structure
`of a holding capacitor of Embodiment 4;
`FIGS. lOA and lOB are sectional views showing the
`structure of the holding capacitor of Embodiment 4;
`FIGS. llA to llC are sectional views showing a process
`of manufacturing a crystalline semiconductor layer of
`Embodiment 3;
`FIGS. 12A to 12F are diagrams showing examples of a
`65 semiconductor device of Embodiment 7;
`FIGS. 13A and 13B are diagrams showing examples of a
`semiconductor device of Embodiment 7;
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 019
`
`

`

`US 6,281,552 Bl
`
`5
`FIGS. 14A to 14D are diagrams showing examples of a
`projector of Embodiment 7;
`FIGS. 15A and 15B are a top view and a sectional view
`showing a construction of an EL display device of Embodi(cid:173)
`ment 8;
`FIGS. 16A and 16B are sectional views of a pixel portion
`of the EL display device of Embodiment 8;
`FIGS. 17 A and 17B are a top view and a circuit diagram
`of the pixel portion of the EL display device of Embodiment
`8; and
`FIGS. 18A-18C are circuit diagrams of examples of the
`pixel portion of the EL display device of Embodiment 9.
`
`15
`
`6
`nitrogen contained in the film to a concentration of 5xl018
`cm- 3 or less. The gate insulating film and the amorphous
`silicon film can be formed by the same film deposition
`method, so that the two may be formed successively. In this
`5 case, avoiding exposure to the air atmosphere once the gate
`insulating film is formed makes it possible to prevent
`contamination of the surface of the gate insulating film, to
`thereby reduce fluctuation in characteristics of the TFTs to
`be manufactured and variation in the threshold voltage.
`10 Thereafter a crystalline silicon film 106 is formed using a
`known crystallizing technique. For example, laser
`crystallization, thermal crystallization (solid phase growth
`method) or a crystallizing method using a catalytic element
`may be employed.
`A region of the crystalline silicon film 106 where the N
`channel type TFT is to be formed may be doped with boron
`(B) in a concentration of lxl016 to 5xl017 cm- 3 with the
`intention of controlling the threshold voltage. This boron
`doping may be conducted by ion doping or may be con-
`20 ducted at the same time as the film deposition of the
`amorphous silicon film.
`(Formation of Spacer Film, Formation of N- Region: FIG.
`lB)
`Next, doping with an impurity element for imparting N
`25 type is conducted in order to form the LDD region in the N
`channel type TFT of the pixel portion. A silicon oxide film
`or a silicon nitride film with a thickness of 100 to 200 nm,
`for example, 120 nm is formed on the entire surface of the
`crystalline silicon film 106. After forming a photoresist film
`30 on the entire surface of this silicon oxide film or silicon
`nitride film, the photoresist film is exposed to light from its
`back surface using the gate electrodes 102 to 104 as masks
`to form a resist mask on the gate electrodes (not shown). At
`this point, the resist mask can be formed to have almost the
`same width as that of the gate electrodes by optimizing the
`exposure time and intensity of light irradiation. Then utiliz(cid:173)
`ing this resist mask, unnecessary portion is etched and
`removed to form first spacer films 107 to 109 made of a
`silicon oxide film or a silicon nitride film. A second spacer
`film 110 with a thickness of 50 nm is further formed thereon.
`Through the second spacer film 110, the crystalline silicon
`film below the film 110 is doped with an impurity element
`for imparting N type by ion doping. The phosphorus (p)
`concentration in the thus formed impurity regions 111 to 115
`desirably ranges from lxl017 cm- 3
`to 2.5x1018 cm- 3
`,
`2xl017 cm- 3
`, in this embodiment. The concentration of the
`impurity element for imparting N type contained in the
`impurity regions 111 to 115 is expressed as (n-) in this
`specification.
`(Formation of N- Region and N+ Region: FIG. lC)
`The next step is to form impurity regions that functions as
`a source region or a drain region in the N channel TFT and
`to form the LDD region in the N channel TFT of the driver
`circuit. Here, masks 116 to 118 are formed from resist by a
`normal exposure. The mask 116 is formed so as to cover at
`least a portion to be a channel formation region of a P
`channel TFT. The mask 118 is formed in the N channel TFT
`of the pixel portion so as to cover portions to be the channel
`formation region and the LDD region, respectively. The
`mask 117 is formed so as to cover a portion to be the channel
`formation region in the N channel TFT of the driver circuit.
`Ion doping (or, ion injection) is conducted to form impurity
`regions 119 to 123 which are doped with an impurity
`element for imparting N type through the second spacer film
`110 and to form impurity regions 124, 125 which are doped
`with an impurity element for imparting N type through the
`second spacer film 110 and the first spacer film 108. The
`
`DETAILED DESCRIPTION OF IBE
`PREFERRED EMBODIMENTS
`A mode for carrying out the present invention will be
`described in detail by means of Embodiments shown below.
`Embodiment 1
`This embodiment will be described with reference to
`FIGS. lA to 2C. Here, a detailed description will be given
`in order on steps for manufacturing simultaneously TFTs for
`a pixel portion and for a driver circuit provided in the
`periphery of the pixel portion.
`(Formation of Gate Electrode, Gate Insulating Film and
`Semiconductor Layer: FIG. lA)
`In FIG. lA, a low alkaline glass substrate or a quartz
`substrate is used for a substrate 101. On one surface of this
`substrate 101 where a TFT is to be formed, a base film made
`of, for example, a silicon oxide film, a silicon nitride film,
`and a silicon nitride oxide film may optionally be formed
`(not shown). Gate electrodes 102 to 104 are formed such that
`a coating is formed of an element selected from tantalum
`(Ta), titanium (Ti), tungsten (W), molybdenum (Mo) and
`aluminum (Al) or of a material containing mainly any one of 35
`these elements by a known film deposition method such as
`sputtering and vacuum evaporation, and the coating is then
`formed into a pattern by etching the coating so that the end
`faces thereof are tapered. For example, a Ta film is formed
`by sputtering to have a thickness of 200 nm, a resist mask 40
`is formed into a given shape, and the film is subjected to
`plasma etching treatment with a mixed gas of CF 4 and 0 2 so
`as to have a desired shape. The gate electrodes may have a
`two-layer structure consisting of a tantalum nitride (TaN)
`film and a Ta film, or of a tungusten nitride (WN) film and 45
`a W film (not shown). Gate wirings to be connected to the
`gate electrodes are formed at the same time, though not
`shown.
`A gate insulating film 105 is formed of a material con(cid:173)
`taining silicon nitride to have a thickness of 10 to 200 nm, 50
`preferably 50 to 150 nm. For instance, a silicon nitride film
`105a made of a raw material of SiH4 , NH3 and N2 and
`having a thickness of 50 nm and a silicon nitride oxide film
`105b made of a raw material of SiH4 , and N2 0 and having
`a thickness of 75 nm are formed by plasma CVD and layered 55
`one on the other to form the gate insulating film. Of course,
`the gate insulating film may be comprised of a single layer
`of a silicon nitride film or a silicon oxide film, which causes
`no trouble. In order to obtain a clean surface, it is effective
`to conduct plasma hydrogen treatment prior to the film 60
`deposition of the gate insulating film.
`Next, an amorphous silicon film with a thickness of 20 to
`150 nm is formed in close contact with the gate insulating
`film 105 by a known film deposition method such as plasma
`CVD and sputtering. Though no limitation is put on the 65
`forming condition of the amorphous silicon film, it is
`preferable to reduce impurity elements such as oxygen and
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 020
`
`

`

`US 6,281,552 Bl
`
`7
`impurity regions 119 to 123 contain the impurity element in
`a concentration of lxl020 to lxl021 cm-3, 5xl020 cm- 3
`, in
`this embodiment. The concentration thereof is expressed as
`(n+) in this specification. The impurity regions 124, 125
`contain the impurity element in a concentration of 2xl017 to
`5xl018 cm- 3
`, 6xl017 cm- 3
`, in this embodiment. The con(cid:173)
`centration thereof is expressed as (n-) in this specification.
`(Formation of p+ Region: FIG. 2A)
`The next step is doping with an impurity element for
`imparting P type to form a source region and a drain region 10
`in the P channel type TFT of the driver circuit. In order to
`secure the channel formation region of the P channel type
`TFT, a new resist mask 126 is formed here on the second
`spacer film 110. Etching treatment is performed on the first
`spacer film and the second spacer film to form new spacer 15
`films 129, 130, exposing at the same time the surface of the
`crystalline silicon film. Upon this etching treatment, regions
`where the N channel type TFTs are to be formed are covered
`with resist masks 127, 128. Impurity regions 131, 132 are
`then formed through ion doping (ion injection also will do) 20
`using dibolane (B 2H6). The boron (B) concentration in these
`regions is 1.5xl020 to 3xl021 cm- 3
`, lxl021 cm- 3
`, in this
`embodiment. The concentration