`_FRISHAUF, HOLTZ, GOODMAN & CHICK,P.C.
`No.:
`EV 720 476 889 US
`=n
`ATTORNEYSAT LAW
`Date of Deposit: September 21, 2005
`B= Se... 20FIFTH AVENUE, NEW YORK,N.Y.10001-7708
`a
`.
`=sS 4
`I hereby certify that this paper is
`3 SS
`being deposited with the United
`© Beenvoit
`States Postal Service "Express Mail
`= ai)
`eee.
`Post Office to Addressee" service
`Ne haRTH
`under 37 CFR 1.10 on the date
`poucLASHOLTZ
`indicated above and is addressed to
`ROBERT P. MICHAL
`the Commissioner for Patents, P.O.
`TELEPHONE:(212) 319-4900
`Box 1450, Alexandria, VAg
`FACSIMILE:(212) 319-5101
`be =
`:
`459
`oO ==
`Commissioner for Patents
`.
`oc —
`P.O. Box |
`r
`
`Alexandria, VA 22313-1450LtCio ‘ 283 28: —_— ro
`OQ) =a
`arbara Villani
`wN =o_ _
`Attorney Docket No. _05621/LH i ——
`CUSTOMERNO.01933
`-
`——
`
`
`
`:
`
`:
`
`Pursuant to 37 CFR 1.53(b), transmitted herewith forfiling is the patent application of
`
`FILING WITHOUT EXECUTED
`DECLARATION(37 CFR 1.53(f))
`
`Inventor(s):
`
`Satoru SHIMODAofFussa-shi, Japan
`Tomoyuki SHIRASAKI of Higashiyamato-shi, Japan
`Jun OGURA ofFussa-shi, Japan
`Minoru KUMAGAIof Tokyo, Japan
`
`“TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL”
`Title:
`Priority Claim (35 U.S.C. 119) is made, based upon:
`Japan
`No. 2004-273532
`filed September 21, 2004
`Japan
`No. 2004-273580
`filed September 21, 2004
`Japan
`No. 2005-269434
`filed September 16, 2005
`ASSIGNMENT INFORMATION FOR PUBLICATION:
`Casio Computer Co.,
`d.
`Tokyo, Japan
`
`Enclosed herewith are:
`
`[X ]
`
`Specification (Description, Claims, Abstract): Pages 1 -98_; Numberof claims1 - 25
`
`[
`]
`Declaration and Power of Attorney
`
`[X ] Sheets of drawings, Figures 1 -__28_[X ] Formal27 | ] Informal
`
`
`
`[1
`Assignment and Recordation Form Cover Sheet (PTO-1595) AND $40. RECORDATIONFEE.
`
`[X ]
`
`[Xx ]
`
`[X]
`
`[X]
`
`[X]
`
`Two Certified copies of priority documentsidentified above
`
`Information Disclosure Statement;
`
`[X ] Form PTO/SB/08A
`
`Change of Correspondence Address (Form PTO/SB/122)
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`PTO Form 2038 (Payment by Credit Card)
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`TO THE EXTENT NOT TENDERED BY CREDIT CARD PAYMENT ATTACHED HERETO,
`AUTHORIZATIONIS GIVEN TO CHARGEANY FEES UNDER37 CFR 1.16 AND 1.17 DURING
`PENDENCYOF THE APPLICATION, OR TO CREDIT ANY OVERPAYMENT, TO DEPOSIT
`ACCOUNTNO. 06-1378. DUPLICATE COPY OF THIS LETTER IS ENCLOSED.
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`Receipt Postcard [X ]
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`Independent Claims
`Application Size Fee
`MULTIPLE DEPENDENT CLAIMS
`
`25
`3
`
`-20
`-3
`
`Number Extra
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`5
`0
`
`=
`=
`
`=
`x$ 50.00
`x $200.00 =
`
`Rate
`
`Calculations
`
`$__
`$
`$__
`$
`$
`
`250.00
`
`250.00
`1000.00
`
`+ $360.00
`BASIC FEE
`(Including Filing, Search
`and Examination Fees)
`
`=
`
`$1500.00
`Total of above Calculations
`
`
`FRISHAUF, HOLTZ, GOO,
`
`AN & CHICK,P.C.
`
`
`
`
`LH:by
`10/04
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 001
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 001
`
`
`
`PTO/SB/122 (10-00)
`Approved for use through 10/31/2002. OMB 0651-0035
`U.S. Patent and Trademark Office: U.S. DEPARTMENT OF COMMERCE
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`Under the Paperwork Reduction Act of 1995, no
`persons are required to respond to a collection of information unlessit displays a valid OMB control number.
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`CHANGE OF
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`
`
`
`Application
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`
`
`
`Addressto:
`
`
`Commissioner for Patents
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`
`
`Alexandria, VA. 22313-1450
` 05621/LH
`
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`
`Submit multiple forms if more than one signature is required. See below. {
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`Please change the Correspondence Address for the above-identified application to:
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`This form cannot be used to change the data associated with a Customer Number. To change the data associated with
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`| am the:
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`1 Applicant/inventor.
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`] Assignee of record of the entire interest. Statement under 37 CFR 3.73(b) is enclosed. (Form PTO/SB/96).
`
`[X] Attorney or Agent of record. Registration No. 22,974
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`{
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`] Registered practitioner named in the application transmittal letter in an application without an executed oath or
`declaration. See 37 CFR 1.33(a)(1). Registration Number
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`Typed or Printed
`Name
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`Signature
`
`Leonard/ Holtz, Reg. No. 22,974
`
`Date September 21,
`
`005
`
`Telephone:
`
`(212) 319-4900
`
`NOTE: Signatures of all the inventors or assignees of record of the entire interest or their representative(s) are required.
`
`forms are submitted.
`) Total of
`This collection of information is required by 37 CFR 1.33. The information is required to obtain or retain a benefit by the public whichis to file (and by the USPTO to
`process) an application. Confidentiality is govered by 35 USC 122 and 37 CFR 1.14. This collection is estimated to take 3 minuted t o complete, including
`gathering, preparing and submitting the completed application to the USPTO. Time will vary depending uponthe individual case. Any comments on the amount of
`time you require to complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark
`Office, U.S. Department of Commerce, P.O. Box 1450,Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SENDTo:
`Commissionerfor Patents, P.O. Box 1450, Alexandria, VA 22313-1450.
`LG Display Co., Ltd.
`Exhibit 1002
`Page 002
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 002
`
`
`
`~GO+260
`
`-
`
`FRISHAUF, HOLTZ, GOODMAN& CHICK,P.C.
`=
`= s
`ATTORNEYS AT LAW
`——— =
`== S .
`20FIFTH AVENUE, NEW YORK, N.Y. 10001-7708
`==
`Zeer
`=e DMAN
`———
`» cue
`‘Ditorrz
`,
`ROBERT. MICHAL
`TELEPHONE:(212) 319-4900
`:
`FACSIMILE:(212) 319-5101
`Commissioner for Patents
`P.O. Box,1450,
`Alexandria, VA 22313-1450
`
`21,
`
`2005
`
`Express oea6 Mailing Label
`O.?
`.
`it:
`sr
`21,
`Date of Deposit: September
`I hereby certify that this paper is
`being deposited with the United
`States Postal Service "Express Mail
`Post Office to Addressee" service
`under 37 CFR 1.10 on the date
`indicated above and is addressed to
`the Commissioner for Patents, P.O.
`Box 1450, Al
`andria, VA o-
`450
`a.
`oO
`:
`SN
`Maar”
`"
`BN
`arbara Villani
`Ne
`Attorney Docket No. _05621/LH a ——
`CUSTOMERNO.01933
`-
`——
`
`
`
`io
`S=0
`rm
`Ss
`o
`
`Pursuant to 37 CFR 1.53(b), transmitted herewith for filing is the patentapplication of
`
`WITHOUT EXECUTED
`DECLARATION(37 CFR 1.53(f))
`
`Inventor(s):
`
`Satoru SHIMODAofFussa-shi, Japan
`Tomoyuki SHIRASAKI of Higashiyamato-shi, Japan
`Jun OGURA ofFussa-shi, Japan
`Minoru KUMAGAIof Tokyo, Japan
`
`Title:
`“TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL”
`Priority Claim G5 U.S.C. 119) is made, based upon:
`Japan
`No. 2004-273532
`filed September 21, 2004
`Japan
`No. 2004-273580
`filed September 21, 2004
`Japan
`No. 2005-269434
`filed September 16, 2005
`ASSIGNMENT INFORMATIONFOR PUBLICATION:
`Casio Computer Co.
`d.
`Tokyo, Japan
`Enclosed herewith are:
`
`[X ]
`
`Specification (Description, Claims, Abstract): Pages 1 -98_; Numberof claims 1 -_25
`
`[
`
`]
`
`[X ]
`
`I!
`
`Declaration and Powerof Attorney
`
`27
`
`Sheets of drawings, Figures 1-_
`
`28
`
`_
`
`[X ] Formal
`
`[
`
`] Informal
`
`Assignment and Recordation Form Cover Sheet (PTO-1595) AND $40. RECORDATION FEE.
`
`[X ]
`
`Two Certified copies of priority documentsidentified above
`
`[X ]
`
`Information Disclosure Statement;
`
`[X ] Form PTO/SB/08A
`
`[X}
`
`[X]}
`
`[X]}
`
`Change of Correspondence Address (Form PTO/SB/122)
`
`PTO Form 2038 (Payment by Credit Card)
`
`TO THE EXTENT NOT TENDERED BY CREDIT CARD PAYMENT ATTACHED HERETO,
`AUTHORIZATIONIS GIVEN TO CHARGEANYFEES UNDER37 CFR1.16 AND 1.17 DURING
`PENDENCYOF THE APPLICATION, OR TO CREDIT ANY OVERPAYMENT,TO DEPOSIT
`ACCOUNTNO.06-1378. DUPLICATE COPYOF THIS LETTERIS ENCLOSED.
`
`Receipt Postcard
`[X ]
`
`
`NumberFiled
`
`Number Extra
`
`Rate
`
`Calculations
`
`Total Claims
`Independent Claims
`Application Size Fee
`MULTIPLE DEPENDENT CLAIMS
`
`25
`3
`
`-20
`-3
`
`=
`=
`
`§
`
`0
`
`=
`x$ 50.00
`x $200.00 =
`
`+ $360.00
`BASIC FEE
`(Including Filing, Search
`and Examination Fees)
`
`=
`
`250.00
`
`$__
`$
`$__250.00
`$
`$
`
`1000.00
`
`Total of above Calculations 3__1500.00
`
`
`
` FRISHAUF, HOLTZ, GOO
`
`are
`
`AN & CHICK,P.C.
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 003
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 003
`
`
`
`PTO/SB/122 (10-00)
`Approved for use through 10/31/2002. OMB 0651-0035
`U.S. Patent and Trademark Office: U.S. DEPARTMENT OF COMMERCE
`
`Under the Paperwork Reduction Act of 1995, no
`persons are required to respond to a collection of information unlessit displays a valid OMB control number.
`
`
`
`
`
`
`
`
`
`
`
`
`CHANGE OF
`CORRESPONDENCE ADDRESS
`
`
`
`Application
`
`
`
`
`Addressto:
`
`
`Commissioner for Patents
`
`P.O. Box 1450
`
`
`Alexandria, VA. 22313-1450
` 05621/LH
`
`Not yet assigned
`
`Submit multiple forms if more than one signature is required. See below. {
`
`Please change the Correspondence Address for the above-identified application to:
`[X]
`Customer Number [ 01933 ]
`>
`
`OR
`
`Individual Name
`
`cy Siede
`
`Country
`
`This form cannot be used to change the data associated with a Customer Number. To change the data associated with
`an existing Customer Number use “Request for Customer Number Data Change” (PTO/SB/124).
`
`| am the:
`
`[
`
`{
`
`1 Applicant/inventor.
`
`] Assignee of record of the entire interest. Statement under 37 CFR 3.73(b) is enclosed. (Form PTO/SB/96).
`
`[X] Attorney or Agent of record. Registration No. 22,974
`
`{
`
`] Registered practitioner named in the application transmittal letter in an application without an executed oath or
`declaration. See 37 CFR 1.33(a)(1). Registration Number
`
`Typed or Printed
`Name
`
`Signature
`
`Leonard/ Holtz, Reg. No. 22,974
`
`Date September 21,
`
`005
`
`Telephone:
`
`(212) 319-4900
`
`NOTE: Signatures of all the inventors or assignees of record of the entire interest or their representative(s) are required.
`
`forms are submitted.
`) Total of
`This collection of information is required by 37 CFR 1.33. The information is required to obtain or retain a benefit by the public whichis to file (and by the USPTO to
`process) an application. Confidentiality is govered by 35 USC 122 and 37 CFR 1.14. This collection is estimated to take 3 minuted t o complete, including
`gathering, preparing and submitting the completed application to the USPTO. Time will vary depending uponthe individual case. Any comments on the amount of
`time you require to complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark
`Office, U.S. Department of Commerce, P.O. Box 1450,Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SENDTo:
`Commissionerfor Patents, P.O. Box 1450, Alexandria, VA 22313-1450.
`LG Display Co., Ltd.
`Exhibit 1002
`Page 004
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 004
`
`
`
`/
`
`ye
`
`yw
`
`0551046
`
`-
`
`1
`
`-
`
`TITLE OF THE INVENTION
`
`TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL
`CROSS-REFERENCE TO RELATED APPLICATIONS
`
`This application is based upon and claims the
`
`benefit of priority from prior Japanese Patent
`
`Applications No. 2004-273532, filed September 21, 2004;
`
`No. 2004-273580, filed September 21, 2004; and
`
`No. 2005-269434, filed September 16, 2005,
`
`the entire
`
`contents of all of which are incorporated herein by
`
`10
`
`reference.
`
`BACKGROUND OF THE INVENTION
`
`1.
`
`Field of the Invention
`
`The present
`
`invention relates to a transistor
`
`array substrate having a plurality of transistors and,
`
`15
`
`more particularly,
`
`to a display panel using light-
`
`emitting elements which cause self emission when a
`
`current is supplied by the transistor array substrate.
`
`2. Description of the Related Art
`
`Organic electroluminescent display panels can
`
`20
`
`roughly be classified into passive driving types and
`
`active matrix driving types. Organic
`
`electroluminescent display panels of active matrix
`
`driving type are more excellent than those of passive
`
`driving type because of high contrast and high
`
`25
`
`resolution.
`
`In a conventional organic
`
`electroluminescent display panel of active matrix
`
`display type described in, e.g., Jpn. Pat. Appln. KOKAI
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 005
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 005
`
`
`
`—
`
`2
`
`=
`
`~’ Publication No. 8-330600, an organic electroluminescent
`
`element
`
`(to be referred to as an organic EL element
`
`hereinafter), a driving transistor which supplies a
`
`current to the organic EL element when a voltage signal
`
`corresponding to image data is applied to the gate of
`
`the transistor, and a switching transistor which
`
`performs switching to supply the voltage signal
`
`corresponding to image data to the gate of the driving
`
`transistor are arranged for each pixel.
`
`In this
`
`10
`
`display panel, when a predetermined scan line is
`
`selected,
`
`the switching transistor is turned on. At
`
`this time, a voltage of level representing the
`
`luminance is applied to the gate of the driving
`
`transistor through a signal line.
`
`Thus,
`
`the driving
`
`15
`
`transistor is turned on.
`
`A driving current having a
`
`magnitude corresponding to the level of the gate
`
`voltage is supplied from the power supply to the
`
`organic EL element
`
`through the source-to-drain path of
`
`the driving transistor. Consequently,
`
`the EL element
`
`20
`
`emits light at a luminance corresponding to the
`magnitude of the current. During the period from the
`
`end of scan line selection to the next scan line
`
`selection,
`
`the level of the gate voltage of the driving
`
`transistor is continuously held even after the
`
`25
`
`switching transistor is turned off. Hence,
`
`the organic
`
`EL element keeps emitting light at a luminance
`
`corresponding to the magnitude of the driving current
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 006
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 006
`
`
`
`bog
`
`©
`
`corresponding to the voltage.
`
`To drive the organic electroluminescent display
`
`panel, a driving circuit is provided around the display
`
`panel to apply a voltage to the scan lines, signal
`
`lines, and power supply lines laid on the display
`
`panel.
`
`In the conventional organic electroluminescent
`
`display panel of active matrix driving type,
`
`interconnections such as a power supply line to supply
`
`10
`
`a current to an organic EL element are patterned
`Simultaneously in the thin-film transistor patterning
`
`step by using the material of a thin-film transistor
`
`such as a switching transistor or driving transistor.
`
`More specifically,
`
`in manufacturing the display panel,
`
`15
`
`a conductive thin film as a prospective electrode of a
`
`thin-film transistor is subjected to: photolithography
`
`and etching to form the electrode of a thin-film
`
`transistor from the conductive thin film. At
`
`the same
`
`time, an interconnection connected to the electrode is
`
`20
`
`also formed.
`
`For this reason, when the interconnection
`
`is formed from the conductive thin film,
`
`the thickness
`
`of the interconnection equals that of the thin-film
`
`‘transistor.
`
`The electrode of the thin-film transistor.is
`
`25
`
`designed assuming that it functions as a transistor.
`
`In other words,
`
`the electrode is not designed assuming
`
`that it supplies a current to a light-emitting element.
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 007
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 007
`
`
`
`Hence,
`
`the thin-film transistor is thin literally.
`
`If
`
`a current is supplied from the interconnection to a
`
`plurality of light-emitting elements, a voltage drop
`
`occurs, or the current flow through the interconnection
`
`delays due to the electrical resistance of the
`
`interconnection.
`
`To suppress the voltage drop or
`
`interconnection delay,
`
`the resistance of the
`
`interconnection is preferably low.
`
`If the resistance
`
`of the interconnection is reduced by making a metal
`
`10
`
`layer serving as the source and drain of the transistor
`
`or a metal layer serving as the gate electrode thick,
`
`or patterning the metal
`
`layers considerably wide to
`
`sufficiently flow the current through the metal layers,
`
`the overlap area of the interconnection on another
`
`15
`
`interconnection or conductor when viewed from the upper
`
`Side increases, and a parasitic capacitance is
`generated between them. This retards the flow of the
`current. Alternatively,
`in a so-called bottom emission
`
`structure which emits EL light from the transistor
`
`20
`
`array substrate side,
`
`light emitted from the EL
`
`elements is shielded by the interconnections, resulting
`
`in a decrease in opening ratio, i.e.,
`
`the ratio of the
`
`light emission area.
`
`If the gate electrode of the
`
`thin-film transistor is made thick to lower the
`
`25
`
`resistance,
`
`a planarization film (corresponding to a
`
`gate insulating film when the thin-film transistor has,
`
`e.g., an inverted stagger structure) to eliminate the
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 008
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 008
`
`
`
`step of the gate electrode must also be formed thick.
`
`This may lead to a large change in transistor
`
`characteristic. When the source and drain are formed
`
`thick,
`
`the etching accuracy of the source and drain
`
`degrades. This may also adversely affect the
`
`transistor characteristic.
`
`BRIEF SUMMARY OF THE INVENTION
`
`It is an object of the present invention to
`
`10
`
`satisfactorily drive a light-emitting element while
`suppressing any voltage drop and signal delay.
`A transistor array substrate according to a first
`
`aspect of the present
`
`invention comprises:
`
`a substrate;
`
`a plurality of driving transistors which are
`
`15
`
`arrayed in a matrix on the substrate, each of the
`
`driving transistors having a gate,
`
`a source, a drain,
`
`and a gate insulating film inserted between the gate,
`and the source and drain;
`
`20
`
`a plurality of signal lines which are patterned
`together with the gates of the plurality of driving
`
`transistors and arrayed to run in a predetermined
`
`direction on the substrate;
`
`a plurality of supply lines which are patterned
`
`together with the sources and drains of the plurality
`
`25
`
`of driving transistors and arrayed to cross the
`
`plurality of signal lines via the gate insulating film,
`
`each of the supply lines being electrically connected
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 009
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 009
`
`
`
`to one of the source and the drain of the driving
`
`transistor; and
`
`a plurality of feed interconnections which are
`
`formed on the plurality of supply lines along the
`
`plurality of supply lines, respectively.
`
`Preferably, a substrate according to claim 1,
`
`further comprising a plurality of scan lines which are
`
`patterned together with the sources and drains of the
`
`plurality of driving transistors and arrayed to cross
`
`10
`
`the plurality of supply lines via the gate insulating
`
`film.
`
`Preferably, a substrate according to claim 2,
`
`which further comprises a plurality of switch
`
`transistors which are arrayed in a matrix on the
`
`15
`
`substrate, each of the switch transistors having the
`
`gate insulating film inserted between a gate and a
`
`source and drain, and
`
`in which one of the source and drain of each of
`
`the plurality of switch transistors is electrically
`
`20
`
`connected to the other of the source and drain of a
`
`corresponding one of the plurality of driving
`
`transistors,
`
`the gate of each of the plurality of switch
`
`transistors is electrically connected to the scan line
`
`25
`
`through a contact hole formed in the gate insulating
`
`film, and
`
`the other of the source and drain of each of the
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 010
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 010
`
`
`
`plurality of switch transistors is electrically
`
`connected to the signal line through a contact hole
`
`formed in the gate insulating film.
`Preferably, a substrate according to claim 2,
`
`which further comprises a plurality of holding
`
`transistors which are arrayed in a matrix on the
`
`substrate, each of the holding transistors having the
`
`gate insulating film inserted between a gate anda
`
`source and drain, and
`in which one of the source and drain of each of
`
`the plurality of holding transistors is electrically
`
`connected to the gate of a corresponding one of the
`
`plurality of driving transistors through a contact hole
`
`formed in the gate insulating film,
`
`the other of the source and drain of each of the
`
`plurality of holding transistors is electrically
`
`connected to one of the supply line and the scan line,
`
`and
`
`10
`
`15
`
`the gate of each of the plurality of holding
`
`20
`
`transistors is electrically connected to the scan line
`
`through a contact hole formed in the gate insulating
`
`film.
`
`A display panel according to a second aspect of
`
`the present invention is a display panel comprising:
`
`25
`
`a substrate;
`
`a plurality of driving transistors which are
`
`arrayed in a matrix on the substrate, each of the
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 011
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 011
`
`
`
`driving transistors having a gate, a source,
`
`a drain,
`
`and a gate insulating film inserted between the gate,
`
`and the source and drain;
`
`a plurality of signal lines which are patterned
`
`together with the gates of the plurality of driving
`
`transistors and arrayed to run in a predetermined
`
`direction on the substrate;
`a plurality of supply lines which are patterned
`
`together with the sources and drains of the plurality
`
`10
`
`of driving transistors and arrayed to cross the
`plurality of signal lines via the gate insulating film,
`
`each of the supply lines being electrically connected
`
`to one of the source and the drain of the driving
`
`transistor; and
`
`15
`
`a plurality of feed interconnections which are
`
`connected to the plurality of supply lines along the
`
`plurality of supply lines;
`
`a plurality of pixel electrodes each of which is
`
`electrically connected to the other of the source and
`
`20
`
`the drain of each of the plurality of driving
`
`transistors;
`
`a plurality of light-emitting layers which are
`
`formed on the plurality of pixel electrodes,
`
`respectively; and
`
`25
`
`a counter electrode which covers the plurality of
`
`light-emitting layers.
`
`Preferably, a panel according to claim 13, further
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 012
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 012
`
`
`
`comprising a plurality of scan lines which are
`
`patterned together with the sources and drains of the
`
`plurality of driving transistors and arrayed to cross
`
`the plurality of supply lines via the gate insulating
`
`film.
`
`According to this aspect,
`
`the signal lines are
`
`patterned together with the gates of the driving
`
`transistors. However, since the feed interconnections
`
`are stacked on the supply lines,
`
`the feed
`
`10
`
`interconnections are formed separately for the drains,
`
`sources, and gates of the driving transistors.
`
`For
`
`this reason,
`
`the feed interconnection can be made thick
`
`without increasing its width, and the resistance of the
`
`feed interconnection can be reduced. Hence, even when
`
`15
`
`a signal is output to the driving transistor and pixel
`
`electrode through the feed interconnection,
`
`the voltage
`
`drop and signal delay can be suppressed.
`
`When the feed interconnections are to be formed by
`
`electroplating,
`
`the supply lines are formed on the
`
`20
`
`signal lines. When the structure is dipped ina
`
`plating solution while a voltage is applied to the
`
`supply lines in the manufacturing step of the
`
`transistor array substrate and the display panel,
`
`the feed interconnections can be grown on the supply
`
`25
`
`lines.
`
`According to this aspect, since the feed
`
`interconnections can be made thick,
`
`the resistance of
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 013
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 013
`
`
`
`-
`
`10
`
`-
`
`the feed interconnections can be reduced. When the
`
`resistance of the feed interconnections decreases,
`Signal delay and voltage drop can be suppressed.
`
`the
`
`A display panel manufacturing method according to
`
`a fourth aspect of the present invention is claim 18.
`
`A thick interconnection can suppress the voltage
`
`drop and can also be used as a partition wall
`
`in
`
`forming an organic compound-containing solution.
`
`Since
`
`the liquid repellent conductive layer exhibits liquid
`
`10
`
`repellency, an organic compound layer can
`
`satisfactorily be patterned.
`
`A liquid repellent
`
`conductive layer containing, e.g.,
`
`a triazine compound
`
`can selectively be formed on a metal surface so as to
`
`exhibit liquid repellency but cannot be formed on the
`
`15
`
`surface of an insulator or a metal oxide to exhibit
`
`liquid repellency.
`
`In addition,
`
`the liquid repellent
`
`conductive layer is formed on the metal surface very
`
`thin. Hence,
`
`the electrical conductivity on the metal
`
`surface is not lost.
`
`20
`
`BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
`
`FIG.
`
`1 is a view showing the circuit arrangement
`
`of an EL display panel together with an insulating
`
`substrate;
`
`FIG.
`
`2 is an equivalent circuit diagram of a pixel
`
`25
`
`circuit of the EL display panel;
`
`FIG.
`
`3 is a plan view showing the electrode of the
`
`pixel circuit of the EL display panel;
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 014
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 014
`
`
`
`rt
`
`»
`
`- 1 -
`
`FIG.
`
`4 is a plan view showing the electrode of the
`
`pixel circuit of the EL display panel;
`
`FIG.
`
`5 is a sectional view taken along a line
`
`V- V in FIG. 3;
`
`FIG.
`
`6 is a sectional view taken along a line
`
`VI - VI
`
`in FIG. 3;
`
`FIG.
`
`7 is a sectional view taken along a line
`
`VII - VII
`
`in FIG. 3;
`
`FIG.
`
`8 is a sectional view taken along a line
`
`10
`
`VIII - VIII in FIG. 3;
`
`15
`
`20
`
`FIG.
`
`9 is a plan view showing a state wherein a
`
`gate layer is patterned;
`
`FIG. 10 is a plan view showing a state wherein a
`
`drain layer is patterned;
`
`FIG. 11 is a plan view showing a state wherein the
`
`drain layer is superposed on the patterned gate layer;
`
`FIG. 12 is a schematic plan view showing the
`
`layout of an organic EL layer of the EL display panel;
`
`FIG. 13 is a timing chart for explaining a driving
`
`method of the EL display panel;
`FIG.
`14 is a timing chart for explaining another
`
`driving method of the EL display panel;
`
`FIG. 15 is a graph showing the current vs. voltage
`
`characteristic of the driving transistor and organic EL
`
`25
`
`element of each pixel circuit;
`
`FIG. 16 is a graph showing the correlation between
`
`the maximum voltage drop and the interconnection
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 015
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 015
`
`
`
`PY
`
`*
`
`.
`
`-
`
`12
`
`-
`
`resistivity o/sectional area S of the feed
`
`interconnection and common interconnection of a 32-inch
`
`EL display panel;
`
`FIG. 17 is a graph showing the correlation between
`
`the sectional area and the current density of the feed
`
`interconnection and common interconnection of the
`
`32-inch EL display panel;
`
`FIG. 18 is a graph showing the correlation between
`
`the maximum voltage drop and the interconnection
`
`10
`
`resistivity o/sectional area S of the feed
`
`interconnection and common interconnection of a 40-inch
`
`EL display panel 1;
`
`FIG. 19 is a graph showing the correlation between
`
`the sectional area and the current density of the feed
`
`15.
`
`interconnection and common interconnection of the
`
`40-inch EL display panel;
`
`FIG. 20 is a view showing the circuit arrangement
`
`of an EL display panel together with an insulating
`
`substrate;
`
`20
`
`25
`
`FIG. 21 is an equivalent circuit diagram of a
`
`pixel circuit of the EL display panel;
`
`FIG. 22 is a plan view showing the electrodes of
`
`pixel circuits Pj,4 and Pj,441 of the EL display panel;
`
`FIG. 23 is a sectional view taken along a plane
`perpendicular to the channel width of a driving
`
`|
`
`transistor;
`
`FIG. 24 is a sectional view taken along a line
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 016
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 016
`
`
`
`7
`
`XXIV - XXIV in FIG. 22;
`
`FIG. 25 is a sectional view taken along a line
`
`XXV - XXV in FIG. 22;
`
`FIG. 26 is a schematic view showing the coating
`
`structure of a liquid repellent conductive film;
`
`FIG. 27 is a schematic plan view showing the
`
`layout of the organic EL layers of the EL display
`panel; and
`|
`
`FIG. 28 is a timing chart for explaining the
`
`10
`
`operation of the EL display panel.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`[First Embodiment]
`
`The best mode for carrying out the present
`
`invention will be described below with reference to the
`
`15
`
`accompanying drawing. Various kinds of limitations
`
`which are technically preferable in carrying out the
`
`present invention are added to the embodiments to be
`
`described below. However,
`
`the spirit and scope of the
`
`present invention are not limited to the following
`
`20
`
`embodiments and illustrated examples.
`
`[Overall Arrangement of EL Display Panel]
`
`FIG.
`
`1 is a schematic view showing an EL display
`
`panel
`
`1 of active matrix driving type.
`
`As shown in
`
`FIG. 1,
`
`the EL display panel
`
`1 comprises an insulating
`
`25
`
`substrate 2, n (a plurality of) signal
`
`lines Yj
`
`to Yn,
`
`m (a plurality of) scan lines Xj
`
`to Xm, m (a plurality
`
`of) supply lines Z1 to Zp,
`
`(m X n) pixel circuits P1/1
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 017
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 017
`
`
`
`-
`
`14
`
`-
`
`to Pm,n,
`
`a@ Plurality of feed interconnections 90, and
`
`common interconnections 91.
`
`The insulating substrate 2
`
`is optically transparent and has a flexible sheet shape
`
`or a rigid plate shape.
`
`The signal lines Yj
`
`to Yy, are
`
`arrayed on the insulating substrate 2 in parallel to
`each other.
`The scan lines X1 to Xm are arrayed on the
`insulating substrate 2 to be perpendicularly to the
`
`Signal lines Yj to Y, when the insulating substrate 2
`
`is viewed from the upper side.
`
`The supply lines Z 1 to
`
`10
`
`2m are arrayed on the insulating substrate 2 between
`
`the scan lines Xj;
`
`to Xm to be parallel to them so that
`
`the supply lines and scan lines alternate.
`
`The pixel
`
`circuits P,,1 to Pm,n are arrayed on the insulating
`
`substrate 2
`
`in a matrix along the signal lines Yj
`
`to Yy
`
`15
`
`and scan lines Xj to Xm.
`
`The feed interconnections 90
`
`are provided in parallel to the supply lines Z1 to Zp
`
`when viewed from the upper side.
`
`The common
`
`interconnections 91 are provided in parallel to the
`
`signal lines Y;
`
`to Y, when viewed from the upper side.
`
`20
`
`In the following description,
`
`the direction in
`
`to Yy run will be defined as
`which the signal lines Yj
`the vertical direction (column direction), and the
`
`direction in which the scan lines Xj;
`
`to Xm run will be
`
`defined as the horizontal direction (row direction).
`
`25
`
`
`In addition, m andnare natural numbers (m 2 2,
`
`n 2 2).
`
`The subscript added to a scan line xX
`
`represents the sequence from the top in FIG. 1.
`
`The
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 018
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 018
`
`
`
`-
`
`15
`
`-
`
`subscript added to a supply line Z represents the
`
`sequence from the top in FIG. 1.
`
`The subscript added
`
`to a signal line Y represents the sequence from the
`
`left in FIG. 1.
`
`The first subscript added to a pixel
`
`circuit P represents the sequence from the top, and the
`
`second subscript represents the sequence from the left.
`
`More specifically,
`
`let i be an arbitrary natural number
`
`of 1 tom, and j be an arbitrary natural number of 1 to
`n,
`a scan line Xj is the ith row from the top,
`a supply
`
`10
`
`line Zi; is the ith row from the top, a signal line Y4
`is the jth column from the left, and a pixel circuit
`
`Pi,j
`
`is located on the ith row from the top and the jth
`
`- column from the left.
`
`The pixel circuit Pi,3 is
`
`connected to the scan line Xj, supply line 2Z;, and
`
`15
`
`Signal line Y5-
`
`The total number of feed interconnections 90 is m.
`
`A voltage VL to flow a write current and a voltage VH
`
`to flow a driving current are applied from a left
`
`terminal 906 and right terminal 90c on the insulating
`
`20
`
`substrate 2 to each feed interconnection 90.
`
`For this
`
`reason,
`
`the voltage drop of the feed interconnection 90
`
`can be suppressed small as compared to when applying
`
`the voltages VL and VH from one of the left terminal
`
`90b and right terminal 90c.
`
`The feed interconnections
`
`25
`
`90 are formed on the upper surfaces of the supply lines
`
`21 to Zm to be electrically connected to them.
`
`The total number of common interconnections 91 is
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 019
`
`LG Display Co., Ltd.
`Exhibit 1002
`Page 019
`
`
`
`-
`
`16
`
`-
`
`n+l.
`
`Two common interconnections 91 adjacent
`
`in the
`
`row direction also function as partition walls to
`
`partition,
`in film formation, organic EL layers 20b of
`organic EL elements (light-emitting elements) 20
`
`arranged between them.
`
`The common interconnections 91
`
`are connected to a lead interconnection 9la on the
`
`front side and to a lead interconnection 91b on the
`
`rear side.
`
`The lead interconnections 9la and 91b have
`
`the same thickness as the common interconnections 91
`
`10
`
`and also function as partition walls to partition the
`
`organic EL layers 20b in the fore-and-aft direction in
`
`film formation.
`
`The common interconnections 91 are
`
`connected to an external device through interconnection
`
`terminals 91lc.
`
`A common potential Vcom is applied to
`
`15
`
`the common interconnections 91.
`
`In the EL display panel 1,
`
`regions partitioned in
`
`a matrix by the scan lines Xj
`
`to Xm and signal lines Yj
`
`to Yn form pixels.
`
`Each of the pixel circuits P,,/1 to
`
`20
`
`Pm,n is provided in one region.
`[Circuit Arrangement of Pixel Circuit]
`
`The pixel circuits Pj,1 to Pm,n have the same
`
`