Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`I.
`
`Appendix B-1: Exemplary Evidence And Discussions Relating To The Invalidity
`Of The ’068 Patent In View Of Shin, International Publication WO 2004/090853
`(“Shin”) ................................................................................................................................2
`
`4.
`
`5.
`
`6.
`
`A.
`
`B.
`
`C.
`
`D.
`
`Independent Claim 1 ................................................................................................2
`1.
`[1pre]—“1. A transistor array substrate comprising:” ..........................2
`2.
`[1a]—“a substrate” ....................................................................................9
`3.
`[1b]—“a plurality of driving transistors which are arrayed in a
`matrix on the substrate, each of the driving transistors having
`a gate, a source, and a drain, and a gate insulating film
`inserted between the gate, and the source and drain;” ..........................9
`[1c]—“a plurality of signal lines which are patterned together
`with the gates of said plurality of driving transistors and
`arrayed to run in a predetermined direction on the substrate” ..........20
`[1d]—“a plurality of supply lines which are patterned together
`with the sources and drains of said plurality of driving
`transistors and arrayed to cross said plurality of signal lines
`via the gate insulating film, one of the source and the drain of
`each of the driving transistors being electrically connected to
`the supply lines” .......................................................................................30
`[1e]—“a plurality of feed interconnections which are formed
`on said plurality of supply lines along said plurality of supply
`lines, respectively.” ...................................................................................50
`Dependent Claim 5 – “A substrate according to claim 1, further
`comprising a plurality of light-emitting elements each of which is
`connected to one of the source and drain of a corresponding one of the
`driving transistors.” ................................................................................................65
`Dependent Claim 10 – “A substrate according to claim 1, wherein the feed
`interconnections have a width of 7.45 to 44.00 um.” ............................................68
`Independent Claim 13 ............................................................................................68
`1.
`[13pre]—“A display panel comprising:” ...............................................68
`2.
`Limitations [13a]-[13d] are disclosed for the same reasons as
`[1a]-[1d] .....................................................................................................70
`[13e]—“a plurality of feed interconnections which are
`connected to said plurality of supply lines along said plurality
`of supply lines;” ........................................................................................70
`[13f]—“a plurality of pixel electrodes each of which is
`electrically connected to the other of the source and the drain
`of a corresponding one of said plurality of driving transistors;” ........72
`[13g]—“a plurality of light-emitting layers which are formed
`on said plurality of pixel electrodes, respectively; and” .......................79
`[13h]—“a counter electrode which covers said plurality of
`light-emitting layers.” ..............................................................................86
`
`3.
`
`4.
`
`5.
`
`6.
`
`1
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 1
`
`

`

`
`I.
`
`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`APPENDIX B-1: EXEMPLARY EVIDENCE AND DISCUSSIONS RELATING
`TO THE INVALIDITY OF THE ’068 PATENT IN VIEW OF SHIN,
`INTERNATIONAL PUBLICATION WO 2004/090853 (“SHIN”)
`
`1.
`
`The following includes exemplary evidence and discussions from Shin relating to
`
`the asserted claims of the ’068 patent.
`
`2.
`
`In addition to the exemplary evidence and discussions below, the body of my report
`
`contains additional narrative descriptions and exemplary evidence as to Shin that supplements the
`
`disclosures below and should be considered part of this Appendix, and vice versa for this and all
`
`other appendices.
`
`3.
`
`I have reviewed Solas’s responses to Defendants’ Interrogatory No. 14, and
`
`understand that Solas contends that Defendants have failed to show that any limitation of the
`
`asserted claims of the ’068 patent is disclosed or rendered obvious by Shin, but has not explained
`
`any of those positions or provided facts supporting its contentions. Thus, it is not possible to
`
`understand or rebut Solas’s contentions, which amount to mere conclusions lacking factual support
`
`or explanation. However, to the extent that Solas or its expert allege any facts or opinions
`
`supporting its contentions that Shin does not disclose and/or render obvious any one or more
`
`limitations of the asserted claims of the ’068 patent, I may supplement my opinions below to cite
`
`additional evidence from Shin, other references, or to supplement or modify my opinions regarding
`
`the obviousness of the asserted claims in view of Shin and one or more references.
`
`A.
`
`Independent Claim 1
`
`1.
`
` [1pre]—“1. A transistor array substrate comprising:”
`
`4.
`
`5.
`
`To the extent the preamble is limiting, Shin discloses and/or renders obvious [1pre].
`
`For example, Shin discloses “an OELD panel capable of decreasing a cross-talk.”
`
`Shin, Abstract. Shin’s OELD panel, like any OELD panel, is composed of a plurality of pixels
`
`
`
`2
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 2
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`arranged in an array of rows and columns, wherein each pixel has multiple transistors (such as “a
`
`driving transistor QD” and a “switching transistor QS”). The claimed transistor array substrate is
`
`disclosed throughout the Shin reference, for example:
`
`Shin, Fig. 1;
`
`
`
`
`
`3
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 3
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`
`
`Shin, Fig. 3;
`
`Shin, 9:8-18;
`
`In addition, the organic electro luminescent panel 50 includes a
`plurality of data lines, a plurality of first current supply lines, a
`plurality of scan lines and a plurality of second current supply lines.
`Numbers of the data lines, the first current supply lines, the scan
`lines and the second current supply lines are 'm', 'm', 'n' and 'n',
`respectively, wherein 'm' and 'n' are positive numbers and are
`independent from each other. The organic electro luminescent panel
`50 displays an image using the image signal that is provided from
`the column driver 20 in response to the scan signals that are provided
`from the low driver 30. A switching element (QS, not shown), a
`driving element (QD, not shown), an organic electro luminescent
`element (not shown) and a storage capacitor (Cst, not shown) are
`formed in a region defined by two adjacent data lines and two
`adjacent scan lines
`
`The organic electro luminescent display apparatus may include a
`plurality of the pixels, a plurality of the scan lines, a plurality of the
`horizontal current supply lines, a plurality of the data lines and a
`plurality of the longitudinal current supply lines. The number of the
`
`
`
`4
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 4
`
`

`

`
`
`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`pixels that are electrically connected to each of the longitudinal
`current supply lines may be equal to that of the scan lines.
`
`The p-th longitudinal current supply line (H-Vddp) is extended in
`the horizontal direction that is substantially in parallel with the scan
`line. The horizontal current supply line (H-Vddp) is electrically
`connected to the longitudinal current supply lines (V-Vddg and V-
`Vddg+1).
`
`Shin, 25:15-23;
`
`FIG. 19 is a plan view showing a unit pixel of an organic electro
`luminescent display apparatus
`in accordance with another
`exemplary embodiment of the present invention. FIG. 20 is a cross-
`sectional view taken along the line Al-Al ' of FIG. 19.
`
`Referring to FIGS. 19 and 20, the organic electro luminescent panel
`includes a scan line N10, a horizontal current supply line N30, a
`switching transistor (QS), a driving transistor (QD), a longitudinal
`current supply line N33, a first ITO pattern N40, a second ITO
`pattern N42, a partition wall N50, an organic electro luminescent
`layer N60, a counter electrode layer N70 and a protection layer N80.
`The organic electro luminescent panel may include a plurality of the
`scan lines, a plurality of the horizontal current supply lines, a
`plurality of the switching transistors, a plurality of the driving
`transistors, a plurality of the longitudinal current supply lines, a
`plurality of the first ITO patterns, a plurality of the second ITO
`patterns, a plurality of the partition walls and a plurality of the
`organic electro luminescent layers.
`
`Shin, 25:24-26:10; see also id., Figs. 1, 7-48 (showing transistors), claim 9 (“plurality of the unit
`pixels”).
`
`6.
`
`With respect to the embodiment described with respect to Figures 18-22, the pixels
`
`and their respective transistors are formed on a “substrate N05 including an insulating material,
`
`for example, such as a glass, a ceramic, etc.”
`
`
`
`5
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 5
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`Shin, Fig. 20;
`
`
`
`Referring to FIG. 21, a metal, for example, such as tantalum (Ta),
`titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr),
`copper (Cu) or tungsten (W) is deposited on a substrate N05
`including an insulating material, for example, such as a glass, a
`ceramic, etc. The deposited metal is patterned to form the scan line
`N10, a first gate electrode N12, a horizontal current supply line N14,
`a storage capacitor pattern N16 and a second gate electrode N18.
`The scan line N10 is extended in a horizontal direction. The first
`gate electrode N12 is electrically connected to the scan line N10.
`The horizontal current supply line N14 is extended in the horizontal
`direction that is substantially in parallel with the scan line. The
`second gate electrode N18 is electrically connected to the storage
`capacitor N 16.
`
`Shin, 26:14-23;
`
`Referring to FIG. 22, a silicon nitride is deposited on the substrate
`N05 through a plasma chemical vapor deposition to form a gate
`insulating layer N19. An amorphous silicon layer and an N+
`amorphous silicon layer implanted with N+ impurities are formed
`on the gate insulating layer N19. The amorphous silicon layer and
`the N+ amorphous silicon layer are patterned to form the first active
`layer N20 and the second active layer N24. The first and second
`active layers N20 and N24 correspond to the first and second gate
`electrodes N12 and N18. The first active layer N20 includes a first
`semiconductor layer N21 and a first ohmic contact layer N22. The
`second active layer N24 includes a second semiconductor layer N25
`and a second ohmic contact layer N26.
`
`Shin, 26:24-27:6; see also id., 18:2-10 (“Referring to FIGS. 8 and 9, an insulating layer 107 is
`
`formed on a substrate 105. The substrate 105 includes a transparent material, for example, such
`
`as a glass, a quartz, a ceramic, a crystalline glass, etc. Preferably, the transparent material is heat
`
`
`
`6
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 6
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`resistive.”), 27:22-28:9, 37:16-19, 40:18-41:3, 41:11-14, 41:23-25, 44:4-10, 44:18-45:8, Figs. 9,
`
`29, 36, 43.
`
`7.
`
`Similarly, with respect to the embodiment described with respect to Figures 7-17,
`
`Shin discloses a unit pixel of an organic electroluminescent display, wherein each unit pixel is
`
`comprised of switching transistors QS1 and QS2 and driving transistors QD.
`
`Shin, Fig. 7, 15:8-16:7;
`
`
`
`Referring to FIG. 7, the unit pixel includes a first switching
`transistor (QS1), a second switching transistor (QS2), a storage
`capacitor (Cst), a driving transistor (QD) and an organic electro
`luminescent element (EL). The first switching transistor (QS1), the
`second switching transistor (QS2), the storage capacitor (Cst), the
`driving transistor (QD) and the organic electro luminescent element
`(EL) are disposed in a region defined by a p-th scan line (Gp), a g-
`th data line (Dg) and a g-th longitudinal current supply line (V-V
`ddg). A p-th scan signal and a g-th data signal are applied to the p-
`th scan line (Gp) and the g-th data line (Dg), respectively. A second
`voltage is applied to a p-th horizontal current supply line (H-Vddp).
`The p-th horizontal current supply line (H-Vddp) is substantially in
`parallel with the p-th scan line (Gp). The p-th horizontal current
`supply line (H-Vddp) is electrically connected to the g-th
`longitudinal current supply line (V-V ddg).
`
`Shin, 15:11-22;
`
`
`
`7
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 7
`
`

`

`
`
`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`An adjacent pixel that is disposed at a position adjacent to the unit
`pixel includes a first switching transistor (QS 1), a second switching
`transistor (QS2), a 25 storage capacitor (Cst), a driving transistor
`(QD) and an organic electro luminescent element (EL). The first
`switching transistor (QS1), the second switching transistor (QS2),
`the storage capacitor (Cst), the driving transistor (QD) and the
`organic electro luminescent element (EL) are disposed in a region
`defined by the p-th scan line (Gp), a g+ 1-th data line (Dg+ 1) and a
`g+ 1-th longitudinal current supply line (V-Vddg+l). The p-th scan
`signal and a g+l-th data signal are applied to the p-th scan line (Gp)
`and the g+ I-th data line (Dg+ 1), respectively. The g+ I-th
`longitudinal current supply line (V-V ddg+ 1) is electrically
`connected to the p-th horizontal current supply line (H-Vddp). The
`organic electro luminescent display apparatus may include a
`plurality of the scan lines and a plurality of the data lines.
`
`Shin, 15:23-16:7.
`
`8.
`
`The pixels and their respective transistors are formed on a “substrate 105,”
`
`including “a transparent material, for example, such as a glass, a quartz, a ceramic, a crystalline
`
`glass, etc.” Shin, 18:3-4.
`
`Shin, Fig. 9; see also id., 18:2-3, 11 (“The switching transistor (QS) is formed on the insulating
`
`layer 107,” wherein the “insulating layer 107 is formed on a substrate 105.”), 18:2-3, 19:6-7 (“The
`
`driving transistor (QD) is formed on the insulating layer 107,” wherein the “insulating layer 107
`
`is formed on a substrate 105.”); see also id., 21:24-22:5 (“switching transistor…and…driving
`
`
`
`
`
`8
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 8
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`transistor are formed on the insulating layer (not show) that is formed over the substrate”), 22:13-
`
`20.
`
`2.
`
`[1a]—“a substrate”
`
`9.
`
`Shin discloses and/or renders obvious “a substrate.” As discussed in the prior
`
`limitation [1pre], Shin teaches that its display panel described in Figures 18-24 is built on a
`
`“substrate N05,” which can be “a glass.” Shin, 26:14-17, 26:24-27, 27:22-25, 28:3-6, Fig. 20.
`
`Additionally, Shin discloses that its display panel described in Figures 7-17 is built on a “substrate
`
`105.” See, e.g., Shin, 18:2-3, 11 (“The switching transistor (QS) is formed on the insulating layer
`
`107,” wherein the “insulating layer 107 is formed on a substrate 105.”), 18:2-3, 19:6-7 (“The
`
`driving transistor (QD) is formed on the insulating layer 107,” wherein the “insulating layer 107
`
`is formed on a substrate 105.”); see also, e.g., id., 21:24-22:5, 22:13-20, Fig. 9..
`
`10.
`
`Every embodiment of Shin includes a substrate. See, e.g., Shin, 18:3-5, 21:27-22:5,
`
`37:16-19, 40:27-41:1, 44:4-8, 44:18-20, 47:24-27 (other embodiments).
`
`3.
`
`[1b]—“a plurality of driving transistors which are arrayed in a matrix
`on the substrate, each of the driving transistors having a gate, a
`source, and a drain, and a gate insulating film inserted between the
`gate, and the source and drain;”
`
`Shin discloses and/or renders obvious limitation [1b].
`
`For example, Shin teaches that each pixel in its display panel of Figures 18-24
`
`11.
`
`12.
`
`includes a “driving transistor (QD),” that includes “a gate electrode N18,” a “source electrode
`
`N35,” a “drain electrode N34,” and a “gate insulating film N19.”
`
`
`
`9
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 9
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`Shin, Fig. 19;
`
`Shin, Fig. 20;
`
`
`
`
`
`FIG. 18 is a circuit diagram showing a unit pixel of an organic
`electro luminescent display apparatus in accordance with another
`exemplary embodiment of the present invention. A switching
`transistor and a driving transistor of the organic electro luminescent
`display apparatus include N-channel metal oxide semiconductor
`(NMOS) transistors.
`
`
`
`10
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 10
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`Shin, 24:17-21;
`
`Referring to FIG. 21, a metal, for example, such as tantalum (Ta),
`titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr),
`copper (Cu) or tungsten (W) is deposited on a substrate N05
`including an insulating material, for example, such as a glass, a
`ceramic, etc. The deposited metal is patterned to form the scan line
`N10, a first gate electrode N12, a horizontal current supply line N14,
`a storage capacitor pattern N16 and a second gate electrode N18.
`The scan line N10 is extended in a horizontal direction. The first
`gate electrode N12 is electrically connected to the scan line N10.
`The horizontal current supply line N14 is extended in the horizontal
`direction that is substantially in parallel with the scan line. The
`second gate electrode N18 is electrically connected to the storage
`capacitor N 16.
`
`Shin, 26:14-23;
`
`A metal is deposited and patterned to form the data line N30, a first
`source electrode N31, a first drain electrode N32, the longitudinal
`current supply line N33, a second drain electrode N34 and a second
`source electrode N35. The data line N30 is extended in the
`longitudinal direction. The first source electrode N31 is electrically
`connected to the data line N30. The first drain electrode N32 is
`spaced apart from the first source electrode N31. The longitudinal
`current supply line N33 is extended in the longitudinal direction.
`The second drain electrode N34 is electrically connected to the
`horizontal current supply line N33. The second source electrode
`N35 is spaced apart from the second drain electrode N34. The
`longitudinal current supply line N33 is electrically connected to the
`horizontal current supply line N14 formed thereunder through the
`first contact hole CNT1.
`
`Shin, 27:11-21; see also id., Figs. 20-24.
`
`13.
`
`Figure 20 below shows a cross section of the driving transistor QD having a bottom-
`
`gate TFT structure, where the gate insulating film N19 is “inserted between the gate [N18], and
`
`the source [N35] and drain [N34]” as required by the claim.
`
`
`
`11
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 11
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`Shin, Fig. 20; see also citations above.
`
`14.
`
`Shin uses Figures 18-24 to describe one exemplary pixel and its respective drive
`
`transistor QD. Shin further discloses that the display panel “may include a plurality of the pixels”
`
`and “a plurality of the driving transistors.”
`
`
`
`The organic electro luminescent display apparatus may include a
`plurality of the pixels, a plurality of the scan lines, a plurality of the
`horizontal current supply lines, a plurality of the data lines and a
`plurality of the longitudinal current supply lines. The number of the
`pixels that are electrically connected to each of the longitudinal
`current supply lines may be equal to that of the scan lines.
`
`Shin, 25:15-19,
`
`FIG. 19 is a plan view showing a unit pixel of an organic electro
`luminescent display apparatus
`in accordance with another
`exemplary embodiment of the present invention. FIG. 20 is a cross-
`sectional view taken along the line Al-Al ' of FIG. 19.
`
`Referring to FIGS. 19 and 20, the organic electro luminescent panel
`includes a scan line N10, a horizontal current supply line N30, a
`switching transistor (QS), a driving transistor (QD), a longitudinal
`current supply line N33, a first ITO pattern N40, a second ITO
`pattern N42, a partition wall N50, an organic electro luminescent
`layer N60, a counter electrode layer N70 and a protection layer N80.
`The organic electro luminescent panel may include a plurality of the
`scan lines, a plurality of the horizontal current supply lines, a
`plurality of the switching transistors, a plurality of the driving
`transistors, a plurality of the longitudinal current supply lines, a
`plurality of the first ITO patterns, a plurality of the second ITO
`patterns, a plurality of the partition walls and a plurality of the
`organic electro luminescent layers.
`
`
`
`12
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 12
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`Shin, 25:24-26:10, 24:17-25:5; see also, e.g., id., 24:24-25:1 (each pixel and its driving transistor
`
`is at the intersection of a data line and scan line), 8:8-18, 9:15-18, Figs. 1, 3, 7, 18-24.
`
`15.
`
`It was typical in the art, including in the ’068 patent specification, to describe the
`
`structure and operation of one pixel when the remaining pixels have the same structure and
`
`operation. For example, Shin teaches that its display can have a resolution of 480x640x3 (480
`
`rows, 640 columns, and three sub-pixels), corresponding to a total of 921,600 unit pixels. Shin,
`
`11:13-19 (“a resolution of the organic electro luminescent panel is 640X480X3.”). It would be
`
`impractical to illustrate all 921,600 pixels when they are substantively the same. A POSA
`
`understood that Shin’s pixels shown in Figures 18-24 are replicated to the side and above and
`
`below in a matrix of pixels in rows and columns. Abstract, 3:25-36, 25:15-19, 26:5-10, 25:15-19,
`
`Figs. 18-24, Fig. 1 (circuit diagram of conventional 2x2 pixel array); see also id., 2:3-5 (describing
`
`conventional displays where the “number of the pixels” in a column of the display is “equal to that
`
`of scan lines”), 3:19-22, 9:8-13, 16:4-15 (describing alternative embodiments and explaining “the
`
`organic electro luminescent display apparatus may include a plurality of the pixels, a plurality of
`
`the scan lines and a plurality of the current supply lines, each of which is connected to a portion
`
`of the pixels.”), 17:22-25, 30:3-7, 31:13-16, 35:6-11, 43:14-18, 46:20-24, 35:12-17, claims 1, 14,
`
`35, Figs. 1, 3, 7, 8, 12-14, 15-24, 27, 30-35, 39-42.
`
`16.
`
`A POSA would have understood and/or found it obvious that Shin’s matrix (i.e.,
`
`rows and columns) of drive transistors are formed on a substrate, such as substrate N05 in the
`
`context of Shin’s Figures 18-24 embodiment. For example, while Shin teaches that the display
`
`can include a plurality of pixels and a plurality of drive transistors, it discloses only a single
`
`substrate N05. See Shin, 24:17-28:26. Indeed, that is true for all of Shin’s embodiments: only a
`
`single substrate is used. Shin, 18:3-5, 21:27-22:5, 37:16-19, 40:27-41:1, 44:4-8, 44:18-20, 47:24-
`
`
`
`13
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 13
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`27 (other embodiments). Moreover, POSAs understood that it was preferable to form the
`
`components of each pixel in a display in the same manufacturing process, i.e., on the same
`
`substrate. See, e.g., Komiya, 9:11-25 (“In view of manufacturing cost reduction and alleviation
`
`variations of TFT characteristics, it is preferable to form corresponding components in each pixel
`
`in the same manufacturing processes.”).
`
`17.
`
`As another example, Shin teaches that each pixel in its display panel of Figures 7-
`
`17 includes a “driving transistor (QD),” which includes “a second gate electrode 134,” “a second
`
`source electrode 154’ and a second drain electrode 156.” Shin, 19:6-23. As shown below, Shin’s
`
`Fig. 8 depicts two unit pixels of the display panel of Figures 7-17, wherein each driving transistor
`
`has a gate, drain, and source.
`
`
`
`14
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 14
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`Shin, Fig. 8.
`
`18.
`
`Shin teaches that the driving transistors QD are formed on the substrate 105 as
`
`shown in Figure 9 below.
`
`
`
`
`
`15
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 15
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`Shin, Fig. 91; see, also e.g., Shin, 21:25-22:6 (“first buffer layer 110…is formed over the
`
`substrate”), 22:13-20 (“a metal layer is formed on the substrate”); see also, id., 21:24-23:10
`
`(describing the manufacturing steps for forming the display panel of Figures 7-17 on a substrate
`
`
`
`105).
`
`19.
`
`As discussed above, the display panel depicted in Figures 7-17 would have rows
`
`and columns of pixels.
`
`The organic electro luminescent display apparatus may include a
`plurality of the pixels, a plurality of the scan lines and a plurality of
`the longitudinal current supply lines, each of which is electrically
`connected to a portion of the pixels. The number of the pixels that
`are electrically connected to each of the longitudinal current supply
`15 lines may be equal to that of the scan lines.
`
`Shin, 16:10-15.
`
`
`1 Shin mistakenly switches “122b” and “134” in Fig. 9, which a POSA would understand is a
`simple typo. Shin clearly discloses 122b as the “second channel forming region,” which is the
`portion located underneath the gate, and the 134 as the “second gate electrode 134.” Shin, 19:6-
`23. Similarly, Shin mistakenly switches 156 and 122c in Figure 9, another typo. Shin discloses
`that 156 is the “second drain electrode” of the driving transistor QD and that 122c is the “second
`drain region.” Id.; see also Figs. 8, 10-17.
`
`
`
`16
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 16
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`20.
`
`And because each pixel has a driving transistor QD, Shin discloses a “plurality” of
`
`
`
`driving transistors formed on the substrate 105. For example, Figures 7-8, 10-17 show two
`
`adjacent pixels, each with their own drive transistor QD.
`
`Shin, Fig. 7;
`
`
`
`
`
`17
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 17
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`
`
`Shin, Fig. 8; see also id., 15:11-16:7.
`
`21.
`
`Additionally, under Solas’s theories of infringement as reflected in its Final
`
`Infringement Contentions, Shin’s display panel embodiment depicted in Figures 7-17 discloses “a
`
`gate insulating film inserted between the gate, and the source and drain.” For example, Solas
`
`alleges that “each of GI [gate insulating film] and ILD [interlayer dielectric] independently, and
`
`GI and ILD taken together, is an insulating film that insulates the gate and that is inserted between
`
`the gate of the driving transistor, and the source and drain”—i.e., that each is the claimed gate
`
`insulating film. 07/31/2020 Final Infringement Contentions, Exhibit B, p. 7. As a result, Solas
`
`appears to argue that other types of films besides a gate insulating film can satisfy this limitation.
`
`As I will explain in my forthcoming non-infringement expert report, Solas’s alleged infringement
`18
`
`
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 18
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`theories with respect to “gate insulating film inserted between the gate and source and drain” are
`
`unfounded. Nevertheless, under Solas’s infringement theories, Shin’s display panel of Figures 7-
`
`17 discloses and/or renders obvious this limitation.
`
`22.
`
`For example, Shin discloses a “gate insulating film 129” and a “first insulating
`
`interlayer 139.”
`
`The driving transistor (QD) is formed on the insulating layer 107 to
`control a current flow. The driving transistor (QD) includes a second
`active layer, the gate insulating layer 129, a second gate electrode
`134, the first insulating interlayer 139, a second source electrode
`154' and a second drain electrode 156. The second active layer
`includes a second source region 122a, a second channel forming
`region 122b and a second drain region 122c. The gate insulating
`layer 129 is formed on the second active layer, and further includes
`two contact holes through which the second source region 122a and
`the second drain region 122c are exposed. The second gate electrode
`134 is formed on the gate insulating layer 129. The first insulating
`interlayer 139 is formed on the second gate electrode 134 and the
`gate insulating layer 129, and further includes two contact holes
`through which the second source region 122a and the second drain
`region 122c are exposed. The second source electrode 154' is formed
`on the first insulating interlayer 139, and electrically connected to
`the second source region 122a. The second drain electrode 156 is
`formed on the first insulating interlayer 139, and electrically
`connected to the second drain region 122c. The second gate
`electrode 136 forms the mono-gate structure. Alternatively, the
`second gate electrodes may form the double-gate structure or the
`triple-gate structure.
`
`Shin, 19:6-23.
`
`23.
`
`Figure 9 below shows a cross section of the driving transistor QD, wherein, under
`
`Solas’s infringement theories, the “gate insulating film 129” and a “first insulating interlayer 139”
`
`are “inserted between the gate [134], and the source [154’] and drain [156’].”
`
`
`
`19
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 19
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`
`
`Shin, Fig. 9.
`
`4.
`
`[1c]—“a plurality of signal lines which are patterned together with the
`gates of said plurality of driving transistors and arrayed to run in a
`predetermined direction on the substrate”
`
`Claim Term
`
`Court’s Construction
`
`patterned together
`
`“patterned to fit together,” wherein patterned may consist of one or
`more fabrication steps
`
`signal lines
`
`
`
`24.
`
`25.
`
`Plain and ordinary meaning wherein the plain and ordinary
`meaning is “conductive lines supplying signals”
`
`Shin discloses and/or renders obvious limitation [1c].
`
`First, Shin discloses a plurality of “scan lines,” which are the claimed signal lines,
`
`labeled Gp in Figure 18 and N10 in Figures 19-24.
`
`
`
`20
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 20
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent, ’068 patent, and ’137 patent
`
`
`
`Shin, Fig. 18;
`
`Shin, Fig. 19;
`
`Shin, Fig. 20;
`
`
`
`
`
`
`
`
`
`21
`
`LG DISPLAY V. SOLAS
`IPR2020-01238
`Exhibit 2019
`Page 21
`
`

`

`Appendix B-1 to the Expert Report of Douglas R. Holberg Regarding The Invalidity of the ’891
`patent