`
`Petition for Inter Partes Review of USP No. 7,573,068
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`
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`In re Inter Partes Review of:
`)
`
`U.S. Patent No. 7,573,068
`)
`
`Issued: August 11, 2009
`)
`
`Application No.: 11/232,368
`)
`
`
`)
`
`
`
`For: TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL
`FILED VIA E2E
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,573,068
`
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`Petition for Inter Partes Review of USP No. 7,573,068
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`TABLE OF CONTENTS
`
`III.
`
`Page
`INTRODUCTION ........................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ................................... 2
`A.
`Real Parties in Interest (37 C.F.R. § 42.8(b)(1)) ................................... 2
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) .............................................. 2
`C.
`Grounds for Standing ............................................................................ 2
`D.
`Lead and Backup Counsel and Service Information ............................. 2
`E.
`Fee for Inter Partes Review .................................................................. 3
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(37 C.F.R. § 42.104(B)) ................................................................................... 4
`A.
`Statutory Ground for the Challenge ...................................................... 4
`IV. BACKGROUND ............................................................................................. 4
`A. Overview of the ’068 Patent (Ex. 1001) ............................................... 4
`B.
`Prosecution History ............................................................................. 14
`C.
`Person Having Ordinary Skill In The Art (POSITA) ......................... 14
`CLAIM CONSTRUCTION .......................................................................... 15
`V.
`VI. DISCRETIONARY DENIAL IS UNWARRANTED .................................. 16
`VII. GROUND 1: CLAIMS 1, 5, 10, 11 AND 13 ARE ANTICIPATED
`BY SHIN ....................................................................................................... 20
`A. Overview – Shin (Ex. 1005) ................................................................ 20
`B.
`Independent Claim 1 Is Anticipated By Shin ...................................... 26
`1.
`[1pre]—“1. A transistor array substrate comprising:” .............. 26
`2.
`[1a]—“a substrate” .................................................................... 28
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`3.
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`4.
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`5.
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`[1b]—“a plurality of driving transistors which are
`arrayed in a matrix on the substrate, each of the driving
`transistors having a gate, a source, and a drain, and a gate
`insulating film inserted between the gate, and the source
`and drain;” ................................................................................. 29
`[1c]—“a plurality of signal lines which are patterned
`together with the gates of said plurality of driving
`transistors and arrayed to run in a predetermined
`direction on the substrate” ........................................................ 35
`[1d]—“a plurality of supply lines which are patterned
`together with the sources and drains of said plurality of
`driving transistors and arrayed to cross said plurality of
`signal lines via the gate insulating film, one of the source
`and the drain of each of the driving transistors being
`electrically connected to the supply lines” ............................... 39
`[1e]—“a plurality of feed interconnections which are
`formed on said plurality of supply lines along said
`plurality of supply lines, respectively.” .................................... 47
`Independent Claim 13 Is Anticipated By Shin .................................... 52
`1.
`[13pre]—“A display panel comprising:” .................................. 52
`2.
`Elements [13a]-[13d] are disclosed for the same reasons
`as [1a]-[1d] ................................................................................ 52
`[13e]—“a plurality of feed interconnections which are
`connected to said plurality of supply lines along said
`plurality of supply lines;” .......................................................... 53
`[13f]—“a plurality of pixel electrodes each of which is
`electrically connected to the other of the source and the
`drain of a corresponding one of said plurality of driving
`transistors;” ............................................................................... 53
`[13g]—“a plurality of light-emitting layers which are
`formed on said plurality of pixel electrodes, respectively;
`and” ........................................................................................... 56
`[13h]—“a counter electrode which covers said plurality
`of light-emitting layers.” ........................................................... 58
`D. Dependent Claims 5, 10, And 11 Are Anticipated By Shin ............... 59
`
`C.
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`6.
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`3.
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`4.
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`5.
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`6.
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`C.
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`1.
`Claim 5 ...................................................................................... 59
`Claim 10 .................................................................................... 60
`2.
`Claim 11 .................................................................................... 61
`3.
`VIII. GROUND 2: CLAIM 13 IS OBVIOUS OVER SHIN ................................. 61
`IX. GROUND 3: CLAIMS 1, 5, 9-13 AND 17 ARE UNPATENTABLE
`OVER SHIN AND HECTOR ....................................................................... 63
`A. Overview – Hector (Ex. 1006) ............................................................ 64
`B.
`Independent Claims 1 and 13 are unpatentable over Shin and
`Hector .................................................................................................. 66
`1. Motivations to combine Shin and Hector ................................. 66
`2.
`All claim 1 and 13 elements except [1e] and 13[e] .................. 73
`3.
`[1e/13e]—“a plurality of feed interconnections which are
`[formed on/connected to] said plurality of supply lines
`along said plurality of supply lines[, respectively]” ................. 73
`Dependent Claims 5, 9-12, and 17 are unpatentable over Shin
`and Hector ........................................................................................... 77
`1.
`Claim 5 ...................................................................................... 78
`2.
`Claim 9 ...................................................................................... 78
`3.
`Claim 10 .................................................................................... 78
`4.
`Claim 11 .................................................................................... 79
`5.
`Claims 12 and 17....................................................................... 79
`a.
`[12a]—“a plurality of light-emitting elements each
`of which has a pixel electrode, an EL layer, and a
`counter electrode and is electrically connected to a
`corresponding one of the driving transistors,” ............... 79
`[12b]/[17]—“wherein the feed interconnections are
`formed by patterning a material film which is
`different from a material film serving as a
`prospective pixel electrode and a material film
`serving as a prospective counter electrode and
`which is thicker than the gates of the driving
`transistors and the sources and drains of the
`driving transistors” ......................................................... 80
`
`b.
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`X. NO KNOWN SECONDARY CONSIDERATIONS EXIST ....................... 85
`XI. CONCLUSION .............................................................................................. 85
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`Petition for Inter Partes Review of USP 7,573,068
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`CASES
`Allied Erecting & Dismantling Co., v. Genesis Attachments, LLC,
`825 F.3d 1373 (Fed. Cir. 2016) .......................................................................... 69
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (Mar. 20, 2020) .................................................passim
`Apple Inc. v. Seven Networks,
`LLC, IPR2020-00156, Paper 10 (June 15, 2020) ............................................... 18
`King Pharms., Inc. v. Eon Labs, Inc.,
`616 F.3d 1267 (Fed. Cir. 2010) .............................................................. 61, 78, 79
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ................................................................................ 67, 68, 69
`NHK Spring Co. v. Intri-Plex Techs., Inc.,
`IPR2018-00752, Paper 8 (Sept. 12, 2018) .......................................................... 19
`Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co.,
`868 F.3d 1013 (Fed. Cir. 2017) .......................................................................... 15
`Paice LLC v. Ford Motor Co.,
`722 F. App’x 1015 (Fed. Cir. 2018) ................................................................... 84
`
`Sand Revolution II, LLC v. Continental Intermodal Grp – Trucking
`LLC,
`IPR2019-01393, Paper 24 (June 16, 2020) ................................................... 18, 19
`STATUTES
`35 U.S.C. § 325(d) ................................................................................................... 20
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`Petition for Inter Partes Review of USP 7,573,068
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`REGULATIONS
`37 C.F.R. § 42.8 ......................................................................................................... 2
`37 C.F.R. § 42.10 ................................................................................................... 2, 4
`37 C.F.R. § 42.15 ....................................................................................................... 3
`37 C.F.R. § 42.100 ................................................................................................... 15
`37 C.F.R. § 42.104 ..................................................................................................... 4
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`Petition for Inter Partes Review of USP 7,573,068
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`LIST OF EXHIBITS
`Ex. No.
`Description
`1001 U.S. Patent No. 7,573,068 (“’068 patent”)
`
`1002 Prosecution history for U.S. Patent Application No. 11/232,368 (“’068
`FH”)
`
`1003 Declaration of Miltiadis Hatalis, Ph.D., in Support of Petitioner’s
`Request for Inter Partes Review (“Hatalis”)
`
`1004 Curriculum Vitae of Miltiadis Hatalis, Ph.D.
`
`1005
`
`International Patent Publication No. WO 2004/090853 (“Shin”)
`
`1006
`
`International Patent Publication No. WO 03/079442 (“Hector”)
`
`1007 Thin Film Transistors, Materials and Processes, Volume 2:
`Polycrystalline Silicon Thin Film Transistors (Yue Kuo ed., 2004)
`(excerpts) (“Kuo”)
`
`1008 Solas’s Opening Claim Construction Brief, Solas OLED Ltd. v. LG
`Display Co., No. 6:19-cv-00236-ADA (W.D. Tex. Mar. 13, 2020),
`ECF No. 68 (“Solas’s Op. Claim Construction Br.”)
`
`1009 Defendants’ Opening Claim Construction Brief, Solas OLED Ltd. v.
`LG Display Co., No. 6:19-cv-00236-ADA (W.D. Tex. Mar. 13, 2020),
`ECF No. 67 (“Defendants’ Op. Claim Construction Br.”)
`
`1010 Claim Construction Order, Solas OLED Ltd. v. LG Display Co., No.
`6:19-cv-00236-ADA (W.D. Tex. June 9, 2020), ECF No. 82
`(“Markman Order”)
`
`1011 RESERVED
`
`1012
`
`Joint Revised List of Terms/Constructions, Solas OLED Ltd. v. LG
`Display Co., No. 6:19-cv-00236-ADA (W.D. Tex. Mar. 13, 2020),
`ECF No. 67-28 (“Parties’ Exchange of Constructions”)
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`Petition for Inter Partes Review of USP 7,573,068
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`Ex. No.
`Description
`1013 Defendants LG Display Co., Ltd., LG Electronics, Inc. and Sony
`Corporation’s Invalidity Contentions, Solas OLED Ltd. v. LG Display
`Co., No. 6:19-cv-00236-ADA (W.D. Tex. Jan. 24, 2020)
`
`1014 U.S. Patent No. 6,724,149 (“Komiya”)
`
`1015 U.S. Patent No. 6,281,552 (“Kawasaki”)
`
`1016 U.S. Patent No. 7,115,956 (“Nakamura”)
`
`1017 U.S. Patent Application Publication No. 2004/0113873 (“Shirasaki”)
`
`1018 Raymond A. Serway, Principles of Physics (2nd ed. 1998) (excerpts)
`(“Serway”)
`
`1019 U.K. Patent Application No. GB 2,389,952 (“Routley”)
`
`1020 U.S. Patent No. 6,809,706 (“Shimoda”)
`
`1021 U.S. Patent Application Publication No. 2002/0101172 (“Bu”)
`
`
`
`
`
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`I.
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`Petition for Inter Partes Review of USP No. 7,573,068
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`INTRODUCTION
`LG Display Co., Ltd. (“LG Display” or “Petitioner”) requests inter partes
`
`review of claims 1, 5, 9-13, and 17 of U.S. Patent No. 7,573,068, titled “Transistor
`
`Array Substrate And Display Panel” (“’068 patent”) (Ex. 1001).
`
`The ’068 patent generally relates to the fabrication of “a transistor array
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`substrate” for an active matrix organic electroluminescent (“OEL”) display panel.
`
`The ’068 patent recognizes that thin supply lines patterned in the layer with the
`
`sources and drains of a drive transistor have a high resistance, causing voltage drop
`
`and signal delays. ’068 patent, 1:57-2:35. To address this problem, the ’068 patent
`
`proposes adding conductive structures that it calls “feed interconnections” along the
`
`supply lines to reduce their effective resistance. ’068 patent, 3:60-4:14.
`
`However, the prior art already recognized and solved this problem in the same
`
`way. Shin, for example, recognized the “voltage drop” problem caused by high
`
`resistance supply lines, and solved the problem in the same way by forming
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`“horizontal current supply lines” along the supply lines to reduce their resistance.
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`Shin, 49:19-50:5 (Ex. 1005). Hector, too, disclosed the “voltage drop” problem and
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`provided the same solution as the ’068 patent, forming “conductive barriers” along
`
`supply lines to reduce their resistance. Hector, Abstract (Ex. 1006).
`
`Accordingly, LG Display respectfully asks the Board to institute review of the
`
`’068 patent and find all challenged claims unpatentable.
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`Petition for Inter Partes Review of USP 7,573,068
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`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`A. Real Parties in Interest (37 C.F.R. § 42.8(b)(1))
`The real-party-in-interest is Petitioner LG Display.
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’068 patent has been asserted in the following district court cases pending
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`in the Western District of Texas: Solas OLED Ltd. v. LG Display Co., Ltd. et al., No.
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`6:19-cv-00236-ADA; Solas OLED Ltd. v. Apple Inc., No. 6:19-cv-00537-ADA;
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`Solas OLED Ltd. v. HP Inc. f/k/a Hewlett-Packard Co., No. 6:19-cv-00631-ADA.
`
`C. Grounds for Standing
`Petitioner certifies that the ’068 patent is available for inter partes review and
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`that Petitioner is not barred from requesting this proceeding.
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`D. Lead and Backup Counsel and Service Information
`Under 37 C.F.R. §§ 42.8(b)(3), 42.8(b)(4), and 42.10(a), Petitioner designates
`
`the following lead counsel:
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`• Jonathan M. Strang (Reg. No. 61,724), jonathan.strang@lw.com,
`
`Latham & Watkins LLP; 555 Eleventh Street, NW, Ste. 1000,
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`Washington, D.C. 20004-1304; 202.637.2362 (Tel.); 202.637.2201
`
`(Fax).
`
`Petitioner also designates the following backup counsel:
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`Petition for Inter Partes Review of USP 7,573,068
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`• Gabriel S. Gross (Reg. No. 52,973), gabe.gross@lw.com, Latham &
`
`Watkins LLP; 140 Scott Drive, Menlo Park, CA 94025; 650.463.2628
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`(Tel.); 650.463.2600 (Fax).
`
`• Douglas E. Lumish (Pro hac vice motion to be filed),
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`doug.lumish@lw.com, Latham & Watkins LLP; 140 Scott Drive,
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`Menlo Park, CA 94025; 650.463.2633 (Tel.); 650.463.2600 (Fax).
`
`• Joseph H. Lee (Pro hac vice motion to be filed), joseph.lee@lw.com,
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`Latham & Watkins LLP; 650 Town Center Drive, 20th Floor, Costa
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`Mesa, CA 92626-1925; 714.755.8046 (Tel.); 714.755.8290 (Fax).
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`• Blake R. Davis (Pro hac vice motion to be filed), blake.davis@lw.com;
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`Latham & Watkins LLP; 505 Montgomery Street, Suite 2000, San
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`Francisco, CA 94111-6538; 415.395.8033 (Tel.); 415.395.8095 (Fax).
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`• Allison K. Harms
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`(Pro hac vice motion
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`to be
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`filed),
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`allison.harms@lw.com; Latham & Watkins LLP; 505 Montgomery
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`Street, Suite 2000, San Francisco, CA 94111-6538; 415.395.8114
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`(Tel.); 415.395.8095 (Fax).
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`Under 37 C.F.R. § 42.10(b), a Power of Attorney from Petitioner is attached.
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`Petitioner consents to electronic service.
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`E.
`Fee for Inter Partes Review
`The Director may charge the fee specified by 37 C.F.R. § 42.15(a) to Deposit
`
`3
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`Account No. 506269.
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`Petition for Inter Partes Review of USP 7,573,068
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`III.
`
`IDENTIFICATION OF CLAIMS
`(37 C.F.R. § 42.104(B))
`A.
`Statutory Ground for the Challenge
`Petitioner requests inter partes review of claims 1, 5, 9-13, and 17 of the ’068
`
`BEING CHALLENGED
`
`patent on these grounds:
`
`Ground
`1
`
`2
`
`3
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`Claims
`1, 5, 10, 11,
`13
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`Basis
`§ 102: Shin
`
`13
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`§ 103: Shin
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`1, 5, 9-13, 17 § 103: Shin and Hector
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`
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`IV. BACKGROUND
`A. Overview of the ’068 Patent (Ex. 1001)
`The ’068 patent relates to active matrix driving type displays that use “light
`
`emitting elements which cause self-emission when a current is supplied by the
`
`transistor array substrate” (e.g., for computing devices, televisions, etc.). ’068
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`patent, 1:15-24; Hatalis ¶¶ 38-44 (providing background information relating to
`
`active matrix OLED displays). The patent’s alleged novelty relates to using
`
`physically thicker conductors along the length of supply lines to reduce the supply
`
`lines’ effective resistance, alleviating problems caused by voltage drops across
`
`supply lines. ’068 patent, 3:60-4:14.
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`Petition for Inter Partes Review of USP 7,573,068
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`To explain, a high level block diagram of an active matrix display is shown
`
`below.
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`
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`’068 patent, Fig. 1 (annotated); Hatalis (Ex. 1003) ¶¶ 45. The display includes a
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`plurality of supply lines (Z1 to Zm) arrayed in a first direction (e.g., horizontally in
`
`the above figure) and a plurality of signal lines that are perpendicular to the supply
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`lines. ’068 patent, 5:52-6:6. Where each signal line and supply line intersect is a
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`pixel (orange box P above) that includes a light-emitting organic electroluminescent
`
`(“OEL”) element, e.g., an organic light emitting diode (“OLED”), and a drive circuit
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`for controlling the amount of light provided by the OEL in that pixel. ’068 patent,
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`1:21-56; Hatalis ¶¶ 45-46.
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`The pixels in the display “have the same structure,” and so the alleged
`
`invention is described with reference to an “arbitrary pixel circuit Pi,j of the pixel
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`circuits P1,1 to Pm,n” shown below in annotated Figure 2. ’068 patent, 6:55-6:62.
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`
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`’068 patent, Figs. 1, 2 (annotated), 6:63-7:26 (describing connections between the
`
`elements shown above); Hatalis ¶¶ 46-47. As shown above, each pixel includes a
`
`light emitting element (OEL 20) and a drive transistor (23). ’068 patent, 7:19-26.
`
`The amount of light the OEL emits corresponds to the amount of current that flows
`
`into it from the supply line, and the magnitude of that current is controlled by the
`
`drive transistor. ’068 patent, 18:16-19 (“The driving transistor 23 functions to drive
`
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`the organic EL element 20 by supplying a current having a magnitude corresponding
`
`to the gray level to the organic EL element 20.”); see also ’068 patent, 15:41-18:19
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`(describing (“EL Display Panel Driving Method”); Hatalis ¶¶ 39-40, 42-43, 47-48.1
`
`The transistors in an active matrix display’s drive circuits, such as transistors
`
`21, 22, and 23 above, are “thin-film” transistors (TFTs). ’068 patent, 1:57-2:3, 6:62-
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`66; Hatalis ¶¶ 42, 49. TFTs are “field effect transistors” (FETs) formed as a series
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`of thin films on a substrate. ’068 patent, 31:43-44 (“[T]he first to third transistors
`
`21 to 23 have been explained as N-channel field effect transistors.”); Hatalis ¶ 50.
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`Each TFT includes a semiconductor (such as polysilicon) and three electrodes: the
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`gate, source and drain. Kuo (Ex. 1007), 007-008; Hatalis ¶ 50. The gate is insulated
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`from the semiconductor layer by a “gate insulating layer,” and the source and drain
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`are formed in direct contact with regions of the semiconductor layer. Hatalis ¶ 50
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`A side view of an exemplary TFT used in the drive circuits of the ’068 patent
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`is shown below. The gate (23g) is formed in a layer on the surface of the substrate
`
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`1 The other transistors (21 and 22) and capacitor 24 of each pixel circuit are used to
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`set the amount of current provided by the drive transistor. See ’068 patent, 6:62-
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`7:26 (describing electrical connections), 15:41-18:19 (describing driving method
`
`and operation). Those elements are not discussed in detail here because they are not
`
`relevant to the challenged claims. Hatalis ¶ 48.
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`(2), then a gate insulating film (31) is formed in a subsequent layer above it, followed
`
`by the layer comprising the source and drain (23s and 23d). In this structure, the
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`gate insulating film is “between” the gate, source and drain.
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`
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`’068 patent, Fig. 23 (annotated); Hatalis ¶ 51.
`
`The ’068 patent admits its displays are made using conventional “patterning”
`
`techniques, i.e., “photolithography and etching” of deposited films. ’068 patent,
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`1:57-2:4, 14:19-15:38. First, a layer is deposited across the entire surface of the
`
`substrate, a photomask is placed over the layer to define a collection of geometries
`
`in the layer, and then the layer is etched. Id.; Hatalis ¶ 52. That process is repeated
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`for each layer of the display. ’068 patent, 14:19-15:38; Hatalis ¶52.
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`For example, the signal lines are formed in the same conductive film as (i.e.
`
`“patterned together with”) the gates of the TFTs, which is shown in the cropped and
`
`annotated cross-section below:
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`
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`’068 patent, Fig. 5 (cropped, annotated), 9:18-28, 14:22-27, 25:4-10; Hatalis ¶ 53.
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`A gate insulating film is then formed over the surface to cover the components
`
`in the gate layer. ’068 patent, 9:29-35. Next, the supply lines are patterned together
`
`with the sources and drains of the TFTs, which the ’068 patent refers to as the “drain
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`layer.” Id., 9:36-49. The gate insulating layer is between the gate layer where the
`
`signal line is formed and the drain layer where the supply line is formed, insulating
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`the lines where they cross.
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`’068 patent, Fig. 8 (annotated, cropped), 9:36-49, 14:42-50, 25:28-35; Hatalis ¶ 54.
`
`
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`A top-down view “wherein the patterned drain layer is superposed on the
`
`patterned gate layer” is shown in Figure 11 below, annotated to show the signal lines
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`(in the gate layer, blue) and supply lines (in the drain layer, green), and the drain of
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`a drive transistor (green with yellow outline) that is connected to the supply line.
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`
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`’068 patent, Fig. 11 (annotated), 9:12-53 (describing the “relationship between the
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`layers” of the transistor 23, signal lines, and scan lines), Fig. 9 (plan view of
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`patterned gate layer), Fig. 10 (plan view of patterned drain layer); Hatalis ¶ 55.
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`The ’068 patent admits that it was “conventional” in active matrix displays to
`
`form the supply lines and the source and drain of the drive circuit transistors in the
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`same layer. ’068 patent, 1:57-2:4. This conventional layout gives rise to the problem
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`allegedly addressed by the ’068 patent. The sources and drains of the “thin-film
`
`transistors” are designed specifically to be thin, and thus the supply lines formed in
`
`the same layer are thin as well. Id., 2:5-9 (“The electrode of the thin-film transistor
`
`is designed assuming that it functions as a transistor.… Hence, the thin-film
`
`transistor is thin literally.”); Hatalis ¶ 56. The ’068 patent recognized the basic fact
`
`that thin supply lines have high resistance, causing voltage drops and signal delays
`
`when delivering current to a light-emitting elements across the length of the display.
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`’068 patent, 1:57-2:12; Hatalis ¶¶ 56-58.
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`The further a pixel is from the voltage source (e.g., in the center of a display),
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`the higher the voltage drop it will see in the supply line. Hatalis ¶¶ 57-58. This is
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`because the conductor’s resistance is equal to its length times the “resistivity” of the
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`material, and divided by the conductor’s cross sectional area. See ’068 patent, 20:51-
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`22:44; Hatalis ¶ 57; Serway (Ex. 1018), 018-021 (resistivity of a conductive wire is
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`“proportional to its length and inversely proportional to its cross-sectional area”).
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`The longer distance implies a larger resistance, and as Ohm’s law dictates, the
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`voltage drop across the supply line is equal to the resistance times the current.
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`Hatalis ¶ 57; Serway, 019-020.
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`The ’068 patent’s alleged point of novelty is providing additional paths for
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`current flow along the supply lines, called “feed interconnections,” to reduce the
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`supply lines’ effective resistance (and thus voltage drop) without increasing the
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`cross-sectional area of the supply lines themselves (which would require that the
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`TFT electrodes be made thicker as well). ’068 patent, 2:5-41; Hatalis ¶¶ 59-60.
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`The ’068 patent describes two ways of arraying “feed interconnections”
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`“along” a display’s supply lines. Hatalis ¶¶ 61-64. In the “First Embodiment,” the
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`feed interconnections are arranged parallel to the supply lines as shown in Figure 1
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`below.
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`’068 patent, Fig. 1 (annotated), 6:26-35; Hatalis ¶ 62.
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`In
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`the “Second Embodiment,” shown
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`in Figure 20, “[t]he
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`feed
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`interconnections” “are connected to the supply lines” in a grid pattern. ’068 patent,
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`23:1-3. Every feed interconnection is connected to every supply line so that the feed
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`interconnections and supply lines form a grid or net shape. See id., 27:6-11, Figs.
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`20, 25; Hatalis ¶ 63.2
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`’068 patent, Fig. 20 (annotated), 2:39-41, 3:60-4:14, 22:45-23:25; Hatalis ¶ 63.
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`2 This works because each pixel ideally receives the same supply voltage. Another
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`signal controls the amount of current delivered from the supply voltage to the pixel’s
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`light emitting element. Hatalis ¶ 63.
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`Thus, each embodiment provides feed interconnections that reduce the total
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`effective cross section—and thus resistance—of the conductor(s) between the
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`supply voltage and each pixel, as compared to conventional supply lines. This
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`lower effective resistance alleviates “signal delay and voltage drop” along the
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`supply lines. ’068 patent, 4:10-14, 6:2-4, 10:17-33, 18:26-40; Hatalis ¶ 64.
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`B.
`Prosecution History
`The patent issued without any Office Actions on the merits aside from a
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`restriction requirement. Ex. 1002 (’068 FH), 662.
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`C.
`Person Having Ordinary Skill In The Art (POSITA)
`A POSITA at the relevant time (2004) would have had at least a bachelor’s
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`degree in electrical engineering (or equivalent) and at least two years’ industry
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`experience, or equivalent experience
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`in circuit design or related fields.
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`Alternatively, a POSITA could substitute directly relevant additional education for
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`experience, e.g., an advanced degree relating to the design of electroluminescent
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`devices, drive circuits, or other circuit design or an advanced degree in electrical
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`engineering (or equivalent), with at least one year of industry experience in a related
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`field. Hatalis ¶ 35.
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`This Petition does not turn on the precise definition above, and the claims are
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`unpatentable from the perspective under any reasonably defined POSITA. Hatalis
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`¶ 37.
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`V. CLAIM CONSTRUCTION
`Claims subject to IPR are to be construed using the same standard as district
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`court. 37 C.F.R. § 42.100(b). Only terms necessary to resolve the controversy need
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`to be construed. Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d
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`1013, 1017 (Fed. Cir. 2017).
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`The parties proposed competing constructions of certain terms in the co-
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`pending litigation. Solas’s Op. Claim Construction Br. (Ex. 1008); Defendants’ Op.
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`Claim Construction Br. (Ex. 1009). On May 22, 2020, the Court held a Markman
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`hearing and on June 10 it issued a two-page order construing four terms of the ’068
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`patent, providing a construction of “feed interconnections” that neither party had
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`proposed. Markman Order (Ex. 1010), 002 (construing “along,” “patterned
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`together,” “signal lines,” and “feed interconnections”).
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`Specifically, the Court found that “signal lines” had the meaning advocated
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`by Solas, i.e., “[p]lain and ordinary meaning wherein the plain and ordinary meaning
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`is ‘conductive lines supplying signals.’” Markman Order, 002. The Court also
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`provided its own construction of “feed interconnections,” construing it to mean
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`“conductive structures in a different layer or layers than the supply line that also
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`provide connections to a source that supplies voltage and/or current.” Markman
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`Order, 002. For the purposes of this IPR, Petitioner adopts and applies the Court’s
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`construction of “signal lines” and “feed interconnections.” 3 Hatalis ¶ 68.
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`The remaining terms construed by the district court, namely “patterned
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`together” and “along,” do not impact the outcome of this IPR because Petitioner
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`conservatively applies the narrower constructions that Petitioner proposed in the
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`district court litigation. Defendants’ Op. Claim Construction Br. at 028-031
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`(“patterned together” means “patterned at the same time”), 025-028 (“along” means
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`“over the length of”); see also Markman Order, 002 (the Court’s broader
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`constructions); Hatalis ¶ 69.
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`VI. DISCRETIONARY DENIAL IS UNWARRANTED
`This Petition should be instituted in considerations of efficiency, fairness, and
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`the overwhelming strength of its merits. Apple Inc. v. Fintiv, Inc., IPR2020-00019,
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`Paper 11 at 5 n.7 (Mar. 20, 2020) (“Fintiv”) (noting that there will be times when
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`“considerations of efficiency, fairness, and the merits of the grounds in the Petition
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`do not weigh in favor of denying the Petition” even where a trial may occur before
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`the Board’s decision). A holistic view of the six factors set forth in Fintiv weigh in
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`favor of instituting review of this Petition. See id. at 6 (listing factors).
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`First and foremost, this Petition was filed expeditiously, less than seven weeks
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`after learning the Court’s unexpected claim constructions, which expanded the
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`3 Petitioner reserves right the appeal the district court’s construction.
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`number of relevant prior art preferences and made plainer the invalidity of the ’068
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`patent. See Fintiv at 11 (“If the evidence shows that the petitioner filed the petition
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`expeditiously, such as promptly after becoming aware of the claims being asserted,
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`this fact has weighed against exercising the authority to deny institution under
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`NHK.”). This Petition could not have been filed any sooner on the grounds described
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`herein. The Court adopted Patent Owner’s broad construction of “signal lines” and
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`“along,” and entered its own constructions of “feed interconnections” and “patterned
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`together” that had not been offered by either party in their briefing. Markman Order
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`(Ex. 1010), 002; Parties’ Exchange of Constructions (Ex. 1012), 004.
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`Immediately after the Markman Hearing, Petitioner diligently searched for
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`invalidating prior art under the Court’s broad claim constructions and identified Shin
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`(Ex. 1005) and Hector (Ex. 1006). Shin could not have been identified sooner
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`because it discloses the claimed “signal lines” (claim elements [1c], [13c]) and “feed
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`interconnections” (claim elements [1e], [13e]) features apparent only under the
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`Court’s construction, and not under the constructions for those terms that Petitioner
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`asserted.4
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`4 Shin and Hector were not identified in Petitioner’s preliminary invalidity
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`contentions served January 24, 2020. See Ex. 1013, 034-035 (preliminary disclosure
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`of prior art references for