(12) United States Patent
`Shimoda et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,573,068 B2
`Aug. 11, 2009
`
`US007573068B2
`
`(54) TRANSISTOR ARRAY SUBSTRATE AND
`DISPLAY PANEL
`
`(75) Inventors: Satoru Shimoda, Fussa (JP); Tomoyuki
`Shirasaki, Higashiyamato (JP); Jun
`Ogura, Fussa (JP); Minoru Kumagai,
`Tokyo (JP)
`Casio Computer Co., Ltd., Tokyo (JP)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 769 days.
`
`(73)
`
`Assignee:
`
`(*)
`
`Notice:
`
`(21)
`(22)
`(65)
`
`Appl. No.:
`
`11/232,368
`
`Filed:
`
`Sep. 21, 2005
`
`Prior Publication Data
`US 2006/OO98521 A1
`May 11, 2006
`
`Foreign Application Priority Data
`(30)
`Sep. 21, 2004
`(JP)
`............................. 2004-273532
`Sep. 21, 2004
`(JP)
`............................. 2004-273580
`Sep. 16, 2005
`(JP)
`............................. 2005-269.434
`
`
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`Int. C.
`(2006.01)
`HOIL 3.3/
`(2006.01)
`HOIL 27/32
`U.S. Cl. .................. 257/72; 257/208; 257/E33.055
`Field of Classification Search ................... 257/59,
`257/72, 79, 81, 83, E33.064, E33.077, E27.131,
`257/E27.132, 208, E33.055; 313/500, 505;
`349/42, 139, 149, 73,74; 345/44, 45, 87-92
`See application file for complete search history.
`References Cited
`
`U.S. PATENT DOCUMENTS
`6,762,564 B2
`7/2004 Noguchi et al.
`
`90
`S.
`
`X
`2
`
`(s
`
`3, 2005 to
`6,864,639 B2
`8, 2005 Yamazaki et al.
`6,933,533 B2
`1/2008 Shirasaki et al.
`7,317,429 B2
`2004/0108978 A1* 6/2004 Matsueda et al. ............. 345/76
`
`FOREIGN PATENT DOCUMENTS
`
`CN
`JP
`
`T 2002
`1360350 A
`8-330600 A 12/1996
`
`(Continued)
`OTHER PUBLICATIONS
`
`A Japanese Office Action (and English translation thereof) dated Apr.
`30, 2008, issued in a counterpart Japanese Application.
`Primary Examiner Davienne Monbleau
`Assistant Examiner Shweta Mulcare
`(74) Attorney, Agent, or Firm Frishauf, Holtz, Goodman &
`Chick, P.C.
`
`(57)
`
`ABSTRACT
`
`A transistor array Substrate includes a plurality of driving
`transistors which are arrayed in a matrix on a Substrate. The
`driving transistor has a gate, a source, a drain, and a gate
`insulating film inserted between the gate, and the Source and
`drain. A plurality of signal lines are patterned together with
`the gates of the driving transistors and arrayed to run in a
`predetermined direction on the substrate. A plurality of Sup
`ply lines are patterned together with the sources and drains of
`the driving transistors and arrayed to cross the signal lines via
`the gate insulating film. The Supply line is electrically con
`nected to one of the source and the drain of the driving
`transistor. A plurality offeed interconnections are formed on
`the Supply lines along the Supply lines, respectively.
`
`17 Claims, 27 Drawing Sheets
`
`-1
`
`:
`
`-- Y
`
`22g
`
`A
`
`21g
`---
`21s / 2
`21
`
`A
`
`22. 22
`
`22s
`
`23d
`
`Hag ?
`
`23g
`
`24
`
`23s
`
`24A
`
`Pi,
`
`243
`A
`|s
`2
`2a r
`20c
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 001
`
`

`

`US 7,573,068 B2
`Page 2
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`
`2000-349298 A 12/2000
`2003-133079 A
`5, 2003
`2003-195810 A
`T 2003
`
`2003-330387 A 11, 2003
`JP
`2004-10 1948 A
`4, 2004
`JP
`WO WO 2004/019314 A1
`3f2004
`
`* cited by examiner
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 002
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 1 of 27
`
`US 7,573,068 B2
`
`
`
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 003
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 2 of 27
`
`US 7,573,068 B2
`
`
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 004
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 3 of 27
`
`US 7,573,068 B2
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`
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`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 005
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 4 of 27
`
`US 7,573,068 B2
`
`
`
`21 d
`
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`
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`
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`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 006
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
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`Sheet 5 Of 27
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`US 7,573,068 B2
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 007
`
`

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`LG Display Co., Ltd.
`Exhibit 1001
`Page 008
`
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
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`Sheet 7 Of 27
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`US 7,573,068 B2
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 009
`
`

`

`Sheet 8 of 27
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 010
`
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`gal/Wfi‘ifigiiigil’’Hflg“"i““““i“
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 011
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`Aug. 11, 2009
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 012
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 11 of 27
`
`US 7,573,068 B2
`
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`
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`
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`
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`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 013
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 12 of 27
`
`US 7,573,068 B2
`
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 014
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 13 Of 27
`
`US 7,573,068 B2
`
`SELECTION PERIOD
`OF PIXE CIRCUITS
`P, 1 TO Pi,
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME
`
`LIGHT EMISSION
`PERIOD OF PIXE
`CIRCUITS Pi, TO Pin
`
`
`
`
`
`
`
`
`
`VOLTAGE LEVEL
`OF SCAN LINE X
`
`VOAGE LEVEL OF FEED
`NTERCONNECTION 90
`AND SUPPLY LINE Zi
`
`WOLAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXELCIRCUITP
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXELCIRCUITP,
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINE Zi
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUITP,
`
`LIGHT EMISSION
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`P1, 1 TOP1,n
`
`LIGHT EMISSION
`PERIOD OF PEXEL
`CIRCUifs PT6P.,
`
`LIGHT EMISSION
`
`FIG.13
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 015
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 14 of 27
`
`US 7,573,068 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi, TO Pin
`
`LIGHT EMISSION
`PERIOD OF
`PRECEOING FRAME
`OF PXEL. CIRCUITS
`Pi, 1 TO Pin
`
`LIGHT EMISSION
`PERIOD OF PIXEL
`|CIRCUITS Pi, To Pi, n
`
`VOLTAGE LEVEL
`OF SCAN LINE X
`
`VOLTAGE LEVEL OF FEED
`NTERCONNECTION 90
`AND SUPPLY LINES
`Z- TOZm
`
`
`
`VOLTAGE LEVEL OF
`TRANSSTOR 23 OF
`PIXEL CIRCUITP,
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUITP,
`
`VOLTAGE LEVEL
`OF SCAN LINEXi.
`
`VOLTAGE LEVE OF
`TRANSISTOR 23 OF
`PIXEL CIRCUITP1,
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT Pi.1,
`
`
`
`LIGHT
`EMISSION
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`LIGHT
`EMISSION
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`LGHT
`EMISSION
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`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pitt, 1 TO Pi.1, n
`H
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`:
`PERIOD OF
`PRECEBINE FRAME
`OF PIXEL CRCUITS
`Pi.1, 1 TO Pin
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`EPs Pi.1, 1 TO
`P
`--it n
`LIGHT
`EMISSION
`
`FIG.14
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 016
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 15 Of 27
`
`US 7,573,068 B2
`
`ld A
`
`1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15
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`
`s Vpo
`
`FIG.15
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 017
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 16 of 27
`
`US 7,573,068 B2
`
`32-NCH PANEL
`
`
`
`
`
`MAXIMUM
`VOLTAGE
`DROPV)
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`
`7
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`9
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`4.
`p/SS2/cm)
`
`FIG.16
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 018
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 17 Of 27
`
`US 7,573,068 B2
`
`32-NCH PANE
`
`1.0x107
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`
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`250
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`FIG.17
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 019
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 18 of 27
`
`US 7,573,068 B2
`
`40-NCH PANEL
`
`
`
`
`
`I -1.
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`
`MAXIMUM
`VOLTAGE
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`F.G. 18
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 020
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 19 of 27
`
`US 7,573,068 B2
`
`1.0x107
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`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 021
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 20 Of 27
`
`US 7,573,068 B2
`
`
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 022
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 21 of 27
`
`US 7,573,068 B2
`
`C2
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`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 023
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 22 of 27
`
`US 7,573,068 B2
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 024
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 23 Of 27
`
`US 7,573,068 B2
`
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`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 025
`
`

`

`U.S. Patent
`
`Aug. 11,2009
`
`Sheet 24 of 27
`
`US 7,573,068 B2
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`Page 026
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`

`

`U.S. Patent
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`Aug. 11, 2009
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`Sheet 25 Of 27
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`US 7,573,068 B2
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`Page 027
`
`

`

`U.S. Patent
`
`Aug. 11,2009
`
`Sheet 26 of 27
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`US 7,573,068 B2
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`
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`
`FIG.27
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 028
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 028
`
`
`
`
`
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`
`
`
`
`
`
`

`

`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 27 Of 27
`
`US 7,573,068 B2
`
`SELECTION PERIOD
`OF PIXE CIRCUITS
`Pi, TO Pin
`LIGHT EMISSION
`PERIOD OF
`PRECEOING FRAME
`OF PIXEL CIRCUITS
`Pi, TOP,
`
`LIGHT EMISSION
`PERIOD OF PIXEL
`CIRCUITS Pi, 1 TO Pin
`
`WOLAGE LEVEL
`OF SCAN LINE X
`
`VOLTAGE LEVEL OF FEED
`INTER CONNECTION 90
`AND SUPPY LINES
`Z TOZm
`
`
`
`VOLAGE LEVEL OF
`TRANSSTOR 23 OF
`PIXELCIRCUITP
`
`CURRENT VALUE OF
`ORGANIC EELEMENT 20
`OF PIXELCIRCUITP,
`
`WOAGE LEVEL
`OF SCAN LINE X1
`
`LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi.1, 1 TOP1,n
`H
`
`VOLAGE LEVEL OF
`TRANSSTOR 23 OF H
`PIXEL CIRCUITP,
`LIGHTEMISSION
`LIGHTEMISSION
`PREEEEEESAME
`ESSEE
`OF PIXELCIRCUITS
`1, 1
`Pi.1, 1 TO Pi.1, n
`se-la---
`LIGHT
`EMISSION
`
`
`
`CURRENT VALUE OF
`ORGANIC EELEMENT 20
`OF PIXEL CIRCUITP1,
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 029
`
`

`

`US 7,573,068 B2
`
`1.
`TRANSISTOR ARRAY SUBSTRATE AND
`DISPLAY PANEL
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is based upon and claims the benefit of
`priority from prior Japanese Patent Applications No. 2004
`273532, filed Sep. 21, 2004; No. 2004-273580, filed Sep. 21,
`2004; and No. 2005-269434, filed Sep. 16, 2005, the entire
`contents of all of which are incorporated herein by reference.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`2
`to the electrode is also formed. For this reason, when the
`interconnection is formed from the conductive thin film, the
`thickness of the interconnection equals that of the thin-film
`transistor.
`The electrode of the thin-film transistor is designed assum
`ing that it functions as a transistor. In other words, the elec
`trode is not designed assuming that it Supplies a current to a
`light-emitting element. Hence, the thin-film transistor is thin
`literally. If a current is supplied from the interconnection to a
`plurality of light-emitting elements, a Voltage drop occurs, or
`the current flow through the interconnection delays due to the
`electrical resistance of the interconnection. To Suppress the
`Voltage drop or interconnection delay, the resistance of the
`interconnection is preferably low. If the resistance of the
`interconnection is reduced by making a metal layer serving as
`the source and drain of the transistor or a metal layer serving
`as the gate electrode thick, or patterning the metal layers
`considerably wide to sufficiently flow the current through the
`metal layers, the overlap area of the interconnection on
`another interconnection or conductor when viewed from the
`upper side increases, and a parasitic capacitance is generated
`between them. This retards the flow of the current. Alterna
`tively, in a so-called bottom emission structure which emits
`EL light from the transistor array substrate side, light emitted
`from the EL elements is shielded by the interconnections,
`resulting in a decrease in opening ratio, i.e., the ratio of the
`light emission area. If the gate electrode of the thin-film
`transistor is made thick to lower the resistance, a planariza
`tion film (corresponding to a gate insulating film when the
`thin-film transistor has, e.g., an inverted Stagger structure) to
`eliminate the step of the gate electrode must also be formed
`thick. This may lead to a large change in transistor character
`istic. When the source and drain are formed thick, the etching
`accuracy of the Source and drain degrades. This may also
`adversely affect the transistor characteristic.
`
`BRIEF SUMMARY OF THE INVENTION
`
`It is an object of the present invention to satisfactorily drive
`a light-emitting element while Suppressing any Voltage drop
`and signal delay.
`A transistor array Substrate according to a first aspect of the
`present invention comprises:
`a Substrate;
`a plurality of driving transistors which are arrayed in a
`matrix on the Substrate, each of the driving transistors having
`a gate, a source, a drain, and a gate insulating film inserted
`between the gate, and the source and drain;
`a plurality of signal lines which are patterned together with
`the gates of the plurality of driving transistors and arrayed to
`run in a predetermined direction on the Substrate;
`a plurality of Supply lines which are patterned together
`with the sources and drains of the plurality of driving transis
`tors and arrayed to cross the plurality of signal lines via the
`gate insulating film, each of the Supply lines being electrically
`connected to one of the Source and the drain of the driving
`transistor, and
`a plurality of feed interconnections which are formed on
`the plurality of Supply lines along the plurality of supply lines,
`respectively.
`Preferably, a substrate according to claim 1, further com
`prising a plurality of Scan lines which are patterned together
`with the sources and drains of the plurality of driving transis
`tors and arrayed to cross the plurality of Supply lines via the
`gate insulating film.
`Preferably, a substrate according to claim 2, which further
`comprises a plurality of Switch transistors which are arrayed
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`1. Field of the Invention
`The present invention relates to a transistor array Substrate
`having a plurality of transistors and, more particularly, to a
`display panel using light-emitting elements which cause self
`emission when a current is Supplied by the transistor array
`substrate.
`2. Description of the Related Art
`Organic electroluminescent display panels can roughly be
`classified into passive driving types and active matrix driving
`types. Organic electroluminescent display panels of active
`matrix driving type are more excellent than those of passive
`driving type because of high contrast and high resolution. In
`a conventional organic electroluminescent display panel of
`active matrix display type described in, e.g., Jpn. Pat. Applin.
`KOKAI Publication No. 8-330600, an organic electrolumi
`nescent element (to be referred to as an organic EL element
`hereinafter), a driving transistor which Supplies a current to
`the organic EL element when a Voltage signal corresponding
`to image data is applied to the gate of the transistor, and a
`Switching transistor which performs Switching to Supply the
`Voltage signal corresponding to image data to the gate of the
`driving transistor are arranged for each pixel. In this display
`panel, when a predetermined scan line is selected, the Switch
`ing transistor is turned on. At this time, a Voltage of level
`representing the luminance is applied to the gate of the driv
`ing transistor through a signal line. Thus, the driving transis
`tor is turned on. A driving current having a magnitude corre
`sponding to the level of the gate Voltage is Supplied from the
`power Supply to the organic EL element through the source
`to-drain path of the driving transistor. Consequently, the EL
`element emits light at a luminance corresponding to the mag
`45
`nitude of the current. During the period from the end of scan
`line selection to the next scan line selection, the level of the
`gate Voltage of the driving transistoris continuously held even
`after the Switching transistor is turned off. Hence, the organic
`EL element keeps emitting light at a luminance correspond
`ing to the magnitude of the driving current corresponding to
`the Voltage.
`To drive the organic electroluminescent display panel, a
`driving circuit is provided around the display panel to apply a
`Voltage to the Scanlines, signal lines, and power Supply lines
`laid on the display panel.
`In the conventional organic electroluminescent display
`panel of active matrix driving type, interconnections such as
`a power Supply line to Supply a current to an organic EL
`element are patterned simultaneously in the thin-film transis
`tor patterning step by using the material of a thin-film tran
`sistor Such as a Switching transistor or driving transistor.
`More specifically, in manufacturing the display panel, a con
`ductive thin film as a prospective electrode of a thin-film
`transistor is Subjected to photolithography and etching to
`form the electrode of a thin-film transistor from the conduc
`tive thin film. At the same time, an interconnection connected
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`LG Display Co., Ltd.
`Exhibit 1001
`Page 030
`
`

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`3
`in a matrix on the Substrate, each of the Switch transistors
`having the gate insulating film inserted between a gate and a
`Source and drain, and
`in which one of the source and drain of each of the plurality
`of switch transistors is electrically connected to the other of
`the source and drain of a corresponding one of the plurality of
`driving transistors,
`the gate of each of the plurality of switch transistors is
`electrically connected to the scan line through a contact hole
`formed in the gate insulating film, and
`the other of the source and drain of each of the plurality of
`Switch transistors is electrically connected to the signal line
`through a contact hole formed in the gate insulating film.
`Preferably, a substrate according to claim 2, which further
`comprises a plurality of holding transistors which are arrayed
`in a matrix on the Substrate, each of the holding transistors
`having the gate insulating film inserted between a gate and a
`Source and drain, and
`in which one of the source and drain of each of the plurality
`of holding transistors is electrically connected to the gate of a
`corresponding one of the plurality of driving transistors
`through a contact hole formed in the gate insulating film,
`the other of the source and drain of each of the plurality of
`holding transistors is electrically connected to one of the
`Supply line and the scan line, and
`the gate of each of the plurality of holding transistors is
`electrically connected to the scan line through a contact hole
`formed in the gate insulating film.
`A display panel according to a second aspect of the present
`invention is a display panel comprising:
`a Substrate;
`a plurality of driving transistors which are arrayed in a
`matrix on the Substrate, each of the driving transistors having
`a gate, a source, a drain, and a gate insulating film inserted
`between the gate, and the Source and drain;
`a plurality of signal lines which are patterned together with
`the gates of the plurality of driving transistors and arrayed to
`run in a predetermined direction on the Substrate;
`a plurality of Supply lines which are patterned together
`with the sources and drains of the plurality of driving transis
`tors and arrayed to cross the plurality of signal lines via the
`gate insulating film, each of the Supply lines being electrically
`connected to one of the source and the drain of the driving
`transistor, and
`a plurality offeed interconnections which are connected to
`the plurality of Supply lines along the plurality of supply lines;
`a plurality of pixel electrodes each of which is electrically
`connected to the other of the source and the drain of each of
`the plurality of driving transistors;
`a plurality of light-emitting layers which are formed on the
`plurality of pixel electrodes, respectively; and
`a counter electrode which covers the plurality of light
`emitting layers.
`Preferably, a panel according to claim 13, further compris
`ing a plurality of scan lines which are patterned together with
`the Sources and drains of the plurality of driving transistors
`and arrayed to cross the plurality of Supply lines via the gate
`insulating film.
`According to this aspect, the signal lines are patterned
`together with the gates of the driving transistors. However,
`since the feed interconnections are stacked on the Supply
`lines, the feed interconnections are formed separately for the
`drains, sources, and gates of the driving transistors. For this
`reason, the feed interconnection can be made thick without
`increasing its width, and the resistance of the feed intercon
`nection can be reduced. Hence, even when a signal is output
`
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`US 7,573,068 B2
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`5
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`4
`to the driving transistor and pixel electrode through the feed
`interconnection, the Voltage drop and signal delay can be
`Suppressed.
`When the feed interconnections are to be formed by elec
`troplating, the Supply lines are formed on the signal lines.
`When the structure is dipped in a plating solution while a
`Voltage is applied to the Supply lines in the manufacturing
`step of the transistor array Substrate and the display panel, the
`feed interconnections can be grown on the Supply lines.
`According to this aspect, since the feed interconnections
`can be made thick, the resistance of the feed interconnections
`can be reduced. When the resistance of the feed interconnec
`tions decreases, the signal delay and Voltage drop can be
`Suppressed.
`A display panel manufacturing method according to a dis
`play panel manufacturing method according to a fourth
`aspect of the present invention comprises; patterning a plu
`rality of pixel electrodes on a panel to be arrayed in a matrix:
`forming an interconnection made of metal between the pixel
`electrodes; coating a Surface of the interconnection with a
`liquid repellent conductive layer, and forming an organic
`compound layer by applying an organic compound-contain
`ing solution to the electrode.
`A thick interconnection can Suppress the Voltage drop and
`can also be used as a partition wall in forming an organic
`compound-containing Solution. Since the liquid repellent
`conductive layer exhibits liquid repellency, an organic com
`pound layer can satisfactorily be patterned. A liquid repellent
`conductive layer containing, e.g., a triazine compound can
`selectively beformed on a metal surface so as to exhibit liquid
`repellency but cannot beformed on the surface of an insulator
`or a metal oxide to exhibit liquid repellency. In addition, the
`liquid repellent conductive layer is formed on the metal sur
`face verythin. Hence, the electrical conductivity on the metal
`Surface is not lost.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`FIG. 1 is a view showing the circuit arrangement of an EL
`display panel together with an insulating Substrate;
`FIG. 2 is an equivalent circuit diagram of a pixel circuit of
`the EL display panel;
`FIG. 3 is a plan view showing the electrode of the pixel
`circuit of the EL display panel;
`FIG. 4 is a plan view showing the electrode of the pixel
`circuit of the EL display panel;
`FIG. 5 is a sectional view taken along a line V-V in FIG.3:
`FIG. 6 is a sectional view taken along a line VI-VI in FIG.
`3:
`FIG. 7 is a sectional view taken along a line VII-VII in FIG.
`3:
`FIG. 8 is a sectional view taken along a line VIII-VIII in
`FIG.3:
`FIG. 9 is a plan view showing a state wherein a gate layer
`is patterned;
`FIG.10 is a plan view showing a state wherein a drain layer
`is patterned;
`FIG. 11 is a plan view showing a state wherein the drain
`layer is Superposed on the patterned gate layer;
`FIG. 12 is a schematic plan view showing the layout of an
`organic EL layer of the EL display panel;
`FIG.13 is a timing chart for explaining a driving method of
`the EL display panel;
`FIG. 14 is a timing chart for explaining another driving
`method of the EL display panel;
`
`LG Display Co., Ltd.
`Exhibit 1001
`Page 031
`
`

`

`US 7,573,068 B2
`
`5
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`FIG. 15 is a graph showing the current vs. Voltage charac
`teristic of the driving transistor and organic EL element of
`each pixel circuit;
`FIG. 16 is a graph showing the correlation between the
`maximum Voltage drop and the interconnection resistivity
`p/sectional area S of the feed interconnection and common
`interconnection of a 32-inch EL display panel;
`FIG. 17 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec
`tion and common interconnection of the 32-inch EL display
`panel;
`FIG. 18 is a graph showing the correlation between the
`maximum Voltage drop and the interconnection resistivity
`p/sectional area S of the feed interconnection and common
`interconnection of a 40-inch EL display panel 1;
`FIG. 19 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec
`tion and common interconnection of the 40-inch EL display
`panel;
`FIG. 20 is a view showing the circuit arrangement of an EL
`display panel together with an insulating Substrate;
`FIG. 21 is an equivalent circuit diagram of a pixel circuit of
`the EL display panel;
`FIG. 22 is a plan view showing the electrodes of pixel
`circuits P, and P.
`of the EL display panel;
`FIG. 23 is a sectional view taken along a plane perpendicu
`lar to the channel width of a driving transistor;
`FIG. 24 is a sectional view taken along a line XXIV-XXIV
`in FIG.22;
`FIG.25 is a sectional view taken along a line XXV-XXV in
`FIG.22;
`FIG. 26 is a schematic view showing the coating structure
`of a liquid repellent conductive film;
`FIG. 27 is a schematic plan view showing the layout of the
`organic EL layers of the EL display panel; and
`FIG. 28 is a timing chart for explaining the operation of the
`EL display panel.
`
`6
`arrayed on the insulating Substrate 2 in a matrix along the
`signal lines Y to Y, and scan lines X to X. The feed inter
`connections 90 are provided in parallel to the supply lines Z.
`to Z, when viewed from the upper side. The common inter
`connections 91 are provided in parallel to the signal lines Y,
`to Y, when viewed from the upper side.
`In the following description, the direction in which the
`signal lines Y to Y, run will be defined as the vertical direc
`tion (column direction), and the direction in which the scan
`lines X to X, run will be defined as the horizontal direction
`(row direction). In addition, m and n are natural numbers
`(m22, n22). The Subscript added to a scan line X represents
`the sequence from the top in FIG.1. The subscript added to a
`supply line Z represents the sequence from the top in FIG. 1.
`The Subscript added to a signal line Y represents the sequence
`from the left in FIG. 1. The first subscript added to a pixel
`circuit Prepresents the sequence from the top, and the second
`subscript represents the sequence from the left. More specifi
`cally, let i bean arbitrary natural number of 1 to m, and be an
`arbitrary natural number of 1 to n, a scan line X, is the ith row
`from the top, a supply line Z, is the ith row from the top, a
`signal lineY, is the jth column from the left, and a pixel circuit
`P, is located on the ith row from the top and the jth column
`from the left. The pixel circuit P, is connected to the scan line
`X, Supply line Z, and signal line Y:
`The total number offeed interconnections 90 is m. A volt
`age VL to flow a write current and a voltage VH to flow a
`driving current are applied from a left terminal 90b and right
`terminal 90c on the insulating substrate 2 to each feed inter
`connection 90. For this reason, the voltage drop of the feed
`interconnection 90 can be suppressed Small as compared to
`when applying the voltages VL and VH from one of the left
`terminal 90b and right terminal 90c. The feed interconnec
`tions 90 are formed on the upper surfaces of the supply lines
`Z to Z, to be electrically connected to them.
`The total number of common interconnections 91 is n+1.
`Two common interconnections 91 adjacent in the row direc
`tion also function as partition walls to partition, in film for
`mation, organic EL layers 20b of organic EL elements (light
`emitting elements) 20 arranged between them. The common
`interconnections 91 are connected to a lead interconnection
`91a on the front side and to a lead interconnection 91b on the
`rear side. The lead interconnections 91a and 91b have the
`same thickness as the common interconnections 91 and also
`function as partition walls to partition the organic EL layers
`20b in the fore-and-aft direction in film formation. The com
`mon interconnections 91 are connected to an external device
`through interconnection terminals 91c. A common potential
`Vcom is applied to the common interconnections 91.
`In the EL display panel 1, regions partitioned in a matrix by
`the Scanlines X to X, and signal lines Y to Y, form pixels.
`Each of the pixel circuits P, to P, is provided in one region.
`Circuit Arrangement of Pixel Circuit
`The pixel circuits P. to P, have the same structure. So,
`the arbitrary pixel circuit P. of the pixel circuits P, to P,
`will be described. FIG. 2 is an equivalent circuit diagram of
`the pixel circuit P. FIGS. 3 and 4 are plan views mainly
`showing the electrode of the pixel circuit P. For the illustra
`tive convenience, FIG. 3 does not illustrate a pixel electrode
`20a of the pixel circuit P. FIG. 4 does not illustrate the
`electrode on the lower side of the pixel circuit P.
`The pixel circuit P. comprises the organic EL element 20
`serving as a pixel, three N-channel amorphous si