`
`1| ||||| IIIII Illll Ill I1III Ill ||1|| ||1| |||| l1 I11 11
`
`USOOS729504A
`
`United States Patent
`
`[19]
`
`Cowles
`
`[11]
`
`[45]
`
`Patent Number:
`
`5,729,504
`
`Date of Patent:
`
`Mar. 17, 1998
`
`[54]
`
`[75]
`
`['73]
`
`[21]
`
`[221
`
`[5 11
`[52]
`
`[58]
`
`[<61
`
`CONTINUOUS BURST EDO MEMORY
`DEVICE
`
`Inventor: Timothy B. Cowles, Boise, Id.
`
`Assignec: Micron Technology, Inc., Boise, Id.
`
`Appl. No.: 572,487
`
`Filed:
`
`Dec. 14, 1995
`
`Int. Cl.6
`us. (:1.
`
`GllC 8/00
`365/2311: 365/238.5; 365/239;
`395/496
`Field of Search ................................. 365/236, 238.5,
`365/239; 395/496
`
`Rofnmncos Cited
`
`“4DRAM 1991”. Toshiba America Electronic Components,
`Inc., pp. A—137—A—159.
`
`“Application Specific DRAM”. Toshiba America Electrvnic
`Components, Inc., C178, C-260, C 218. (1994).
`
`“Burst DRAM Function & Pinout". Oki Electric Ind., Co.,
`
`Ltd, 2nd Pnesentation, Item #619. (Sep. 1994)
`
`(List continued on next page.)
`
`Primary Examiner—David C. Nelms
`Assistant Examiner—F. Niranjan
`Attomey. Agent,
`or
`Firm—Schwcgman, Lundbcrg.
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0001
`
`
`
`5,729,504
` Page 2
`
`US. PATENT DOCUMENTS
`
`OTHER PUBLICATIONS
`
`
`
`3563/32
`taggg 1253:? £531: a].
`
`. 365/233
`4:685,089
`8/1937 Patel etal.
`
`
`..
`.. 3651239
`4,707,311
`11/1937 Takemae et 21.
`365/193
`4,738,667
`11/1933 Nakano ..........
`
`. 365/230
`4,870,622
`9/1939 Ana et a].
`365/193
`4,375,192 “”1989 Ma‘sumoto
`365/189.05
`5,053,066 10/1991 Yu ...............
`365/230
`5,126,975
`6/1992 Handy eta].
`. 365l189
`5257,2013 10/1993 Tobita .....
`
`5,263,865 12/1993 Takasugi
`................................. 365/189
`365/238 5
`3333 2:33: Emma 3‘ 31
`,
`wase
`.
`
`5,325,330
`6/1994 Morgan
`365/139.05
`5325502
`5,1994 McLaury
`395/425
`
`..
`.. 365/2335
`5,349,566
`9/1994 Memittetal.
`
`5,357,469 10l1994 Sommer et a1.
`..... 365/193
`5,373,227 12/1994 Keeth ................... 323/313
`
`........
`5,379,261
`111995 Jones, Jr.
`365/230
`ta].
`5,3
`39
`2/1
`5 M
`'
`365/18
`5,3370 4/1335 111121331253
`365/422
`
`
`..... 365/233
`5,452,261
`9/1995 Chung et a].
`..... 365/222
`5,457,659 10/1995 Schacfer
`
`5,526,320
`6/1996 Zagar et a1.
`365/2335
`
`“Hyper Page Mode DR 4M”, 8029 Electmnic Engineering,
`$3,941?“ 813' WOOIWICh’ L‘mdm" GB‘ PP” 4748’ (sep‘
`'
`.
`‘Mosel—Vltclic V53C8257H DRAM Specificanon Sheet. 20
`pages, Jul. 2, 199
`“PipelinedBurstDRAM”, Toshiba, JEDECJC42.3Hawaii,
`(Dec 1994)
`‘
`'
`“Samsung Synchronous DRAM”, Samsung Electronics, pp.
`146, (Mar. 1993).
`“Synchronous DRAM 2 MEG x 8 SDRAM", Micron Semi-
`_
`”Mum" 1“" PP' 2‘43 timing" 2 8'
`_
`.
`Dave Bursky, “Novel I/O Optmns and Innovatlve Archltec-
`turcs Let DRAMs Achieve SRAM Performance; Fast
`DRAMS can be swapped for SRAM Caches", Electronics
`Design, vol. 41, No. 15, Cleveland, Ohio. pp. 55—67, (Jul.
`22,1993).
`.
`.
`Shiva P- G°Wm~ 3‘ ‘1" “A 9NS~ 32K X 9» BICMOS m
`Syncmnous Cachc RAMWith BurstMode AOCCSS”~ IEEE,
`Custom Integrated Circuits Conference. pp. 781-786, (Mar.
`3, 1992).
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0002
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0002
`
`
`
`US. Patent
`
`Mar. 17, 1998
`
`Sheet 1 of 7
`
`5,729,504
`
`RAS“
`
`CAS“
`
`WE“
`
`22
`
`ROW DECODE
`
`AO-AQ
`
`ADDRESS
`
`
`
`COL.DECODE
`
`DATA
`OE“
`
`
`
`V0 LOGIC
`AND
`LATCHES
`
`42
`
`MEMORY
`ARRAY
`
`
`
`1 2
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0003
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0003
`
`
`
`US. Patent
`
`Mar. 17, 1998
`
`Sheet 2 of 7
`
`5,729,504
`
`52moan;N.9“.
`
`©¢h-v-m-N-m-ou_.
`
`
`
`méfié-To-m-N
`
`_-o-n-o-m-¢-m-m
`
`
`
`$90-50-TNLm
`
`m-ro-\.-o-mé-m
`
`
`
`m-N-Tofiékmuv
`
`
`
`N-m-o-Tmfiéh
`
`To.m-N-m-¢-\H©
`
`o-TNééfiéS
`
`m-m-vo.\.-o-m-v
`
`w-m.m-wo-h-m-m
`
`m+-m-m+o-g
`
`o-m-¢-m.m+o-n
`
`FOFOY—OY‘
`
`>
`
`>OO'I-V—
`
`01-1—00??-
`
`>
`
`>>>>>
`
`OOOPFFF’
`
`5.3m
`
`-'£93
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0004
`
` O
`
`1—07.0‘.
`
`98:9528::o<F<~<
`
`5:2009385
`
`mmmfig
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0004
`
`
`
`
`
`
`US. Patent
`
`Mar. 17, 1998
`
`Sheet 3 of 7
`
`5,729,504
`
`\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\>
`
`$2102$n.OE
`
`
`
`ch, LLC
`Patent Owner Monterey Resear
`Ex. 2001, 0005
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0005
`
`
`
`US. Patent
`
`Mar. 17, 1998
`
`Sheet 4 of 7
`
`5,729,504
`
`Cm<moan;¢.9...
`
`ch, LLC
`Patent Owner Monterey Resear
`Ex. 2001, 0006
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0006
`
`
`
`US. Patent
`
`Mar. 17, 1998
`
`Sheet 5 of 7
`
`5,729,504
`
`138
`
`141
`
`MODE
`
`CONTINUOUS
`
`122
`
`CONTROL
`
`
`RAS“
`
`CAS*
`
`WE*
`
`AO—A9
`ADDRESS
`
`DATA
`
`OE*
`
`ROW DECODE
`
`
`
`COUNTER COL.DECODE
`
`
`MEMORY
`ARRAY
`
`1 1 2
`
`I/OAthlc
`LATCHES
`
`142
`
`
`
`FIG. 5
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0007
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0007
`
`
`
`US. Patent
`
`Mar. 17, 1998
`
`Sheet 6 of 7
`
`5,729,504
`
`
`
`
`
`
`
`mlllllllgWIIIIIIIII;________*m<og*9». fillgfill;fill;
`Egg;”+8E55%
`
`
`§HOH§§E8H§E$Emom:
`
`¢_28WT
`
`V\\\\\\\\\\\\\
`
`IEEEEE25Na8_. _
`
`
`
`_____._______,m_m*m<o
`
`..
`
`rmé
`
`m*mg
`
`<0.oEm*m§
`
`0Q
`
`ch, LLC
`Patent Owner Monterey Resear
`Ex. 2001, 0008
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0008
`
`
`
`
`US. Patent
`
`hdan 17,1998
`
`Sheet 7 of 7
`
`5,729,504
`
`_mcoom
`
`_mcomm
`
`_mcovm
`
`~mcopm
`
`_mcom_
`
`
`
`__mcom_mcoN_
`
`_mcom
`
`_mcow
`
`_mcom
`
`
`
`<5.07.
`
`_mcoom
`
`_mcomm
`
`_mcowm
`
`_mco_w
`
`_mcomF
`
`
`
`__mcom_mcomfi
`
`_mcom
`
`_mcom
`
`_mcom
`
`m5.9...
`
`
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0009
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0009
`
`
`
`1
`CONTINUOUS BURST EDO MEMORY
`DEVICE
`
`TECHNICAL FIELD OF THE INVENTION
`
`The present invention relates generally to integrated cir-
`cuit memories and in particular the present invention relates
`to burst access memories.
`
`BACKGROUND OF THE INVENTION
`
`A wide variety of integrated circuit memories are avail-
`able for storing data. One type of memory is the dynamic
`random access memory (DRAM). A DRAM is designed to
`store data in memory cells formed as capacitors. The data is
`stored in a binary format; a logical “one” is stored as a
`charge on a capacitor. and a logical “zero“ is stored as a
`discharged capacitor. The typical DRAM is arranged in a
`plurality of addressable rows and columns. To access a
`memory cell, a row is first addressed so that all memory cells
`coupled with that row are available for accessing. Aftm' a
`row has been addressed. at
`least one column can be
`addressed to pinpoint at least one specific memory cell for
`either reading data from. or writing data to via external data
`communication lines. The data stored in the memory cells is,
`therefore, accessible via the columns.
`With the constant development of faster computer and
`communication applications.
`the data rates in which a
`memory circuit must operate continue to increase. To
`address the need for inqeased data rates. a variety of
`DRAMs are commercially available. These memories are
`produced in a variety of designs which provide difierent
`methods of reading from and writing to the dynamic
`memory cells of the memory. One such method is page
`mode operation. Page mode operations in a DRAM are
`defined by the method of accessing a row of a memory cell
`array and randomly accessing difi‘erent columns of the array.
`Data stored at the row and column intersection can be read
`
`and output while that column is accessed. Page mode
`DRAMs require access steps which limit the communication
`speed of the memory circuit.
`An alternate type of memory circuit is the extended data
`output (EDO) memory which allows data stored at a
`memory array address to be available as output after the
`addressed column has been closed. This memory circuit can
`increase some communication speeds by allowing shorter
`access signals without reducing the time in which memory
`output data is available on the communication lines. Column
`access times are.
`therefore. “mas
`” by providing the
`extended data output. A more detafled description of a
`DRAM having EDO features is provided in the “1995
`DRAM Data Boo ” pages 1—1 to 1—30 available from
`Micron Technology. Inc. Boise. Id.. which is incorporated
`herein by reference.
`Yet another type of memory circuit is a burst access
`memory which receives one address of a memory array on
`external address lines and automatically addresses a
`sequence of columns without the need for additional column
`addresses to be provided on the external address lines. By
`reducing the external address input signals. burst EDO
`memory circuits (BEDO) are capable of outputting data at
`significantly faster communication rates than the above
`described memory circuits.
`Although BEDO memories can operate at significantly
`faster data rates than non-burst memories, bursts of output
`data are terminated when changing from one memory row to
`another. The alternative to terminating a data burst is to wait
`until a data burst is complete until the memory row is
`
`5,729,504
`
`2
`
`changed. Changing memory rows is time consuming and
`because data is interrupted during the transition between
`rows, the data rate of the memory circuits is slowed
`For the reasons stated above, and for other reasons stated
`below which will become apparent to those skilled in the art
`upon reading and understanding the present specification,
`there is a need in the art for a burst access memory which
`allows a data burst to continue while receiving and address-
`ing a new memory row address.
`
`SUMMARY OF THE INVENTION
`
`The above mentioned problems with integrated memory
`circuits and other problems are addressed by the present
`invention and which will be understood by reading and
`studying the following specification. A burst access memory
`device is described which allows a new memory array row
`to be accessed while continually bursting data out from a
`prior memory row.
`In particular. the present invention describes a memory
`device comprising addressable memory elements. external
`address inputs. and an address counter for receiving an
`address on the external address inputs. The address counter
`also generates a sequence of addresses. The memory further
`comprises an output butter adapted to drive a sequence of
`data from the memory device. The output bufier circuitry
`can drive the sequence of data from the memory device
`while a new address is received by the address counter.
`In one embodiment. the memory includes a write enable
`signal input for receiving an enable signal. and termination
`circuitry for terminating an output of the sequence of data.
`In another embodiment. a memory device is described
`which comprises addressable memory elements arranged in
`rows and columns. external address inputs. and address
`circuitry for receiving row addresses and column addresses
`from the external address inputs. Counter circuitry is
`included for generating a sequence of column addresses in
`response to a first received column address. The memory
`also includes row access circuitry for accessing a row of
`memory elements in response to a received first row address.
`and an output bufl‘er for outputting a sequence of data from
`the memory device. The sequence of data being stored in the
`addressable memory elements having addresses correspond-
`ing to the sequence of addresses and the first row address.
`The memory further includes control circuitry for control-
`ling the output bufier circuitry and the access circuitry.
`wherein a second row of memory elements can be accessed
`without interrupting the output sequence of data from the
`first row address.
`
`In yet another embodiment. a method of burst reading
`data from a memory device having addressable memory
`elements arranged in rows and columns is described. The
`method comprises the steps of receiving a first row address.
`receiving a first column address. and accessing a row of
`memory elements having the first row address. The method
`also includes the steps of generating a sequence of column
`addresses starting at the first column address. outputting data
`stored at the sequence of column addresses. receiving a
`second row address. and accessing a row of memory ele-
`ments having the second row address while outputting the
`data stored at the sequence of column addresses.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`ID
`
`15
`
`25
`
`35
`
`45
`
`50
`
`55
`
`65
`
`FIG. 1 is a block diagram of a memory device incorpo-
`rating burst access;
`FIG. 2 illustrates linear and interleaved addressing
`sequences;
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0010
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0010
`
`
`
`3
`
`5,729,504
`
`4
`
`FIG. 3 is a timing diagram of a burst read followed by a
`burst write of the device of FIG. 1;
`
`FIG. 4 is a timing diagram of a burst write followed by a
`burst read of the device of FIG. 1;
`
`FIG. 5 is a block diagram of a memory device incorpo—
`rating the features of the present invention;
`FIG. 60 is a timing diagram of the operation of the device
`of FIG. 5;
`FIG. 6b is a continuation of the timing diagram of FIG.
`6a:
`
`FIG. 7a is a timing diagram of a series of continuous burst
`read operations; and
`FIG. 7b is a timing diagram of a series of burst read
`operations.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`In the following detailed description of the preferred
`embodiments. reference is made to the accompanying draw-
`ings which form a part hereof. and in which is shown by way
`of illustration specific preferred embodiments in which the
`inventions may be practiced. These embodiments are
`described in suflicient detail to enable those skilled in the art
`to practice the invention. and it is to be understood that other
`embodiments may be utilized and that logical, mechanical
`and electrical changes may be made without departing from
`the spirit and scope of the present inventions. The following
`detailed description is, therefore. not to be taken in a limiting
`sense, and the scope of the present inventions is defined only
`by the appended claims.
`
`BEDO Memories
`
`10
`
`IS
`
`25
`
`30
`
`35
`
`invention, a detailed
`To fully understand the present
`description is provided of a burst extended data output
`memory circuit (BEDO). FIG. 1 is a schematic representa-
`tion of a sixteen megabit device designed to operate in a
`burst access mode. The device is organized as a 2 Meg><8
`burst mm DRAM having an eight bit data input/output path
`10 providing data storage for 2.097.152 bytes of information
`in the memory array 12. An active-low row address strobe
`(RAS*) signal 14 is used to latch a first portion of a
`multiplexed memory address, from address inputs A0
`through A10 16, in latch 18. The latched row address 20 is
`decoded in row decoder 22. The decoded row address is used
`to select a row of the memory array 12. An active-low
`column address strobe (CAS*) signal 24 is used to latch a
`second portion of a memory address from address inputs 16
`into column address counter 26. The latched column address
`28 is decoded in column address decoder 30. The decoded
`column address is used to select a column of the memory
`array 12.
`In a burst read cycle. data within the memory array
`located at the row and column address selected by the row
`and column address decoders is read out of the memory
`array and sent along data path 32 to output latches 34. Data
`10 driven from the burst EDO DRAM may be latched
`external to the device with a CAS“ signal after a predeter-
`mined number of CAS“ cycle delays (latency). For a two
`cycle latency design. the first CAS" failing edge during a
`RAS“ cycle is used to latch the initial address for the burst
`access. The first burst data from the memory is driven from
`the memory after the second CAS“ falling edge, and remains
`valid through the third CAS“ failing edge. Once the memory
`device begins to output data in a burst read cycle. the output
`drivers 34 will continue to drive the data lines without
`
`Iii-stating the data outputs during CAS* high intervals
`dependent on the state of the output enable 42 and write
`enable 36 (013‘ and WE“) control lines. thus allowing
`additional time for the system to latch the output data. Once
`a row and a column address are selected, additional transi-
`tions of the CAS“ signal are used to advance the column
`address within the column address counter in a predeter—
`mined sequence. The time at which data will be valid at the
`outputs of the burst EDO DRAM is dependent only on the
`timing of the CAS“ signal provided that OE" is maintained
`low, and WE* remains high. The output data signal levels
`may be driven in accordance with standard CMOS, 'ITL,
`LV'I'I'L. GI‘L, or HSTL output level specifications.
`The address may be advanced linearly, or in an inter-
`leaved fashion for maximum compatibility with the overall
`system requirements. FIG. 2 is a table which shows linear
`and interleaved addressing sequences for burst lengths of 2,
`4 and 8 cycles. The “V” for starting addresses A1 andA2 in
`the table represent address values that remain unaltered
`through the burst sequence. The column address may be
`advanced with each CAS“ transition. When the address is
`advanced with each transition of the CAS“ signal, data is
`also driven from the part after each transition following the
`device latency which is then referenced to each edge of the
`CAS“ signal. This allows for a burst access cycle where
`CAS" toggles only once (high to low or low to high) for each
`memory cycle. This is in contrast to standard DRAMs which
`require CAS“ to go low and then high for each cycle, and
`synchronous DRAMs which require a full CAS“ cycle (high
`and low transitions) for each memory cycle.
`In the burst access memory device. each new column
`address from the column address counter is decoded and is
`used to access additional data within the memory array
`without the requirement of additional column addresses
`being specified on the address inputs 16. This burst sequence
`of data will continue for each CAS“ failing edge until a
`predetermined number of data accesses equal to the burst
`length has occurred. A CAS“ falling edge received after the
`last burst address has been generated will latch another
`column address from the address inputs l6 and a new burst
`sequence will begin. Read data is latched and output with
`each falling edge of CAS“ after the first CAS“ latency. For
`a burst write cycle, data 10 is latched in input data latches
`34. Data targeted at the first address specified by the row and
`column addresses is latched with the CAS* signal when the
`first column address is latched (write cycle data latency is
`zero). Other write cycle data latency values are possible;
`however. for today’s memory systems. zero is preferred.
`Additional input data words for storage at incremented
`column address locations are latched by CAS* on successive
`CAS” pulses. Input data from the input latches 34 is passed
`along data path 32 to the memory array where it is stored at
`the location selected by the row and column address decod-
`ers. As in the burst read cycle previously described. a
`predetermined number of burst access writes will occur
`without the requirement of additional column addresses
`being provided on the address lines 16. After the predeter-
`mined number of burst writes has occurred. a subsequent
`CAS“ will latch a new beginning column address. and
`another burst read or write access will begin.
`Control circuitry 38. in addition to performing standard
`DRAM control functions. controls the I/O circuitry 34 and
`the column address counter/latch 26. The control circuity
`determines when a cln'rent data burst should be terminated
`based upon the state of RAS“ 14. CAS“ 2A andWE* 36. The
`write enable signal is used in burst access cycles to select
`read or write burst accesses when the initial column address
`
`45
`
`50
`
`55
`
`65
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0011
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0011
`
`
`
`5,729,504
`
`5
`for a burst cycle is latched by CAS“. WE* low at the column
`address latch time selects a burst write access. WE* high at
`the column address latch time selects a burst read access.
`The level of the WE* signal must remain high for read and
`low for write burst accesses throughout the burst access. A
`low to high transition within a burst write access will
`terminate the burst access. preventing further writes from
`occurring. A high to low transition on WE* within a burst
`read access will likewise terminate the burst read access and
`will place the data output 10 in a high impedance state.
`Transitions of the WE* signal may be locked out during
`critical timing periods within an access cycle in order to
`reduce the possibility of triggering a false write cycle. After
`the critical timing period, the state of WE* will determine
`whether a burst access continues, is initiated, or is termi-
`nated. Termination of a burst access resets the burst length
`counter and places the DRAM in a state to receive another
`burst access command. In the case of burst reads, WE* will
`transition from high to low to terminate a first burst read, and
`then WE* will transition back high prior to the next falling
`edge of CAS" in order to specify a new bin-st read cycle. For
`burst writes, WE* would n'ansition high to terminate a
`current burst write access, then back low prior to the next
`falling edge of CAS* to initiate another burst write access.
`Both RAS“ and CAS" going high during a burst access will
`also terminate the burst access cycle placing the data drivers
`in a high impedance output state, and resetting the burst
`length counter.
`A basic implementation of the device of FIG. 1 may
`include a fixed burst length of 4. a fixed CAS“ latency of 2
`and a fixed interleaved sequence of burst addresses. Rather,
`just as fast page mode DRAMs and BBQ DRAMs are
`available in numerous configurations including x1, x4. x8
`and x16 data widths, and 1 Megabit, 4 Megabit, 16 Megabit
`and 64 Megabit densities; the burst access memory device of
`FIG. 1 may take the form of many different memory
`organizations.
`FIG. 3 is a timing diagram for performing a burst read
`followed by a burst write of the device of FIG. 1. In FIG. 3,
`a row address is latched by the RAS“ signal. WE* is low
`when RAS* falls for an embodiment of the design where the
`state of the WE* pin is used to specify a burst access cycle
`at RAS“ time. Next, CAS* is driven low with WE* high to
`initiate a burst read access. and the column address is
`latched. The data out signals (DQ’s) are not driven in the
`first CAS" cycle. On the second falling edge of the CAS"
`signal, the internal address generation circuitry advances the
`column address and begins another access of the array, and
`the first data out is driven from the device after a CAS“ to
`data access time (Tc-AC). Additional burst access cycles
`continue. for a device with a specified burst length of four,
`until the fifth failing edge of CAS* which latches a new
`column address for a new burst read access. WE* falling in
`the fifth CAS* cycle terminates the burst access. and ini—
`tializes the device for additional burst accesses. The sixth
`falling edge of CAS* with WE* low is used to latch a new
`burst address, latch input data and begin a burst write access
`of the device. Additional data values are latched on succes-
`sive CAS” failing edges until RAS" rises to terminate the
`burst access.
`
`FIG. 4 is a timing diagram depicting burst write access
`cycles followed by burst read cycles. As in FIG. 3. the RAS“
`signal is used to latch the row address. The first CAS* falling
`edge in combination with WE* low begins a burst write
`access with the first data being latched. Additional data
`values are latched with successive CAS“ falling edges, and
`the memory address is advanced internal to the device in
`
`5
`
`10
`
`15
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`6
`either an interieaved or sequential manner. 0n the fifth
`CAS" falling edge a new column address and associated
`write data are latched. The burst write access cycles continue
`until the WE* signal goes high in the sixth—CAS* cycle.
`The transition of the WE* signal terminates the burst write
`access. The seventh CAS“ low transition latches a new
`column address and begins a burst read access (WE* is
`high). The burst read continues until RAS" rises terminating
`the burst cycles.
`
`Continuous BEDO (CBEDO)
`
`FIG. 5 illustrates a continuous memory circuit which
`includes all of the features of the standard BEDO memory
`as described above. The continuous memory circuit.
`however, operates difi‘a‘ently than the previously described
`BEDO memory when the row access signal (RAS*) is
`inactive. That is, as explained above, a burst access opera-
`tion is terminated when the RAS" and the CAS“ signals go
`higr in a standard BEDO circuit. Time specifications for the
`BEDO circuitry dictates that the RAS" signal remain high
`for a minimum time of TRP (precharge time). Fm‘ther, a
`minimum access time TRAC. measured from the falling edge
`of RAS”, is required to access the new row. As a result, a
`new memory row cannot be accessed until a minimum time
`of TRAC+TRP has passed following the rising edge of RAS".
`Typical times for Tmc and Tm, are 60 us and 40 ns,
`respecn'vely. To eliminate this 100 us time period in which
`data is not being provided as output, circuitry is provided in
`control 139 of the memory circuit.
`FIG. Sis a schematic representation of a sixteen megabit
`device designed to operate in a burst access mode and
`incorporating the features of present invenn'on. The device is
`organized as a 2 MegXB burst EDO DRAM having an eight
`bit data input/output path 110 providing data storage for
`2,097,152 bytes of information in the memory array 112. An
`active-low row address strobe (RAS‘) signal 114 is used to
`latch a first portion of a multiplexed memory address, from
`address inputs AO through A10 116.
`in latch 118. The
`latched row address 120 is decoded in row decoder 122. The
`
`decoded row address is used to select a row of the memory
`array 112. An active-low column address strobe (CAS*)
`signal 124 is used to latch a second portion of a memory
`address from address inputs 116 into column address counter
`126. The latched column address 128 is decoded in column
`address decoder 130. The decoded column address is used to
`select a column of the memory array 112.
`In a burst read cycle. data within the memory array
`located at the row and column address selected by the row
`and column address decoders is read out of the memory
`array and sent along data path 132 to output latches 134.
`Data 110 driven fiom the burst EDO DRAM may be latched
`external to the device with a CAS* signal after a predeter—
`mined number of CAS* cycle delays (latency). Once the
`memory device begins to output data in a burst read cycle,
`the output drivers 134 will continue to drive the data lines
`without tri-stating the data outputs during CAS* high inter-
`vals dependent on the state of the output enable and write
`enable (OE* and WE*) control lines, thus allowing addi-
`tional time for the system to latch the output data. Once a
`row and a column address are selected, additional transitions
`of the CAS“ signal are used to advance the column address
`within the column address counter in a predetermined
`sequence. The time at which data will be valid at the outputs
`of the burst EDO DRAM is dependent only on the timing of
`the CAS" signal provided that 013* is maintained low. and
`WE* remains high. As with the memory of FIG. 1. the
`output data signal levels may be driven in accordance with
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0012
`
`Patent Owner Monterey Research, LLC
`Ex. 2001, 0012
`
`
`
`7
`
`8
`
`5,729,504
`
`standard CMOS, TI'L, LV'ITL, GI'L, or HSTL output level
`specifications. Further,
`the address may be advanced
`linearly, or in an interleaved fashion for maximum compat-
`ibility with the overall system requirements as shown in
`FIG. 2.
`
`In the burst access memory device, each new column
`address from the column address counter is decoded and is
`used to access additional data within the memory array
`without the requirement of additional column addresses
`being specified on the address inputs 116. This burst
`sequence of data will continue for each CAS“ falling edge
`until a predetermined number of data accesses equal to the
`burst length has occurred. A CAS" falling edge received
`after the last burst address has been generated will latch
`another column address from the address inputs 116 and a
`new burst sequence will begin. Read data is latched and
`output with each falling edge of CAS“ after the first CAS“
`latency.
`Input data from the input latches 134 is passed along data
`path 132 to the memory array where it is stored at the
`location selected by the row and column address decoders.
`As in the burst read cycle previously described, a Indeter-
`mined number of burst access writes will occur without the
`requirement of additional column addresses being provided
`on the address lines 116. After the predetermined number of
`burst writes has occurred, a subsequent CAS“ will latch a
`new beginning column address. and another burst read or
`write access will begin.
`The write enable signal is used in burst access cycles to
`select read or write burst accesses when the initial column
`address for a burst cycle is latched by CAS“. WE* low at the
`column address latch time selects a burst write access. WE"
`high at the column address latch time selects a burst read
`access. The level of the WE" signal must remain high for
`read and low for write burst accesses throughout the burst
`access. A low to high transition within a burst write access
`will terminate the burst access, preventing further writes
`from occurring. A high to low transition on WE" within a
`burst read access will likewise terminate the burst read
`access and will place the data output 110 in a high imped-
`ance state. Transitions of the WE* signal may be locked out
`during critical timing pm-iods within an access cycle in order
`to reduce the possibility of triggering a false write cycle.
`After the critical timing period,
`the state of WE“ will
`determine whether a burst access continues. is initiated. or is
`terminated. Termination of a burst access resets the burst
`length counta and places the DRAM in a state to receive
`another burst access command.
`
`10
`
`15
`
`25
`
`35
`
`45
`
`just as fast page mode DRAMs and EDO DRAMs are
`available in numerous configurations including x1, x4, x8
`and x16 data widths, and 1 Megabit, 4 Megabit, 16 Megabit
`and 64 Megabit densities; the burst access memory device of
`FIG. 5 may take the form of many different memory
`organizations.
`FIGS. 60 and 6b is a timing diagram for performing a
`continuous burst read of the device of FIG. 5. In FIGS. 60
`and 6b, row address 1 is latched on the first failing edge of
`the RAS“ signal. WE" is low when RAS" falls for an
`embodiment of the memory device where the state of the
`WE" pin is used to specify a burst access cycle at RAS"
`time. Next, with WB“ nigh. CAS“ is driven low to initiate
`a burst read access. and column address to is latched. The
`data out signals (DQ’s) are not driven in the first CAS“
`cycle, but remain tri-state. 0n the second falling edge of the
`CAS* signal, data stored at column In is output on the DQ
`lines after a CAS“ to data access time (Tao-)- On the rising
`edges of CAS“, the intanal address generation circuitry
`advances the column address. Data stored at column
`addresses m+1, m+2. and m+3 are output on the falling
`edges of CAS“. After column address 111 is latched, the
`RAS* signal goes high to begin the sequence of accessing a
`new row. While data is being provided on the DQ lines from
`row 1, RAS“ goes low to latch a new row address (2) fiom
`the address inputs. It will be appreciated that the RAS*
`signal transitioned big: and low without interrupting the
`data output on the DQ lines. A new column address will be
`loaded on the last CAS“ cycle of a burst, For example in
`FIGS. 6a and 6b. a new column address (n) is latched on the
`first CAS“ active transition following the beginning of the
`RAS“ cycle. The bmst read operation continues uninter-
`rupted for rows 2 and 3, and columns 11. o, and p. To
`terminate a continuous burst read operation, the WE“ signal
`merely has to transition high prior to a falling edge of the
`CAS“ signal.
`It will be appreciated that the read and write operations
`performed on a single memory row of the memory of FIG.
`5 are identical to the operation of the memory of FIG. 1 as
`shown in FIG. 3. That is, after completing a burst read. the
`WE“ signal transitions low and the next falling edge of
`CAS“ latches a new column address for a burst write
`operation. Likewise, the timing diagram of FIG. 4 depicting
`burst write access cycles followed by burst read cycles can
`be replicated with the memory of the present invention. As
`such. BEDO memory devices can be replaced with CBEDO
`memory devices without eifecting the operation of the
`memory support system. It will further be appreciated by
`those skilled in the art that the memory device of FIG. 5 can
`operate with burst lengths of 2, 4. 8. or full row cycles.
`FIGS. 7a and 7b are provided to more clearly illustrate the
`advantages of the CBEDO memory over BEDO memory
`devices. The timing diagram of FIG. 7a shows one possible
`series of burst read operations on four difi’erent memory
`rows (R1, R2, R3 and R4) in a CBEDO memory device.
`FIG. 7b shows burst read operations in a BEDO memory
`device. 0n the first CAS“ cycle of the