Case IPR2020-00985
`U.S. Patent No. 6,651,134
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________________________________
`
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`__________________
`
`Case IPR2020-00985
`
`U.S. Patent No. 6,651,134
`__________________
`
`
`
`PATENT OWNER SUR-REPLY
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`TABLE OF CONTENTS
`
`Page
`Introduction ...................................................................................................... 1 
`I. 
`II.  Wada Does Not Invalidate The ’134 Patent Claims. ....................................... 2 
`A.  Wada Does Not Disclose Non-Interruptible Bursts .............................. 2 
`1. 
`Neither Wada’s Conventional Nor Second Embodiment
`Prevents Interruptions Of Individual Bursts ............................... 2 
`Non-Interruptible Bursts Are Not Obvious Over Wada ............. 5 
`2. 
`B.  Wada Does Not Teach Generating A Predetermined Number Of
`Internal Address Signals ........................................................................ 7 
`1. 
`Generating At Most 2^k States IS NOT the same as
`Generating A Predetermined Number of Internal Address
`Signals ......................................................................................... 7 
`2.  Wada’s and the ’134 Patents ADV Signals Are Not The
`Same Signal And Operate Differently ........................................ 8 
`III.  AMD Incorrectly Argues That An Uninterruptible Burst Transfer Was
`Not New ........................................................................................................... 9 
`IV.  Wada And Barrett Do Not Render Obvious The ’134 Patent Claims ........... 11 
`A. 
`The Differences in Data Transfer Speed and Protocols
`Demonstrate That Wada and Barrett Are Directed to Different
`Bursts ................................................................................................... 11 
`B.  Wada and Barrett Defeat Each Other’s Goals..................................... 13 
`Secondary Indicia Of Non-Obviousness Demonstrate That The
`Challenged Claims Are Not Obvious Over Wada, Alone Or In
`Combination With The Secondary References ............................................. 14 
`A. 
`The Claimed Invention Of The ’134 Patent Solves A Long-Felt
`Need. .................................................................................................... 14 
`A Nexus Exists Between The Claimed Invention Of The ’134
`Patent And Non-Interruptible DDR SDRAM Technology. ................ 16 
`
`V. 
`
`B. 
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`Case IPR2020-00985
`Page(s)
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`U.S. Patent No. 6,651,134
`VI.  Conclusion ..................................................................................................... 18 
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
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`PATENT OWNER’S EXHIBIT LIST
`
`Exhibit No.
`2001
`2002
`2003
`
`2004
`2005
`2006
`2007
`
`2008
`2009
`
`2010
`
`2011
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`2012
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`2013
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`2014
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`2015
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`2016
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`2017
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`2018
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`2019
`2020
`
`DESCRIPTION
`U.S. Patent No. 5,729,504 to Cowles (“Cowles”)
`U.S. Patent No. 6,289,138 to Yip (“Yip”)
`Declaration In Support Of Patent Owner Monterey Research, LLC’s
`Unopposed Motion For Admission Pro Hac Vice Of Michael A.
`Wueste.
`Declaration Of Michael C. Brogioli, Ph.D.
`Curriculum Vitae Of Michael C. Brogioli, Ph.D.
`2021-02-12 Deposition Transcript of Dr. R. Jacob Baker.
`Excerpts Of R. JACOB BAKER ET AL., DRAM CIRCUIT DESIGN
`FUNDAMENTAL AND HIGH-SPEED TOPICS, IEEE Press (2008)
`https://www.transcend-info.com/Support/FAQ-296
`PCI Local Bus Specification, Production Version Revision 2.1 (June
`1, 1995)
`JEDEC Standard – Double Data Rate (DDR) SDRAM, JESD79F,
`JEDEC Solid State Technology Association.
`JEDEC Standard – DDR2 SDRAM Specification, JESD79-2B,
`JEDEC Solid State Technology Association.
`JEDEC Standard – Low Power Double Data Rate 3 (LPDDR3),
`JESD209-3, JEDEC Solid State Technology Association.
`JEDEC Standard – Low Power Double Data Rate 4 (LPDDR4),
`JESD209-4, JEDEC Solid State Technology Association.
`JEDEC Standard – DDR3 SDRAM Standard, JESD79-3F, JEDEC
`Solid State Technology Association.
`JEDEC Standard – DDR4 SDRAM, JESD79-4B, JEDEC Solid State
`Technology Association.
`JEDEC Standard – Graphics Double Data Rate (GDDR5) SGRAM
`Standard, JESD212C, JEDEC Solid State Technology Association.
`JEDEC Standard – Graphics Double Data Rate (GDDR5X) SGRAM
`Standard, JESD232A, JEDEC Solid State Technology Association.
`JEDEC Standard – Graphics Double Data Rate (GDDR6) SGRAM
`Standard, JESD250B, JEDEC Solid State Technology Association.
`https://www.intel.com/pressroom/kits/quickrefyr.htm
`https://web.archive.org/web/20000818114318/http://www.cypress.c
`om/press/releases/990726.html
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`U.S. Patent No. 6,651,134
`All citations to specific pages of exhibits follow the pagination added to those
`exhibits per 37 C.F.R. § 42.63(d)(2)(i).
`
`All emphasis added unless specified otherwise.
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`U.S. Patent No. 6,651,134
`I.
`Introduction
`
`AMD’s Reply continues to mischaracterize Wada in an attempt to read
`
`disclosure into Wada that simply is not there. Wada is directed to preventing
`
`interruptions between two bursts and discloses a signal (“ADV”) that controls
`
`whether or not a single burst output will be interrupted. AMD has not demonstrated,
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`and cannot demonstrate, that Wada discloses non-interruptible bursts. AMD has
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`also failed to demonstrate that Wada teaches generating a predetermined number of
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`internal address signals.
`
`AMD’s Reply further fails to address and rebut Monterey’s detailed and
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`thorough explanation regarding why a person of ordinary skill in the art (“POSITA”)
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`would not have been motivated to combine Wada and Barret. Instead, AMD glosses
`
`over those very issues, characterizing the reasons for not combining Wada and
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`Barrett as a “protracted discussion of the differences between Wada and Barrett.”
`
`AMD Reply (“Reply”), 17.
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`Finally, AMD’s discussion on the secondary indicia of non-obviousness
`
`mischaracterizes the long-felt need identified in Monterey’s Response and provides
`
`an alleged “solution” to the long-felt need that the Examiner already considered and
`
`rejected during prosecution.
`
`For each of these independent reasons, the Board should find in favor of Patent
`
`Owner on all issues.
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`U.S. Patent No. 6,651,134
`II. Wada Does Not Invalidate The ’134 Patent Claims.
`
`A. Wada Does Not Disclose Non-Interruptible Bursts
`1.
`
`Neither Wada’s Conventional Nor Second Embodiment
`Prevents Interruptions Of Individual Bursts
`
`Wada does not disclose preventing interruptions within bursts; AMD attempts
`
`to read that concept into Wada. In Wada, “a data free-period (an interruption in the
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`flow of data output) is bound to occur between two burst outputs, one relating to
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`the current memory address An, the other associated with the next memory address
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`Am.” U.S. Patent No. 6,115,280 (“Wada” or “Ex-1005”), 5:50-53. That is, Wada
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`prevents interruptions between two burst outputs, i.e., a first burst output
`
`corresponding to memory address An and a second burst output corresponding to
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`memory address Am. Wada does not relate to preventing interruptions within
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`burst outputs, e.g., within the first or the second burst outputs.
`
`AMD mischaracterizes Wada and redefines a “data free-period” to include
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`“interruptions either within or between bursts.” AMD Reply (“Reply”), 4. But
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`neither of Wada’s conventional and second embodiments discloses preventing
`
`interruptions of individual bursts because, in either embodiment, a burst may be
`
`terminated at any time by failing to maintain the external advance signal “ADV”
`
`high. Patent Owner Response (“POR”), 29. Dr. Brogioli Decl. (“Ex-2004”), ¶132.
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`The Board correctly acknowledged that Wada’s embodiments “disclose systems in
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`which the internal address increments for burst operation only when an external
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`U.S. Patent No. 6,651,134
`signal (ADV) is maintained in a particular state.” DI, 17. The Board properly
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`concluded that Wada disclosed a method of terminating a burst before it completed.”
`
`See id. [“[W]e do not agree with Petitioner that Wada discloses no method of
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`terminating a burst before it has completed.”]
`
`AMD does not and cannot point to any express disclosure in Wada directed
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`to preventing interruptions within bursts. See e.g., Reply, 2-5. Instead, AMD makes
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`the conclusory assertion that “[a]llowing an interruption within a burst would defeat
`
`Wada’s entire purpose and was a problem that had already been solved in the first
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`conventional embodiment and did not need to be solved again.” Id., 4. But AMD
`
`is mistaken. Wada’s stated purpose was to address interruptions between burst
`
`outputs, i.e., an interruption following a burst output. See Ex-1005, 5:54-57
`
`(“Suppose that a data output interruption of one cycle period occurs following each
`
`burst output lasting four cycles. In that case, if one burst output is taken as a single
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`period, the data transfer period is prolonged by 20 percent.”)
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`Contrary to AMD’s allegation, Monterey’s expert did not testify that Wada’s
`
`description of Figure 4 showing data being output uninterrupted applies to a single
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`burst. See Reply, 5 (citing to Ex-1015, 211:23-212:7.) Rather, Dr. Brogioli’s
`
`testimony refers to Wada’s second embodiment, in which a second burst
`
`(corresponding to address Am) involves the “above-described actions [being] carried
`
`out continuously.” Ex-1005, 16:7-8. The “above described actions” involve
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`admitting a second address Ax simultaneously with a first address An, such that data
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`corresponding to An is burst output while data corresponding to Ax is transferred by
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`the multiplexer—therefore, there is no interruption between data burst from An and
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`data burst from Am (see, e.g., Ex-1005:15:30-16:3.) Wada then states that these
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`actions, plus the use of three or more output registers, provide the same advantage
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`of the first embodiment: “the ability to execute data burst output in uninterrupted
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`fashion” between bursts. Ex-1005, 16:11-15. Therefore, Wada’s second
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`embodiment addresses interruptions between burst outputs, i.e., an interruption
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`following a burst output.
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`In any event, both Wada’s conventional and inventive embodiments use the
`
`same signaling—including requiring that the ADV signal be high in order to
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`advance addresses, thereby allowing control of whether a burst is interrupted or not,
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`by controlling the ADV signal, i.e., de-asserting the signal will interrupt a burst
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`output.
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`Finally, AMD inappropriately introduces a new inherency argument in its
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`Reply. See PTAB Consolidated Trial Practice Guide, 73-74 (Nov. 2019). “Petitioner
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`may not submit new evidence or argument in reply that it could have presented
`
`earlier, e.g. to make out a prima facie case of unpatentability.” Specifically, AMD
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`argues for the first time in its Reply that “[b]ecause the data corresponding to address
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`Am is a single burst, this teaching of uninterrupted output must refer to
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`eliminating interruptions within a burst.” Reply, 4. First, this conclusory
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`statement does not satisfy the high standard for showing inherency. Second, the
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`teaching regarding addressing Am does not mention or concern eliminating
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`interruptions during that burst output. And finally, the only explicit disclosure in
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`Wada about eliminating interruptions, concerns interruptions between bursts, not
`
`during a burst. Therefore, in any case, AMD’s belated and inappropriate inherency
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`argument fails.
`
`2.
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`Non-Interruptible Bursts Are Not Obvious Over Wada
`
`In the Reply, AMD repeats its unsupported, conclusory assertion that “it
`
`would have been obvious to a POSA not to interrupt Wada’s bursts…” Reply, 6.
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`But AMD offers no evidence – including any expert testimony – about why a POSA
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`ostensibly would have found it obvious to not interrupt an individual burst. Wada’s
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`teaching about outputting data without interruptions refers to interruptions between
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`bursts. Ex-1005, 6:3–7. As the Institution Decision correctly observed, “Wada’s
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`disclosure of operating ‘without causing data output interruptions’ refers to inter-
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`burst interruptions and does not justify a modification that would render bursts non-
`
`interruptible.” Paper 13, 19.
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`AMD does not explain why its proposed modification, i.e., not interrupting
`
`single bursts, would justify or outweigh relinquishing control over whether a burst
`
`can be interrupted. Wada’s system was designed and built with the ability to
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`interrupt bursts, for example, to control the rate data is received and consumed by
`
`receiving devices. AMD’s proposed modification would force Wada’s system to
`
`lose control over the rate data is output from the memory and is received
`
`downstream. AMD provided not comparison about the benefits and drawbacks of
`
`its proposed modification.
`
`In fact, as Dr. Brogioli explained, before the invention of the ’134 Patent
`
`memory devices would interrupt bursts in SRAM or DRAM. For example, “burst
`
`accesses of JEDEC-compliant SDRAM were interruptible before the invention of
`
`the ’134 Patent. Indeed, the first JEDEC DDR SDRAM standard—JEDEC Standard
`
`No. JSD79, first published in 2000—included a “BURST TERMINATE” command
`
`that would truncate a burst operation before the full burst length was reached.” Ex-
`
`2004, ¶221. The “BURST TERMINATE” command would be issued, for example,
`
`to avoid overflow of the buffers in the receiving device, when the memory would
`
`output data in a rate higher than the ability of the receiving device to consume the
`
`data from memory. Therefore, at least in some systems there were well-known
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`benefits in connection with the ability to interrupt burst outputs and a POSITA would
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`not have been motivated to remove the ability to interrupt such burst outputs.
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`B. Wada Does Not Teach Generating A Predetermined Number Of
`Internal Address Signals
`1. Generating At Most 2^k States IS NOT the same as
`Generating A Predetermined Number of Internal Address
`Signals
`
`Wada also does not disclose the “generat[ing] a predetermined number of
`
`said internal addresses” limitation. AMD continues to confuse Wada’s ability to
`
`generate as many as 2^k internal addresses with the separate issue of actually
`
`generating a predetermined number of internal addresses. Specifically, AMD
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`alleges that “Wada’s burst counter of Figure 12 can generate 2^k internal addresses
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`for a given external address, which is a predetermined number.” Reply, 7-8. But
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`Wada’s ability (“can generate”) to generate up to 2^k internal addresses, does not
`
`mean or suggest that Wada will actually generate 2^k internal addresses. In Wada,
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`2^k merely represents a potential range of states. As Dr. Brogioli explained, “the
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`burst counter described in Wada’s conventional embodiment blindly increments
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`addresses every clock cycle as long as an external signal—the external advance
`
`signal ADV—is maintained high.” Ex-2004, ¶111. Dr. Brogioli further explained
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`that “[i]f the external advance signal ADV is released … before AMD’s arbitrary
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`and unsupported ‘2^k’ … alleged burst limits are reached, Wada’s burst counters
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`will increment and generate less than ‘2^k’ … internal addresses. If the external
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`advance signal ADV is released … after AMD’s arbitrary and unsupported ‘2^k’ …
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`U.S. Patent No. 6,651,134
`alleged burst limits are reached, Wada’s burst counters will wrap around and
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`increment and generate more than ‘2^k’ … internal addresses.” Id.
`
`2. Wada’s and the ’134 Patents ADV Signals Are Not The Same
`Signal And Operate Differently
`
`AMD assumes that because Wada and the ’134 Patent both identify in their
`
`disclosures an external signal with the same name (“ADV”), Wada’s ADV signal is
`
`no different from ’134 Patent’s ADV signal. See Reply, 8. But AMD is mistaken.
`
`The ADV signal of the ’134 Patent starts the address generation procedure and the
`
`’134 Patent contains explicit language that the generation of addresses is non-
`
`interruptible. For example, the ’134 Patent teaches that “[w]hen the signal ADV is
`
`asserted, the circuit 100 will generally begin transferring a predetermined number of
`
`words. The transfer is generally non-interruptible.” U.S. Patent No. 6,651,134 (“Ex-
`
`1001”), 3:6-13. The ’134 Patent further teaches that “[o]nce the circuit 102 has
`
`started generating the fixed number of addresses, the circuit 102 will generally not
`
`stop until the fixed number of addresses has been generated (e.g., a non-
`
`interruptible burst). Id., 3:25-28. Therefore, the ’134 Patent provides explicit
`
`disclosure that burst outputs are non-interruptible.
`
`In contrast, Wada’s ADV signal does not start the address generation process;
`
`rather it is required for incrementing the address on a burst counter. See Ex-1005,
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`2:55-59. (“[W]hen the advance signal ADV is brought High, the address on the burst
`
`counter 84 is incremented every time a leading edge of the clock Signal CLK is
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`encountered.”) Importantly, Wada does not teach that incrementing the address is
`
`performed uninterruptedly. AMD alleges that “both the ’134 Patent and Wada
`
`describe systems that are non-interruptible only when used in accordance with the
`
`teachings of the patents.” Reply, 12 (emphasis in original). But AMD does not
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`point to any such teaching in Wada.
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`AMD also incorrectly suggests that in the ’134 Patent “if the bursts started
`
`and the signal ADV/LDb were driven to the first state,” that would load in a new
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`starting address (Reply, 11) and that holding the clock low would interrupt the
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`generation of internal addresses. Id., 12. But these suggestions go against the
`
`explicit teachings of the ’134 Patent. See, e.g., Ex-1001, 3:6-13, 3:25-28. Moreover,
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`AMD’s suggestion to stop the clock defeats the actual operation of the disclosed
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`systems. Id. A synchronous (i.e., clocked) system requires the clock to operate.
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`Holding the clock low, as AMD suggests, would not result in uninterrupted bursts,
`
`because without a clock, there would be no bursts to interrupt.
`
`III. AMD Incorrectly Argues That An Uninterruptible Burst Transfer Was
`Not New
`
`AMD alleges that making a burst transfer uninterruptible was not new merely
`
`because (1) the ’134 Patent is not limited to DRAM or SRAM memories and (2)
`
`DRAM and SRAM face different problems. See Reply, 13-16. AMD is mistaken.
`
`First, the mere fact that the ’134 Patent identifies one problem with DRAM
`
`memories and a second problem with SRAM memories—and its proposed solution
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`addresses both—does not mean the proposed non-interruptible solution is not new.
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`Rather, the “non-interruptible bursts” for the ’134 Patent apply to SRAM memories
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`because “the burst mode of a conventional synchronous SRAM memories can be
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`started and stopped in response to a control signal.” Ex-1001, 1:16-18. And even if
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`SRAM memories do not suffer from the need to refresh its contents, SRAM
`
`memories can still benefit from uninterrupted bursts. For example, bursts create
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`uncertainties to the exact timing of a data transfer and therefore can adversely affect
`
`the performance and efficiency of a memory system. SRAM memories can benefit
`
`from uninterrupted bursts because uninterrupted bursts offer determinism in the data
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`transfers and remove any speculation about when all the data will be transferred.
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`Second, AMD alleges that, even for DRAM systems, the problem of dealing
`
`with periodic refresh interruptions had already been solved. But the hiding of
`
`DRAM refreshes is a problem that can have many different solutions, each with
`
`different advantages. AMD points to U.S. Patent No. 6,226,755 (“Reeves” (“Ex-
`
`1008”)), which addresses the problem by partitioning, such that one partition is
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`pre-charged while the other bursts. But this solution is the same as the solution
`
`disclosed in U.S. Patent No. 5,729,504 to Cowles (“Ex-2001”), which was identified
`
`in the ’134 Patent’s prosecution history. Cowles’s—and therefore Reeves’s—
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`proposed solution does not address the ’134 Patent’s solution to the issue, which
`
`does not need to partition the memory to achieve non-interruptible bursts.
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`Finally, the mere fact that the burst counter itself was well-known does not
`
`mean that non-interruptible bursts were well-known.
`
` AMD confuses an
`
`implementation detail with the actual invention of the ’134 Patent.
`
`IV. Wada And Barrett Do Not Render Obvious The ’134 Patent Claims
`A. The Differences
`in Data Transfer Speed and Protocols
`Demonstrate That Wada and Barrett Are Directed to Different
`Bursts
`
`AMD ignores Patent Owner’s argument about Wada and Barret being directed
`
`to different bursts. For example, the bursts in Barrett focus on data transfers from
`
`peripheral devices over different technology, such as Peripheral Component
`
`Interconnect (“PCI”). Ex-2004, ¶¶63-64. In contrast, the bursts in Wada are directed
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`to burst transactions, for example, from a DRAM memory. A memory burst is an
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`atomic and non-interruptible burst operation whereas a peripheral device burst
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`operation requires multiple phases, such as initialization, transfer, conclusion, as
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`Barrett discloses. Id. ¶64.
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`Moreover, Barrett’s system employs PCI and similar technologies that operate
`
`in data transfer rates that are approximately in the 133MB/sec range. USB
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`technologies are even slower. This is an order of magnitude slower than the
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`CPU/memory transfer rates that Wada contemplates. Ex-2004, ¶63-64. Different
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`systems that operate in speeds in different orders of magnitude face many different
`
`challenges.
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`AMD allegation that “Monterey’s protracted discussion of the differences
`
`between Wada and Barrett and the protocols and data transfer speeds involved is
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`entirely irrelevant” is incorrect. Reply, 17. Any proposed modification of a system,
`
`e.g., Wada’s system, in view of another system, e.g., Barrett’s system, that ignores
`
`the details of each system oversimplifies the issues and is destined to fail. Indeed,
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`AMD oversimplifies the issues of combining Wada with Barrett by alleging that
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`“such uninterruptible bursts are achieved in Wada simply by not prematurely
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`holding the ADV signal low or stopping the clock.” Id. AMD appears to base these
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`proposed modifications on the fact that Wada does not expressly state (1) that the
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`ADV should transition to the Low state during a burst and (2) that a user cannot stop
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`the clock. See id., (“Wada nowhere teaches that a user should prematurely hold
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`ADV low before a burst is complete or ever stop the clock.”)
`
`A POSITA would not have been motivated to modify Wada as AMD suggests.
`
`First, AMD proposes to force the signal ADV to a high state during the duration of
`
`the burst output. But AMD does not explain how this would be accomplished. A
`
`POSITA would have understood that a control circuit would receive one or more
`
`inputs and would calculate the proper value for the ADV signal, e.g., the proper state
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`for ADV, i.e., whether high or low, based on control logic that allows controlling
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`whether a burst output will be interrupted or not. AMD does not explain why a
`
`POSITA would have been motivated to modify Wada in a way that relinquishes
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`control of the burst output. AMD’s proposal essentially forces Wada’s system to
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`ignore messages from the consumer device about, for example, potential overflows
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`downstream from Wada. AMD further fails to explain how Wada’s control circuit
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`would have been modified, e.g., through a hardware or software modification, to
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`accommodate the revised control circuit that generates a different ADV signal based
`
`on the same inputs.
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`Instead, AMD ignores the complication of changing the control circuitry that
`
`sets or resets the ADV signal and also ignores the consequences of its proposed
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`modification, e.g., how to handle overflows of data when the burst output produces
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`more data than can be consumed by the receiving device.
`
`Second, AMD proposes to implement uninterrupted bursts in Wada by
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`stopping the clock. AMD’s proposal cannot be taken seriously. Stopping the clock
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`would pause operation of Wada’s system, because synchronous (i.e., clocked)
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`systems need a clock to operate. Regardless, a POSITA would have understood that
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`stopping the clock would not result in an uninterruptible burst output, because
`
`without a clock, there would be no burst output to interrupt.
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`B. Wada and Barrett Defeat Each Other’s Goals
`
`AMD allegation that Wada and Barret do not defeat each other’s goals is
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`incorrect. Reply, 18. Wada is directed to eliminating pauses in between bursts for
`
`a single semiconductor memory—not preventing interruptions of any individual
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`burst operation. See e.g., Ex-1005, 5:53, 6:56-61. Ex-2004, ¶175. In short, Wada
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`focuses on interruptions between bursts of data—not the burst itself.
`
`Barrett, on the other hand, is explicitly directed towards ensuring pauses in
`
`between burst data transfers between I/O devices within a computing system—
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`precisely the opposite of Wada’s goal. See, e.g., Ex-1010, Abstract, 3:12-22; Ex-
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`2004, ¶175. Therefore, Barrett is focused on the requirement to have interruptions
`
`within its burst.
`
`V.
`
`Secondary Indicia Of Non-Obviousness Demonstrate That The
`Challenged Claims Are Not Obvious Over Wada, Alone Or In
`Combination With The Secondary References
`A. The Claimed Invention Of The ’134 Patent Solves A Long-Felt
`Need.
`
`AMD mischaracterizes the long-felt need identified in Monterey’s Response
`
`and provides an alleged “solution” to the long-felt need that was considered during
`
`prosecution and rejected by the Examiner.
`
`Monterey’s Response explained that “[t]he claimed invention of the ’134
`
`Patent solves a long-felt need, specifically the need to improve read/write rates and
`
`efficiency of DRAMs.” POR, 64. As processor speeds increase, memory read and
`
`write rates need to improve and become more efficient, so they do not present a
`
`bottleneck to the entire computer system’s performance. Dr. Brogioli further
`
`explained that “[t]he benefits realized by the patented invention, discussed above,
`
`filled a long-felt but unmet need for providing fixed, non-interruptible burst accesses
`
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`of memories, including DRAM and SDRAM.” Ex-2004, ¶219. It is the “fixed, non-
`
`interruptible burst accesses of memories” that improve the read/write rates and the
`
`efficiency of memories.
`
`AMD misrepresents the long-felt need and characterizes it in an overly narrow
`
`manner. See Reply, 21. (“At best, the ‘need’ Monterey articulates is the need to hide
`
`DRAM refresh cycles behind burst operations, which is a problem that had already
`
`been solved by Reeves, as discussed above.”) According to AMD, AMD’s alleged
`
`“solution,” e.g., hiding DRAM refresh cycles, had been disclosed by Reeves. As
`
`Dr. Brogioli explains, however, “Reeves seeks to provide an ‘improved transfer
`
`technique’ for ‘ensur[ing] data transfers are not broken whenever a portion of the
`
`SDRAM system is being pre-charged or refreshed. … Particularly, Reeves provides
`
`an SDRAM partition while data is read from a second partition.” Ex-2004, ¶99
`
`(internal citations omitted.) Dr. Brogioli also recognized that “including multiple
`
`partitions ensures that ‘[d]uring the time in which one partition is being read (i.e.,
`
`data being transferred therefrom), another partition may undergo a refresh or pre-
`
`charge operation.’ According to Reeves, this prevents ‘non-data transfers
`
`occurring between data burst cycles.’” Id. AMD does not dispute this. Therefore,
`
`Reeves does not disclose the non-interruptible bursts claimed by the ’134 Patent.
`
`In any event, as discussed in Section Error! Reference source not found.,
`
`AMD’s alleged “solution” to the long-felt need (Reeves) is the same one presented
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`during the prosecution of the ’134 Patent by Cowles, over which the ’134 Patent
`
`issued.. But this solution does not address the ’134 Patent’s solution to the issue,
`
`which doesn’t need to partition the DRAM in order to achieve non-interruptible
`
`bursts. The ’134 Patent meets a long felt need by providing uninterrupted bursts—
`
`which also addresses the refresh problem for DRAM—without requiring partitions.
`
`B. A Nexus Exists Between The Claimed Invention Of The ’134 Patent
`And Non-Interruptible DDR SDRAM Technology.
`
`Both of AMD’s arguments concerning nexus fail. First, AMD alleges that
`
`“the ’134 Patent claims are written broadly to encompass SRAM.” Reply, 24. But
`
`as discussed in Section Error! Reference source not found., the “non-interruptible
`
`bursts” for the ’134 Patent apply to SRAM memories as well as DRAM memories
`
`because “the burst mode of a conventional synchronous SRAM memories can be
`
`started and stopped in response to a control signal.” (Ex-1001, 1:16-18.) And even
`
`if SRAM memories do not suffer from the need to refresh its contents, SRAM
`
`memories can still benefit from uninterrupted bursts as taught in the ’134 Patent.
`
`For example, bursts create uncertainties to the exact timing of a data transfer. SRAM
`
`memories can benefit from uninterrupted bursts because they offer determinism in
`
`the data transfers and remove any speculation about when all the data will be
`
`transferred.
`
`Second, AMD argues that “Monterey then goes on to map the JEDEC DDR3
`
`specification to claims 1, 16, and 17 of the ’134 Patent” (Reply, 25) but “for multiple
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`claim elements in its mapping, Monterey relies upon disclosures in a figure from the
`
`DDR specification (Ex-2010) that do not appear in the DDR3 specification.” Id.
`
`AMD’s argument is a red herring. The figure from the DDR Specification—
`
`Figure 3, illustrated below— is a general figure showing DDR devices, which of
`
`course discloses the limitations.
`
`Indeed a virtually identical figure is provided by Dr. Baker Baker’s DRAM Circuit
`
`Design book (Ex-2007, Fig. 1.18), generally describing SDRAM blocks. Therefore,
`
`a figure from the DDR Specification can illustrate aspects of memory systems that
`
`are not compliant only to the DDR Specification, but are common across different
`
`
`
`versions, e.g., DDR2 or DDR3.
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`U.S. Patent No. 6,651,134
`In addition, the DDR3 Specification was created based on the DDR2 and DDR
`
`specifications so the block diagram of the DDR specification also applies to DDR3.
`
`See Ex-2014, 15 (“This document defines the DDR3 SDRAM specification … This
`
`specification was created based on the DDR2 specification (JESD79-2) and some
`
`aspects of the DDR specification (JESD79).”)
`
`VI. Conclusion
`
`For the foregoing reasons, AMD has failed to carry its burden of proving that
`
`the challenged claims are anticipated or obvious. Accordingly, Monterey
`
`respectfully requests a final written decision affirming the patentability of each of
`
`the challenged claims.
`
`
`
`Dated: July 7, 2021
`
`Respectfully submitted,
`
`/Theodoros Konstantakopoulos/
`Theodoros Konstantakopoulos (Reg.
`No. 74,155)
`tkonstantakopoulos@desmaraisllp.com
`DESMARAIS LLP
`230 Park Avenue
`New York, NY 10169
`Telephone: 212-351-3400
`Facsimile: 212-351-3401
`
`Lead Counsel for Patent Owner
`Monterey Research, LLC
`
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`CERTIFICATION UNDER 37 C.F.R. § 42.24(d)
`
`
`I hereby certify that this paper, excluding the portions exempted under 37
`C.F.R. § 42.24(a), has 3,854 words as counted by Microsoft Word 2016, the word-
`processing system used to prepare this paper.
`
`
`
`Dated: July