JEDEC
`STANDARD
`
`GRAPHICS DOUBLE DATA RATE
`(GDDR5) SGRAM STANDARD
`
`Des m arais LLP
`
`JESD212C
`(Revision of JESD212B.01, December 2013)
`
`FEBRUARY 2016
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Oct 19, 2020, 1:20 pm PDT
`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0001
`
`

`

`NOTICE
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`The information included in JEDEC standards and publications represents a sound approach to
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`Des m arais LLP
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`PLEASE!
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`DON'T VIOLATE
`THE
`LAW!
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`This document is copyrighted by the JEDEC Solid State Technology Association
`and may not be reproduced without permission.
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`
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`Arlington, Virginia 22201
`or call (703) 907-7559
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`Des m arais LLP
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`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Oct 19, 2020, 1:20 pm PDT
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`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0004
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`

`

`JEDEC Standard No. 212C
`
`Contents
`
`1 SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
`
`2 GDDR5 SGRAM SPECIFICATION OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
`2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
`2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
`2.3 Definition of Signal State Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
`2.4 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
`
`3 INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
`3.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
`3.2 Initialization with Stable Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
`3.3 Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
`
`4 ADDRESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
`4.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
`4.2 Address Bus Inversion (ABI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`4.3 Bank Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`
`5 TRAINING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
`5.1 Interface Training Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
`5.2 Address Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`5.3 WCK2CK Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`5.4 READ Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`5.5 WRITE Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`
`6 MODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
`6.1 Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`6.2 Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
`6.3 Mode Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`6.4 Mode Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
`6.5 Mode Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
`6.6 Mode Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
`6.7 Mode Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`6.8 Mode Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`6.9 Mode Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`6.10 Mode Register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`6.11 Mode Register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
`
`Des m arais LLP
`
`7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
`7.1 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
`7.2 Deselect (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`7.3 No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`7.4 Mode Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`7.5 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`7.6 Bank Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`7.7 Write (WOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`7.8 Write Data Mask (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`7.9 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
`7.10 DQ Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`7.11 Read and Write Data Bus Inversion (DBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`7.12 Error Detection Code (EDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
`7.13 Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
`7.14 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
`7.15 Refresh and Per-Bank Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
`7.16 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
`7.17 Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
`7.18 Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
`7.19 Command Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
`7.20 Low Frequency Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
`7.21 RDQS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
`
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`
`

`

`JEDEC Standard No. 212C
`
`7.22 Clock Frequency Change Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
`7.23 Dynamic Voltage Switching (DVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
`7.24 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
`7.25 Duty Cycle Connector (DCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
`
`8 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
`8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
`8.2 AC & DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
`8.3 Clock-To-Data Timing Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
`8.4 1.5V I/O Driver Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
`8.5 1.35V I/O Driver Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
`8.6 POD I/O System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
`
`9 PACKAGE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
`9.1 Ball-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
`9.2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
`9.3 On Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
`9.4 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
`9.5 Mirror Function (MF) Enable and x16 Mode Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
`
`10 BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
`
`Annex A (informative) Differences between JESD212C and JESD212B.01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
`
`Des m arais LLP
`
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`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Oct 19, 2020, 1:20 pm PDT
`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0006
`
`

`

`JEDEC Standard No. 212C
`Page 1
`
`GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD
`
`(From JEDEC Board Ballot JCB-16-53, formulated under the cognizance of the JC-42.3 Subcommittee on
`DRAM Memories.)
`
`1
`
`SCOPE
`
`This document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access
`Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope
`may be expanded in future to also include other higher density devices.
`The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible
`512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this
`standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices.
`Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized.
`Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should
`be consulted for specifics.
`This standard was created based on the DDR Standard (JESD79) and some aspects of the GDDR4 Standard
`(JESD21C - 3.11.5.8). Each aspect of the changes for high speed operation were considered and balloted. The
`accumulation of these ballots were then incorporated to prepare this GDDR5 SGRAM document, replacing
`whole sections and incorporating the changes into Functional Description and Operation.
`
`Des m arais LLP
`
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`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0007
`
`

`

`JEDEC Standard No. 212C
`Page 2
`
`2
`
`GDDR5 SGRAM STANDARD OVERVIEW
`
`512 Mb = 16 Mb x 32
`1 Gb
`= 32 Mb x 32
`2 Gb
`= 64 Mb x 32
`4 Gb
`= 128 Mb x 32
`8 Gb
`= 256 Mb x 32
`
`(2 Mb x 32 x 8 banks)
`(2 Mb x 32 x 16 banks)
`(4 Mb x 32 x 16 banks)
`(8 Mb x 32 x 16 banks)
`(16 Mb x 32 x 16 banks)
`
`/ 32 Mb x 16
`/ 64 Mb x 16
`/ 128 Mb x 16
`/ 256 Mb x 16
`/ 512 Mb x 16
`
`(4 Mb x 16 x 8 banks)
`(4 Mb x 16 x 16 banks)
`(8 Mb x 16 x 16 banks)
`(16 Mb x 16 x 16 banks)
`(32 Mb x 16 x 16 banks)
`
`Des m arais LLP
`
` FEATURES
`2.1
`• Single ended interface for data, address and command
`• Quarter data-rate differential clock inputs CK_t/CK_c for ADD/CMD
`• Two half data-rate differential clock inputs WCK_t/WCK_c, each associated with two data bytes (DQ, DBI_n, EDC)
`• Double Data Rate (DDR) data (WCK)
`• Single Data Rate (SDR) command (CK)
`• Double Data Rate (DDR) addressing (CK)
`• 8 or 16 internal banks
`• 4 bank groups for tCCDL = 3 tCK and 4 tCK
`• 8n prefetch architecture: 128/256 bit per array read or write access
`• Burst length: 8 only
`• Programmable CAS latency: 5 to 36 tCK
`• Programmable WRITE latency: 1 to 7 tCK
`• WRITE Data mask function via address bus (single/double byte mask)
`• Data bus inversion (DBI) & address bus inversion (ABI)
`• Input/output PLL/DLL on/off mode
`• Address training: address input monitoring by DQ pins
`• WCK2CK clock training with phase information by EDC pins
`• Data read and write training via READ FIFO
`• READ FIFO pattern preload by LDFF command
`• Direct write data load to READ FIFO by WRTR command
`• Consecutive read of READ FIFO by RDTR command
`• Read/Write data transmission integrity secured by cyclic redundancy check (CRC-8)
`• READ/WRITE EDC on/off mode
`• Programmable EDC hold pattern for CDR
`• Programmable CRC READ latency = 0 to 4 tCK
`• Programmable CRC WRITE latency = 7 to 14 tCK
`• Low Power modes
`• RDQS mode on EDC pin
`• Optional on-chip temperature sensor with read-out
`• Auto & self refresh modes
`• Auto precharge option for each burst access
`• 32ms, auto refresh (8k/16k cycles)
`• Temperature sensor controlled self refresh rate
`• Optional Partial Array Self Refresh (PASR)
`• Optional Per-Bank Refresh (REFPB)
`• Optional digital tRAS lockout
`• On-die termination (ODT); nominal values of 60 ohm and 120 ohm
`• Pseudo open drain (POD-15 or POD-135) compatible outputs (40 ohm pulldown, 60 ohm pullup)
`• ODT and output drive strength auto-calibration with external resistor ZQ pin (120 ohm)
`• Programmable termination and driver strength offsets
`• Selectable external or internal VREF for data inputs; programmable offsets for internal VREF
`• Separate external VREF for address / command inputs
`• Vendor ID, FIFO depth and Density info fields for identification
`• x32/x16 mode configuration set at power-up with EDC pin
`• Mirror function with MF pin
`• Boundary scan function with SEN pin
`• 1.5V +/- 0.045V or 1.35V +/- 0.0405V supply for device operation (VDD)
`• 1.5V +/- 0.045V or 1.35V +/- 0.0405V supply for I/O interface (VDDQ)
`• 170 ball BGA package
`
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`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0008
`
`

`

`JEDEC Standard No. 212C
`Page 3
`
` FUNCTIONAL DESCRIPTION
`2.2
`The GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring
`high bandwidth. GDDR5 devices contain the following number of bits:
`
`512 Mb has 536,870,912 bits and eight banks
`1 Gb has 1,073,741,824 bits and sixteen banks
`2 Gb has 2,147,483,648 bits and sixteen banks
`4 Gb has 4,294,967,296 bits and sixteen banks
`8 Gb has 8,589,934,592 bits and sixteen banks
`
`The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. The
`device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during
`device initialization. The GDDR5 interface transfers two 32 bit wide data words per WCK clock cycle to/
`from the I/O pins. Corresponding to the 8n-prefetch a single write or read access consists of a 256 bit wide,
`two CK clock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one-half
`WCK clock cycle data transfers at the I/O pins.
`The device operates from a differential clock CK_t and CK_c. Commands are registered at every rising edge
`of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.
`GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free
`running differential forwarded clock (WCK_t/WCK_c) with both input and output data registered and
`driven respectively at both edges of the forwarded WCK.
`Read and write accesses to the device are burst oriented; an access starts at a selected location and consists of
`a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then
`followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE
`command and the next rising CK_c edge are used to select the bank and the row to be accessed. The address
`bits registered coincident with the READ or WRITE command and the next rising CK_c edge are used to
`select the bank and the column location for the burst access.
`This specification includes all features and functionality required for JEDEC GDDR5 SGRAM devices. Users
`benefit from knowing that any system design based on the required aspects of the specification are
`supported by all GDDR5 SGRAM vendors; conversely users seeking to use any superset specifications bear
`the responsibility to verify support with individual vendors.
`
`Des m arais LLP
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Oct 19, 2020, 1:20 pm PDT
`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0009
`
`

`

`JEDEC Standard No. 212C
`Page 4
`
` DEFINITION OF SIGNAL STATE TERMINOLOGY
`2.3
`The device will be operated in both ODT Enable (terminated) and ODT Disable (unterminated) modes. For
`highest data rates it is recommended to operate in the ODT Enable mode. ODT Disable mode is designed to
`reduce power and may operate at reduced data rates. There exist situations where ODT Enable mode can
`not be guaranteed for a short period of time, i.e., during power up.
`Following are four terminologies defined for the state of a device (GDDR5 SGRAM or controller) pin during
`operation. The state of the bus will be determined by the combination of the device pins connected to the
`bus in the system. For example in GDDR5 it is possible for the SGRAM pin to be tristated while the
`controller pin is High or ODT. In both cases the bus would be High if the ODT is enabled. For details on the
`GDDR5 SGRAM pins and their function see Sections 9.1 and 9.2.
`
`Device pin signal level:
`• High: A device pin is driving the Logic “1” state.
`• Low: A device pin is driving the Logic “0” state.
`• Hi-Z: A device pin is tristate.
`• ODT: A device pin terminates with ODT setting, which could be terminating or tristate depending on Mode
`Register setting.
`
`Bus signal level:
`• High: One device on bus is High and all other devices on bus are either ODT or Hi-Z. The voltage level on the bus
`would be nominally VDDQ
`• Low: One device on bus is Low and all other devices on bus are either ODT or Hi-Z. The voltage level on the bus
`would be nominally VOL(DC) if ODT was enabled, or VSSQ if Hi-Z.
`• Hi-Z: All devices on bus are Hi-Z. The voltage level on bus is undefined as the bus is floating.
`• ODT: At least one device on bus is ODT and all others are Hi-Z. The voltage level on the bus would be nominally
`VDDQ.
`
`Des m arais LLP
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`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0010
`
`

`

`JEDEC Standard No. 212C
`Page 5
`
` CLOCKING
`2.4
`The device operates from a differential clock CK_t and CK_c. Commands are registered at every rising edge
`of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.
`GDDR5 uses a DDR data interface and an 8n-prefetch architecture. The data interface uses two differential
`forwarded clocks (WCK_t/WCK_c). DDR means that the data is registered at every rising edge of WCK_t
`and rising edge of WCK_c. WCK_t and WCK_c are continuously running and operate at twice the frequency
`of the command/address clock (CK_t/CK_c).
`
`CK_c
`CK_t
`
`COMMAND
`
`ADDRESS
`
`WCK_c
`WCK_t
`
`DQ*1
`
`Figure 1 — GDDR5 Clocking and Interface Relationship
`NOTE Figure 1 shows the relationship between the data rate of the buses and the clocks and is not a timing diagram.
`
`Controller
`
`ADD/CMD centered with CK_t/CK_c
`
`CMD/ADD
`
`QD
`
`GDDR5 SGRAM
`
`CMD sampled by CK_t/CK_c as SDR
`ADD sampled by CK_t/CK_c as DDR
`
`CMD/ADD
`
`QD
`QB
`
`CK_t/CK_c
`(1 GHz)
`
`Des m arais LLP
`
`DRAM
`core
`
`WCK2CK
`Alignment
`
`D Q
`
`PLL optional
`
`/2
`
`To EDC pin
`
`WCKint
`(1 GHz)
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`DQ
`
`QD
`
`DRAM
`core
`
`Oscillator
`
`PLL/DLL
`Data Tx/Rx
`
`WCK_t/
`WCK_c
`(2 GHz)
`
`DQ [0]-[7]
`(4 Gbps)
`
`early/late
`
`Clock Phase
`Controller
`
`Phase detector/
`Phase accumulator
`
`corelogic
`
`DQ
`
`Receiver
`clock
`
`early/late from
`calibration data
`
`DQ
`
`D Q
`
`Clock Phase
`Controller
`
`For 8 data bits
`Figure 2 — Block Diagram of an example clock system
`
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`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0011
`
`

`

`JEDEC Standard No. 212C
`Page 6
`
`3
`
`INITIALIZATION
`
` POWER-UP SEQUENCE
`3.1
`GDDR5 SGRAMs must be powered up and initialized in a predefined manner as shown in Figure 3.
`Operational procedures other than those specified may result in undefined operation. The Mode Registers
`do not have RESET default values, except for ABI_n, ADD/CMD termination, and the EDC hold pattern. If
`the mode registers are not set during the initialization sequence, it may lead to unspecified operation.
`
`Apply power to VDD
`
`Apply power to VDDQ at same time or after power is applied to VDD
`
`Apply VREFC and VREFD at same time or after power is applied to VDDQ
`
`After power is stable, provide stable clock signals CK_t/CK_c
`
`Assert and hold RESET_n low to ensure all drivers are in Hi-Z and all active terminations are off. Assert and hold NOP
`command.
`
`6 Wait a minimum of 200µs.
`
`If boundary scan mode is necessary, SEN can be asserted HIGH to enter boundary scan mode. Boundary scan mode must be
`entered directly after power-up while RESET_n is low. Once boundary scan is executed, power-up sequence should be
`followed.
`
`Set CKE_n for the desired ADD/CMD ODT settings, then bring RESET_n High to latch in the logic state of CKE_n, tATS and
`tATH must be met during this procedure. See Table 1 for the values and logic states for CKE_n. The rising edge of RESET_n
`will determine x32 mode or x16 mode depending on the state of EDC1(EDC2 when MF=1). In normal x32 mode, EDC1 has to
`be sustained HIGH until RESET_n is HIGH. See Table 70 for the values and logic states for EDC1(EDC2 when MF=1).
`
`Bring CKE_n Low after tATH is satisfied
`
`Step
`
`1
`
`2
`
`3
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`4
`
`5
`
`7
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`8
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`9
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`11
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`12
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`13
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`Des m arais LLP
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`10 Wait at least 200µs referenced from the beginning of tATS
`
`Issue at least 2 NOP commands
`
`Issue a PRECHARGE ALL command followed by NOP commands until tRP is satisfied
`
`Issue MRS command to MR15. Set the device into address training mode (optional)
`
`14 Complete address training (optional)
`
`15
`
`16
`
`17
`
`18
`
`19
`
`Issue MRS command to read the Vendor ID
`
`Issue MRS command to set WCK01_t/WCK01_c and WCK23_t/WCK23_c termination values
`
`Provide stable clock signals WCK01_t/WCK01_c and WCK23_t/WCK23_c
`
`Issue MRS commands to the mode registers in any order. Issue MRS commands to use PLL/DLL or not and select the position
`of a WCK/CK phase detector. The use of PLL/DLL and the position of a phase detector must be set before WCK2CK training.
`tMRD must be met during +this procedure. WLmrs, CLmrs, CRCWL and CRCRL must be programmed before WCK2CK
`training.
`
`Issue two REFRESH commands followed by NOP until tRFC is satisfied. GDDR5 SGRAMs may optionally require 500 us
`before the first REFRESH command may be issued. Vendor datasheets should be consulted for specifics.
`
`20 After any necessary GDDR5 training sequences such as WCK2CK training, READ training (LDFF, RDTR) and WRITE training
`(WRTR, RDTR), the device is ready for operation.
`
`Figure 3 — GDDR5 Power-up Sequence
`
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`
`Patent Owner Monterey Research, LLC
`Exhibit 2016, 0012
`
`

`

`JEDEC Standard No. 212C
`Page 7
`
`3.1
`
`POWER-UP SEQUENCE (cont’d)
`Table 1 — Address and Command Termination
`
`CKE_n at RESET_n high transition
`
`Low
`
`High
`
`VALUE (OHMS)
`
`ZQ/2 = 60 Ohms
`
`ZQ = 120 Ohms
`
`VDD
`
`VDDQ
`
`VREFD/C
`
`RESET_n
`
`CKE_n
`
`CK_c
`CK_t
`
`CMD
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`DQ<31:0>,
`DBI<3:0>_n
`
`EDC<3,0>
`
`EDC<2,1>
`
`WCK_c
`WCK_t
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