JEDEC
`STANDARD
`
`DDR3 SDRAM SWDQGDUG
`
`JESD79-3)
`(Revision of JESD79-3(, -XO\ 20)
`
`J8/< 201
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0001
`
`

`

`NOTICE
`JEDEC standards and publications contain material that has been prepared, reviewed, and
`approved through the JEDEC Board of Directors level and subsequently reviewed and approved
`by the JEDEC legal counsel.
`
`JEDEC standards and publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchasers, facilitating interchangeability and
`improvement of products, and assisting the purchaser in selecting and obtaining with minimum
`delay the proper product for use by those other than JEDEC members, whether the standard is to
`be used either domestically or internationally.
`
`JEDEC standards and publications are adopted without regard to whether or not their adoption
`may involve patents or articles, materials, or processes. By such action JEDEC does not assume
`any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
`the JEDEC standards or publications.
`
`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer
`viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
`publication may be further processed and ultimately become an ANSI standard.
`
`No claims to be in conformance with this standard may be made unless all requirements stated in
`the standard are met.
`
`Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
`publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or
`www.jedec.org
`
`Published by
`©JEDEC Solid State Technology Association 201
`3103 North 10th Street, Suite 240 South
`Arlington, VA 22201
`
`This document may be downloaded free of charge; however JEDEC retains the copyright on this
`material. By downloading this file the individual agrees not to charge for or resell the resulting
`material.
`
`PRICE: Please refer to the current
`Catalog of JEDEC Engineering Standards and Publications online at
`http://www.jedec.org/Catalog/catalog.cfm
`Printed in the U.S.A.
`All rights reserved
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0002
`
`

`

`PLEASE!
`
`DON'T VIOLATE THE LAW!
`
`This document is copyrighted by JEDEC and may not be
`reproduced without permission.
`
`Organizations may obtain permission to reproduce a limited number of copies
`through entering into a license agreement. For information, contact:
`
`JEDEC Solid State Technology Association
`3103 North 10th Street, Suite 240 South
`Arlington, Virginia 22201
`or call (703) 907-7559
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0003
`
`

`

`This page left blank.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0004
`
`

`

`JEDEC Standard No. 79-3F
`
`Contents
`
`1 Scope..........................................................................................................................................1
`2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
`2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
`2.11.1 512Mb ....................................................................................................................15
`2.11.2 1Gb..........................................................................................................................15
`2.11.3 2Gb .........................................................................................................................15
`2.11.4 4Gb .........................................................................................................................15
`2.11.5 8Gb .........................................................................................................................16
`3 Functional Description.............................................................................................................17
`3.1 Simplified State Diagram.................................................................................................17
`3.3.1 Power-up Initialization Sequence .............................................................................19
`3.3.2 Reset Initialization with Stable Power......................................................................21
`3.4.1 Programming the Mode Registers ............................................................................22
`3.4.2 Mode Register MR0..................................................................................................23
`3.4.3 Mode Register MR1..................................................................................................27
`3.4.4 Mode Register MR2..................................................................................................30
`3.4.5 Mode Register MR3..................................................................................................32
`4 DDR3 SDRAM Command Description and Operation...........................................................33
`4.1 Command Truth Table.....................................................................................................33
`4.3 No OPeration (NOP) Command ......................................................................................36
`4.4 Deselect Command ..........................................................................................................36
`4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
`4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
`4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
`4.8.2 Procedure Description...............................................................................................43
`4.8.3 Write Leveling Mode Exit ........................................................................................45
`4.9.1 Self-Refresh Temperature Range - SRT...................................................................46
`4.10.1 MPR Functional Description ..................................................................................49
`4.10.2 MPR Register Address Definition ..........................................................................50
`4.10.3 Relevant Timing Parameters...................................................................................50
`4.10.4 Protocol Example....................................................................................................50
`4.12 PRECHARGE Command ..............................................................................................55
`4.13.1 READ Burst Operation...........................................................................................56
`4.13.3 Burst Read Operation followed by a Precharge......................................................66
`4.14.1 DDR3 Burst Operation ...........................................................................................68
`4.14.2 WRITE Timing Violations .....................................................................................68
`4.14.3 Write Data Mask.....................................................................................................69
`4.14.4 tWPRE Calculation.................................................................................................70
`4.14.5 tWPST Calculation .................................................................................................70
`4.17.1 Power-Down Entry and Exit...................................................................................81
`4.17.2 Power-Down clarifications - Case 1 .......................................................................86
`4.17.3 Power-Down clarifications - Case 2 .......................................................................87
`5 On-Die Termination (ODT).....................................................................................................89
`5.1 ODT Mode Register and ODT Truth Table.....................................................................89
`
`i
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0005
`
`

`

`JEDEC Standard No. 79-3F
`
`Contents
`
`5.2 Synchronous ODT Mode .................................................................................................90
`5.2.1 ODT Latency and Posted ODT.................................................................................90
`5.2.2 Timing Parameters....................................................................................................90
`5.2.3 ODT during Reads ....................................................................................................92
`5.3.1 Functional Description:.............................................................................................94
`5.3.2 ODT Timing Diagrams.............................................................................................95
`5.4.1 Synchronous to Asynchronous ODT Mode Transitions.........................................101
`5.4.2 Synchronous to Asynchronous ODT Mode Transition during
`Power-Down Entry .................................................................................................101
`5.4.3 Asynchronous to Synchronous ODT Mode Transition during
`Power-Down Exit ...................................................................................................104
`5.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short
`CKE low periods.....................................................................................................105
`5.5.1 ZQ Calibration Description.....................................................................................107
`5.5.2 ZQ Calibration Timing ...........................................................................................108
`5.5.3 ZQ External Resistor Value, Tolerance, and Capacitive loading ...........................108
`6 Absolute Maximum Ratings ..................................................................................................109
`6.1 Absolute Maximum DC Ratings....................................................................................109
`6.2 DRAM Component Operating Temperature Range ......................................................109
`7 AC & DC Operating Conditions............................................................................................111
`7.1 Recommended DC Operating Conditions......................................................................111
`8 AC and DC Input Measurement Levels.................................................................................113
`8.1 AC and DC Logic Input Levels for Single-Ended Signals ............................................113
`8.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals.........113
`8.3 AC and DC Logic Input Levels for Differential Signals ...............................................116
`8.3.1 Differential signal definition...................................................................................116
`8.3.2 Differential swing requirements for clock (CK - CK#) and strobe
`(DQS - DQS#) ........................................................................................................116
`8.3.3 Single-ended requirements for differential signals.................................................117
`8.4 Differential Input Cross Point Voltage ..........................................................................118
`8.6 Slew Rate Definitions for Differential Input Signals.....................................................120
`9 AC and DC Output Measurement Levels ..............................................................................121
`9.1 Single Ended AC and DC Output Levels.......................................................................121
`9.2 Differential AC and DC Output Levels .........................................................................121
`9.6.1 Address and Control Overshoot and Undershoot Specifications............................125
`9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications.............126
`9.7.1 Output Driver Temperature and Voltage sensitivity...............................................128
`9.8.1 On-Die Termination (ODT) Levels and I-V Characteristics ..................................130
`9.8.2 ODT DC Electrical Characteristics.........................................................................131
`9.8.3 ODT Temperature and Voltage sensitivity.............................................................134
`9.9 ODT Timing Definitions................................................................................................134
`9.9.1 Test Load for ODT Timings ...................................................................................134
`9.9.2 ODT Timing Definitions.........................................................................................135
`10 IDD and IDDQ Specification Parameters and Test Conditions...........................................139
`
`ii
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0006
`
`

`

`JEDEC Standard No. 79-3F
`
`Contents
`
`10.1 IDD and IDDQ Measurement Conditions ...................................................................139
`11 Input/Output Capacitance ....................................................................................................153
`11.1 Input/Output Capacitance ............................................................................................153
`12 .............................................................................................................................................155
`12.1 Clock Specification......................................................................................................155
`12.1.1 Definition for tCK(avg) ........................................................................................155
`12.1.2 Definition for tCK(abs).........................................................................................155
`12.1.3 Definition for tCH(avg) and tCL(avg)..................................................................155
`12.1.4 Definition for tJIT(per) and tJIT(per,lck) .............................................................156
`12.1.5 Definition for tJIT(cc) and tJIT(cc,lck) ................................................................156
`12.1.6 Definition for tERR(nper).....................................................................................156
`12.2 Refresh parameters by device density..........................................................................156
`13 Electrical Characteristics and AC Timing ...........................................................................167
`13.1 Timing Parameters for DDR3-800, DDR3-1067, DDR3-1333, and DDR3-1600.......167
`13.6.1 Data Setup, Hold and Slew Rate Derating of DDR3-1866/2133..........................190
`
`iii
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0007
`
`

`

`JEDEC Standard No. 79-3F
`
`List of Figures
`
`Figure 1 —Qual-stacked / Quad-die DDR3 SDRAM x4 rank association . . . . . . . . . . . . . . . . . 12
`Figure 2 —Qual-stacked / Quad-die DDR3 SDRAM x8 rank association . . . . . . . . . . . . . . . . . 12
`Figure 3 —Qual-stacked / Quad-die DDR3 SDRAM x16 rank association . . . . . . . . . . . . . . . . 12
`Figure 4 —Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`Figure 5 —Reset and Initialization Sequence at Power-on Ramping . . . . . . . . . . . . . . . . . . . . . 20
`Figure 6 —Reset Procedure at Power Stable Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
`Figure 7 —tMRD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
`Figure 8 —tMOD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
`Figure 9 —MR0 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
`Figure 10 —MR1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`Figure 11 —MR2 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`Figure 12 —MR3 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Figure 13 —DLL-off mode READ Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
`Figure 14 — DLL Switch Sequence from DLL-on to DLL-off . . . . . . . . . . . . . . . . . . . . . . . . . 38
`Figure 15 —DLL Switch Sequence from DLL Off to DLL On . . . . . . . . . . . . . . . . . . . . . . . . . 39
`Figure 16 —Change Frequency during Precharge Power-down . . . . . . . . . . . . . . . . . . . . . . . . . 41
`Figure 17 —Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
`Figure 18 —Timing details of Write leveling sequence [DQS - DQS# is capturing
`CK - CK# low at T1 and CK - CK# high at T2 . . . . . . . . . . . . . . . . . . . . . . . . . . 44
`Figure 19 —Timing details of Write leveling exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
`Figure 20 —MPR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
`Figure 21 —MPR Readout of predefined pattern, BL8 fixed burst order, single readout . . . . . 51
`Figure 22 —MPR Readout of predefined pattern, BL8 fixed burst order,
`back-to-back readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`Figure 23 —MPR Readout predefined pattern, BC4, lower nibble then upper nibble . . . . . . . . 53
`Figure 24 —MPR Readout of predefined pattern, BC4, upper nibble then lower nibble . . . . . . 54
`Figure 25 —READ Burst Operation RL = 5 (AL = 0, CL = 5, BL8) . . . . . . . . . . . . . . . . . . . . . 56
`Figure 26 —READ Burst Operation RL = 9 (AL = 4, CL = 5, BL8) . . . . . . . . . . . . . . . . . . . . . 56
`Figure 27 —READ Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`Figure 28 —Clock to Data Strobe Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Figure 29 —Data Strobe to Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`Figure 30 —tLZ and tHZ method for calculating transitions and endpoints . . . . . . . . . . . . . . . . 60
`Figure 31 —Method for calculating tRPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . . 61
`Figure 32 —Method for calculating tRPST transitions and endpoints . . . . . . . . . . . . . . . . . . . . 61
`Figure 33 —READ (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Figure 34 —Nonconsecutive READ (BL8) to READ (BL8), tCCD=5 . . . . . . . . . . . . . . . . . . . 62
`Figure 35 —READ (BC4) to READ (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Figure 36 —READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Figure 37 —READ (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
`Figure 38 —READ (BL8) to READ (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
`Figure 39 —READ (BC4) to READ (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
`Figure 40 —READ (BC4) to WRITE (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
`Figure 41 —READ (BL8) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`Figure 42 —READ to PRECHARGE, RL = 5, AL = 0, CL = 5, tRTP = 4, tRP = 5 . . . . . . . . . 67
`Figure 43 —READ to PRECHARGE, RL = 8, AL = CL-2, CL = 5, tRTP = 6, tRP = 5 . . . . . . 67
`Figure 44 —Write Timing Definition and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`Figure 45 —Method for calculating tWPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . 70
`
`iv
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0008
`
`

`

`JEDEC Standard No. 79-3F
`
`List of Figures
`
`Figure 46 —Method for calculating tWPST transitions and endpoints . . . . . . . . . . . . . . . . . . . . 70
`Figure 47 —WRITE Burst Operation WL = 5 (AL = 0, CWL = 5, BL8) . . . . . . . . . . . . . . . . . . 71
`Figure 48 —WRITE Burst Operation WL = 9 (AL = CL-1, CWL = 5, BL8) . . . . . . . . . . . . . . 71
`Figure 49 —WRITE (BC4) to READ (BC4) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`Figure 50 —WRITE (BC4) to PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`Figure 51 —WRITE (BC4) OTF to PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`Figure 52 —WRITE (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Figure 53 —WRITE (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Figure 54 —WRITE (BL8) to READ (BC4/BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`Figure 55 —WRITE (BC4) to READ (BC4/BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`Figure 56 —WRITE (BC4) to READ (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`Figure 57 —WRITE (BL8) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`Figure 58 —WRITE (BC4) to WRITE (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Figure 59 —Refresh Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`Figure 60 —Postponing Refresh Commands (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`Figure 61 —Pulling-in Refresh Commands (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`Figure 62 —Self-Refresh Entry/Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
`Figure 63 —Active Power-Down Entry and Exit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 82
`Figure 64 —Power-Down Entry after Read and Read with Auto Precharge . . . . . . . . . . . . . . . 82
`Figure 65 —Power-Down Entry after Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . 83
`Figure 66 —Power-Down Entry after Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`Figure 67 —Precharge Power-Down (Fast Exit Mode) Entry and Exit . . . . . . . . . . . . . . . . . . . 84
`Figure 68 — Precharge Power-Down (Slow Exit Mode) Entry and Exit . . . . . . . . . . . . . . . . . . 84
`Figure 69 — Refresh Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
`Figure 70 — Active Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
`Figure 71 — Precharge / Precharge all Command to Power-Down Entry . . . . . . . . . . . . . . . . . 86
`Figure 72 — MRS Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
`Figure 73 —Power-Down Entry/Exit Clarifications - Case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
`Figure 74 —Power-Down Entry/Exit Clarifications - Case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
`Figure 75 —Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
`Figure 76 —Synchronous ODT Timing Example for AL = 3; CWL = 5;
`ODTLon = AL + CWL - 2 = 6.0; ODTLoff = AL + CWL - 2 = 6 . . . . . . . . . . . 91
`Figure 77 —Synchronous ODT example with BL = 4, WL = 7. . . . . . . . . . . . . . . . . . . . . . . . . 92
`Figure 78 —ODT must be disabled externally during Reads by driving ODT low.
`(example: CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5;
`ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8) . . . . . . . . . . . . 93
`Figure 79 —Dynamic ODT: Behavior with ODT being asserted before and after the write . . . 96
`Figure 80 —Dynamic ODT: Behavior without write command, AL = 0, CWL = 5 . . . . . . . . . 96
`Figure 81 —Dynamic ODT: Behavior with ODT pin being asserted together with write
`command for a duration of 6 clock cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
`Figure 82 —Dynamic ODT: Behavior with ODT pin being asserted together with write
`command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF),
`AL = 0, CWL = 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
`Figure 83 —Dynamic ODT: Behavior with ODT pin being asserted together with write
`command for a duration of 4 clock cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
`Figure 84 —Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition:
`AL is ignored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
`
`v
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0009
`
`

`

`JEDEC Standard No. 79-3F
`
`List of Figures
`
`Figure 85 —Synchronous to asynchronous transition during Precharge Power Down
`(with DLL frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4) . . . . . . . . 102
`Figure 86 —Synchronous to asynchronous transition after Refresh command
`(AL = 0; CWL = 5; tANPD = WL - 1 = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
`Figure 87 —Asynchronous to synchronous transition during Precharge Power Down (with
`DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9) . . . 104
`Figure 88 —Transition period for short CKE cycles, entry and exit period overlapping
`(AL = 0, WL = 5, tANPD = WL - 1 = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
`Figure 89 —ZQ Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
`Figure 90 —Illustration of VRef(DC) tolerance and VRef ac-noise limits . . . . . . . . . . . . . . . . 115
`Figure 91 —Definition of differential ac-swing and “time above ac-level” tDVAC . . . . . . . . 116
`Figure 92 —Single-ended requirement for differential signals. . . . . . . . . . . . . . . . . . . . . . . . . 118
`Figure 93 —Vix Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
`Figure 94 —Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# . . . . . . . . 120
`Figure 95 —Single-ended Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
`Figure 96 —Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
`Figure 97 —Reference Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . 124
`Figure 98 —Address and Control Overshoot and Undershoot Definition . . . . . . . . . . . . . . . . 125
`Figure 99 —Clock, Data, Strobe and Mask Overshoot and Undershoot Definition . . . . . . . . . 126
`Figure 100 —Output Driver: Definition of Voltages and Currents . . . . . . . . . . . . . . . . . . . . . . 127
`Figure 101 —On-Die Termination: Definition of Voltages and Currents . . . . . . . . . . . . . . . . . 130
`Figure 102 —ODT Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
`Figure 103 —Definition of tAON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
`Figure 104 —Definition of tAONPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
`Figure 105 —Definition of tAOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
`Figure 106 —Definition of tAOFPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
`Figure 107 —Definition of tADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
`Figure 108 — Measurement Setup and Test Load for IDD and IDDQ (optional)
`Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
`Figure 109 —Correlation from simulated Channel IO Power to actual Channel IO Power
`supported by IDDQ Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
`Figure 110 —Illustration of nominal slew rate and tVAC for setup time tIS (for ADD/CMD
`with respect to clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
`Figure 111 —Illustration of nominal slew rate for hold time tIH (for ADD/CMD with
`respect to clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
`Figure 112 —Illustration of tangent line for setup time tIS (for ADD/CMD with respect
`to clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
`Figure 113 —Illustration of tangent line for for hold time tIH (for ADD/CMD with respect to
`clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
`Figure 114 —Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with
`respect to strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
`Figure 115 —Illustration of nominal slew rate for hold time tDH (for DQ with respect
`to strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
`Figure 116 —Illustration of tangent line for setup time tDS (for DQ with respect to strobe) . . 197
`Figure 117 —Illustration of tangent line for hold time tDH (for DQ with respect to strobe) . . 198
`
`vi
`
`Patent Owner Monterey Research, LLC
`Exhibit 2014, 0010
`
`

`

`JEDEC Standard No. 79-3F
`
`List of Tables
`
`Table 1 —Input/output functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`Table 2 —State Diagram Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`Table 3 —Burst Type and Burst Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`Table 4 —Additive Latency (AL) Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`Table 5 —TDQS, TDQS# Function Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`Table 6 —Command Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
`Table 7 —CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`Table 8 —MR setting involved in the leveling procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
`Table 9 —DRAM termination function in the leveling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
`Table 10 —Mode Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
`Table 11 —Self-Refresh mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`Table 12 —MPR MR3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
`Table 13 —MPR MR3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
`Table 14 —Power-Down Entry Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
`Table 15 —Termination Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
`Table 16 —Latencies and timing parameters relevant for Dynamic ODT. . . . . . . . . . . . . . . . . . 94
`Table 17 —Timing Diagrams for “Dynamic ODT”. . . . . . . . . . . . . . . . . . . . . . . . .