~·
`
`LCJCAL BUS
`
`PCILocalBus
`Specification
`
`Production Version
`
`Revision 2.1
`
`June 1, 1995
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0001
`
`

`

`lif!!!.91
`
`Revision 2.1
`
`REVISION
`
`REVISION HISTORY
`
`Original issue
`
`1.0
`
`2.0
`
`2.1
`
`DATE
`
`6/22/92
`
`Incorporated connector and expansion board specification 4/30/93
`
`Incorporated clarifications and added 66 MHz chapter
`
`6/1/95
`
`The PCI Special Interest Group disclaims all warranties and liability for the use of this document
`and the information contained herein and assumes no responsibility for any errors that may
`appear in this document, nor does the PCI Special Interest Group make a commitment to update
`the information contained herein.
`
`Contact the PC! Special Interest Group office to obtain the latest revision of the specification.
`
`Questions regarding the PCI specification or membership in the PCI Special Interest Group may
`be forwarded to:
`
`PC! Special Interest Group
`P.O. Box 14070
`Portland, OR 97214
`(800)433-5 I 77 (U.S.)
`(503)797-4207 (International)
`(503)234-6762 (FAX)
`
`Fire Wire is a trademark of Apple Computer, Inc.
`
`Token Ring and VGA are trademarks and PS/2, IBM, Micro Channel, OS/2, and PC AT are registered
`trademarks of 113M Corporation.
`
`Intel386, Intel486, and i486 are trademarks and Pentium is a registered trademark of Intel Corporation.
`
`Windows is a trademark and MS-DOS and Microsoft are registered trademarks of Microsoft Corporation.
`
`Tristate is a registered trademark of National Semiconductor.
`
`NuBus is a trademark of Texas Instruments.
`
`Ethernet is a registered trademark of Xerox Corporation.
`
`All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
`
`Copyright© 1992, 1993, 1995 PCI Special Interest Group
`
`ii
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0002
`
`

`

`Revision 2.1
`
`Contents
`
`Chapter 1 Introduction
`1.1. Specification Contents ........................................................................................................ 1
`
`1.2. Motivation ......................................................................................................................... 1
`
`1.3. PCI Local Bus Applications ............................................................................................... 2
`
`1.4. PCI Local Bus Overview .................................................................................................... 3
`
`1.5. PCI Local Bus Features and Benefits ................................................................................. .4
`
`1.6. Administration ................................................................................................................... 6
`
`Chapter 2 Signal Definition
`2.1. Signal Type Definition ....................................................................................................... 8
`
`2.2. Pin Functional Groups ........................................................................................................ 8
`
`2.2.1. System Pins ........................................................................................................ 8
`
`2.2.2. Address and Data Pins ........................................................................................ 9
`
`2.2.3. Interface Control Pins ....................................................................................... 10
`
`2.2.4. Arbitration Pins (Bus Masters Only) ................................................................. 11
`
`2.2.5. Error Reporting Pins ......................................................................................... 12
`
`2.2.6. Interrupt Pins (Optional) ................................................................................... 13
`
`2.2.7. Cache Support Pins (Optional) .......................................................................... 14
`
`2.2.8. Additional Signals ............................................................................................ 15
`
`2.2.9. 64-Bit Bus Extension Pins (Optional) ............................................................... 16
`
`2.2.10. JT AG/Boundary Scan Pins (Optional) ............................................................. 17
`
`2.3. Sideband Signals .............................................................................................................. 18
`
`2.4. Central Resource Functions .............................................................................................. 19
`
`iii
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0003
`
`

`

`Revision 2.1
`
`Chapter 3 Bus Operation
`
`3.1. Bus Co1nmands ................................................................................................................ 21
`
`3 .1.1. Com1nand Definition ......................................................................................... 21
`
`3.1.2. Co1nmand Usage Rules ..................................................................................... 23
`
`3.2. PCI Protocol Fundamentals .............................................................................................. 25
`
`3 .2.1. Basic Transfer Control ...................................................................................... 25
`
`3.2.2. Addressing ........................................................................................................ 26
`
`3.2.3. Byte Alignment ................................................................................................. 29
`
`3.2.4. Bus Driving and Turnaround ............................................................................. 30
`
`3.2.5. Transaction Ordering ......................................................................................... 30
`
`3.2.6. Combining, Merging, and Collapsing ................................................................ 33
`
`3.3. Bus Transactions .............................................................................................................. 35
`
`3.3.1. Read Transaction ............................................................................................... 36
`
`3.3.2. Write Transaction .............................................................................................. 37
`
`3.3.3. Transaction Termination .................................................................................... 38
`
`3.3.3.1. Master Initiated Tennination .............................................................. 38
`
`3.3.3.2. Target Initiated Tennination ............................................................. .40
`
`3.3.3.2.1. Target Tennination Signaling Rules ................................... 42
`
`3.3.3.2.2. Requirements on a Master Because of Target
`Termination ..................................................................... .48
`
`3.3.3.3. Delayed Transactions .......................................................................... 49
`
`3.3.3.3.1. Basic Operation of a Delayed Transaction .......................... 50
`
`3.3.3.3.2.
`
`lnfonnation Required to Complete a Delayed
`Transaction ....................................................................... 51
`
`3.3.3.3.3. Discarding a Delayed Transaction ....................................... 51
`
`3.3.3.3.4. Memory Writes and Delayed Transactions .......................... 52
`
`3.3.3.3.5. Delayed Transactions and LOCK# ...................................... 52
`
`3.3.3.3.6. Supporting Multiple Delayed Transactions ......................... 53
`
`3 .4. Arbitration ........................................................................................................................ 55
`
`3.4.1. Arbitration Signaling Protocol ........................................................................... 57
`
`3.4.2. Fast Back-to-Back Transactions ........................................................................ 59
`
`3.4.3. Arbitration Parking ............................................................................................ 61
`
`iv
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0004
`
`

`

`Revision 2.1
`
`3.5. Latency ............................................................................................................................ 62
`
`3.5.1. TargetLatency .................................................................................................. 62
`
`3.5.1.1. Target Initial Latency ........................................................................ 62
`
`3.5.1.2. Target Subsequent Latency ................................................................ 64
`
`3.5.2. Master Data Latency ......................................................................................... 64
`
`3.5.3. Arbitration Latency ........................................................................................... 65
`
`3.5.3.1. Bandwidth and Latency Considerations ............................................. 66
`
`3.5.3.2. Detennining Arbitration Latency ....................................................... 68
`
`3.5.3.3. Determining Buffer Requirements ..................................................... 72
`
`3.6. Exclusive Access .............................................................................................................. 73
`
`3.6.1. Starting an Exclusive Access ............................................................................ 76
`
`3.6.2. Continuing an Exclusive Access ....................................................................... 77
`
`3.6.3. Accessing a Locked Agent ................................................................................ 78
`
`3.6.4. Completing an Exclusive Access ...................................................................... 79
`
`3.6.5. Supporting LOCK# and Write-back Cache Coherency ...................................... 79
`
`3.6.6. Co1nplete Bus Lock .......................................................................................... 80
`
`3. 7. Other Bus Operations ....................................................................................................... 80
`
`3.7.1. Device Selection ............................................................................................... 80
`
`3.7.2. SpecialCycle .................................................................................................... 81
`
`3.7.3. Address/Data Stepping ...................................................................................... 83
`
`3.7.4. Configuration Cycle .......................................................................................... 84
`
`3.7.4.1. Configuration Mechanism #1 ............................................................ 89
`
`3.7.4.2. Configuration Mechanism #2 ............................................................ 91
`
`3. 7 .5. Interrupt Acknowledge ..................................................................................... 94
`
`3.8. Error Functions ................................................................................................................ 95
`
`3.8.1. Parity ................................................................................................................ 95
`
`3.8.2. Error Reporting ................................................................................................. 96
`
`3.8.2.1. Parity Error Response and Reporting on PERR# ............................... 97
`
`3.8.2.2. Error Response and Reporting on SERR# .......................................... 99
`
`3.9. Cache Support ................................................................................................................ 100
`
`3.9.1. Definition of Cache States .............................................................................. 102
`
`3.9.1.1. Cache - Cacheable Memory Controller ............................................ 102
`
`3.9.2. Supported State Transitions ............................................................................ 103
`
`3.9.3. Ti1ning Diagrams ............................................................................................ 103
`
`3.9.4. Write-through Cache Support ......................................................................... 107
`
`3.9.5. Arbitration Note .............................................................................................. 108
`
`V
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0005
`
`

`

`Revision 2.1
`
`3.10. 64-Bit Bus Extension .................................................................................................... 108
`
`3.10.1. 64-bit Addressing on PCI .............................................................................. 112
`
`3 .11. Special Design Considerations ...................................................................................... 114
`
`Chapter 4 Electrical Specification
`4.1. Overview ........................................................................................................................ 119
`
`4.1.1. 5V to 3.3V Transition Road Map .................................................................... 119
`
`4.1.2. Dynamic vs. Static Drive Specification ........................................................... 121
`
`4.2. Co1nponent Specification ................................................................................................ 122
`
`4.2.1. 5V Signaling Environment .............................................................................. 123
`
`4.2.1.1. DC Specifications ............................................................................ 123
`
`4.2.1.2. AC Specifications ............................................................................ 124
`
`4.2.1.3. Maximum AC Ratings and Device Protection .................................. 126
`
`4.2.2. 3.3V Signaling Environment ........................................................................... 128
`
`4.2.2.1. DC Specifications ............................................................................ 128
`
`4.2.2.2. AC Specifications ............................................................................ 129
`
`4.2.2.3. Maximum AC Ratings and Device Protection .................................. 131
`
`4.2.3. Timing Specification ....................................................................................... 132
`
`4.2.3.1. Clock Specification .......................................................................... 132
`
`4.2.3.2. Ti1ning Parameters ........................................................................... 134
`
`4.2.3.3. Measurement and Test Conditions ................................................... 135
`
`4.2.4. Indetenninate Inputs and Metastability ............................................................ 136
`
`4.2.5. Vendor Provided Specification ........................................................................ 137
`
`4.2.6. Pinout Recommendation ................................................................................. 13 7
`
`4.3. System (Motherboard) Specification ............................................................................... 138
`
`4.3.1. Clock Skew ..................................................................................................... 138
`
`4.3.2. Reset ............................................................................................................... 139
`
`4.3.3. Pull-ups ........................................................................................................... 141
`
`4.3.4. Power .............................................................................................................. 142
`
`4.3.4.1. Power Requirements ........................................................................ 142
`
`4.3.4.2. Sequencing ...................................................................................... 142
`
`4.3.4.3. Decoupling ...................................................................................... 143
`
`4.3.5. Syste1n Ti1ning Budget .................................................................................... 143
`
`vi
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0006
`
`

`

`Revision 2.1
`
`lfff!!.GI
`
`4.3.6. Physical Requirements .................................................................................... 144
`
`4.3 .6.1. Routing and Layout of Four Layer Boards ....................................... 144
`
`4.3.6.2. Motherboard Impedance .................................................................. 145
`
`4.3.7. Connector Pin Assignments ............................................................................ 145
`
`4.4. Expansion Board Specification ....................................................................................... 149
`
`4.4.1. Board Pin Assigntnent .................................................................................... 149
`
`4.4.2. Power Requirements ....................................................................................... 153
`
`4.4.2.1. Decoupling ...................................................................................... 153
`
`4.4.2.2. Power Consumption ........................................................................ 153
`
`4.4.3. Physical Requirements .................................................................................... 154
`
`4.4.3.1. Trace Length Limits ........................................................................ 154
`
`4.4.3.2. Routing ........................................................................................... 155
`
`4.4.3.3. Impedance ....................................................................................... 155
`
`4.4.3.4. Signal Loading ................................................................................ 155
`
`Chapter 5 Mechanical Specification
`
`5.1. Overview ....................................................................................................................... 157
`
`5.2. Expansion Card Physical Dimensions and Tolerances .................................................... 158
`
`5.2.1. Connector Physical Description ...................................................................... 173
`
`5 .2.1.1. Connector Physical Requirements ................................................... 180
`
`5.2.1.2. Connector Perfonnance Specification .............................................. 181
`
`5.2.2. Planar Imple1nentation .................................................................................... 182
`
`Chapter 6 Configuration Space
`
`6.1. Configuration Space Organization .................................................................................. 186
`
`6.2. Configuration Space Functions ....................................................................................... 188
`
`6.2.1. Device Identification ....................................................................................... 188
`
`6.2.2. Device Control ............................................................................................... 189
`
`6.2.3. Device Status .................................................................................................. 191
`
`6.2.4. Miscellaneous Functions ................................................................................. 193
`
`6.2.5. Base Addresses ............................................................................................... 195
`
`6.2.5.1. Address Maps .................................................................................. 196
`
`6.2.5.2. Expansion ROM Base Address Register .......................................... 198
`
`6.2.5.3. Add-in :Memory ............................................................................... 199
`
`vii
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0007
`
`

`

`Revision 2.1
`
`6.3. PCI Expansion ROMs .................................................................................................... 199
`
`6.3.1. PCI Expansion ROM Contents ........................................................................ 199
`
`6.3.1.1. PCI Expansion ROM Header Fonnat ............................................... 200
`
`6.3.1.2. PCI Data Structure Format.. ............................................................. 201
`
`6.3.2. Power-on Self Test (POST) Code .................................................................... 202
`
`6.3.3. PC-compatible Expansion ROMs .................................................................... 202
`
`6.3.3.1. ROM Header Extensions .................................................................. 203
`
`6.3.3.1.1. POST Code Extensions .................................................... 203
`
`6.3.3.1.2. INIT Function Extensions ................................................. 203
`
`6.3.3.1.3. Image Structure ................................................................ 204
`
`6.4. Vital Product Data ........................................................................................................... 205
`
`6.4.1. Importance of Vital Product Data ..................................................................... 205
`
`6.4.2. VPD Location .................................................................................................. 206
`
`6.4.3. VPD Data Structure Description ....................................................................... 206
`
`6.4.4. VPD Format ..................................................................................................... 207
`
`6.4.4.1. Recommended Fields ........................................................................ 208
`
`6.4.4.1. Conditionally Recommended Fields ................................................... 208
`
`6.4.4.2. Additional Fields ............................................................................... 209
`
`6.4.5. VPD Example ................................................................................................. 210
`
`6.5. Device Drivers ................................................................................................................ 211
`
`6.6. System Reset .................................................................................................................. 21 l
`
`6.7. User Definable Configuration Items ................................................................................ 212
`
`6.7.1. Overview ........................................................................................................ 212
`
`6.7.2. PCF Definition ................................................................................................ 213
`
`6.7.2.1. Notational Convention ..................................................................... 213
`
`6.7.2.1.1. Values and Addresses ....................................................... 213
`
`6.7.2.1.2. Text .................................................................................. 214
`
`6.7.2.1.3. Internal Comments ........................................................... 214
`
`6.7.2.1.4. Symbols Used in Syntax Description ................................ 214
`
`6.7.2.2. PCI Configuration File Outline ........................................................ 214
`
`6. 7 .2.2.1. Device Identification Block .............................................. 215
`
`6.7.2.2.2. Function Statement Block ................................................ 216
`
`6.7.2.2.2.1. Choice Statement Block .................................... 217
`
`6.7.2.2.2.1.1. INIT Statements ................................ 217
`
`6.7.3. Sample PCF .................................................................................................... 218
`
`viii
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0008
`
`

`

`Revision 2.1
`
`Chapter 7 66 MHz PCI Specification
`7 .1. Introduction ................................................................................................................... 219
`
`7.2. Scope ............................................................................................................................. 219
`
`7.3. Device Implementation Considerations .......................................................................... 220
`
`7.3.1. Configuration Space ....................................................................................... 220
`
`7.4. Agent Architecture ......................................................................................................... 220
`
`7.5. Protocol ......................................................................................................................... 221
`
`7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition ................................................... 221
`
`7.5.2. Latency ........................................................................................................... 221
`
`7.6. Electrical Specification ................................................................................................... 222
`
`7.6.1. Overview ........................................................................................................ 222
`
`7.6.2. Transition Roadmap to 66 MHz PCI ............................................................... 222
`
`7.6.3. Signaling Environment ................................................................................... 222
`
`7.6.3.1. DC Specifications ............................................................................ 223
`
`7.6.3.2. AC Specifications ............................................................................ 223
`
`7.6.3.3. Maximum AC Ratings and Device Protection ................................. 224
`
`7.6.4. Tilning Specification ...................................................................................... 224
`
`7.6.4.1. Clock Specification ......................................................................... 224
`
`7.6.4.2. Timing Parameters .......................................................................... 225
`
`7.6.4.3. Measurement and Test Conditions ................................................... 226
`
`7.6.5. Vendor Provided Specification ........................................................................ 228
`
`7.6.6. Recommendations .......................................................................................... 228
`
`7.6.6.1. Pinout Rec01mnendations ................................................................ 228
`
`7.6.6.2. Clocking Recommendations ............................................................ 228
`
`7.7. System (Planar) Specification ......................................................................................... 229
`
`7. 7 .1. Clock Uncertainty ........................................................................................... 229
`
`7.7.2. Reset .............................................................................................................. 230
`
`7.7.3. Pullups ........................................................................................................... 230
`
`7.7.4. Power ............................................................................................................. 230
`
`7.7.4.1. Power Requirements ........................................................................ 230
`
`7.7.4.2. Sequencing ...................................................................................... 230
`
`7.7.4.3. Decoupling ...................................................................................... 230
`
`7.7.5. System Timing Budget ................................................................................... 230
`
`ix
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0009
`
`

`

`E!!PI
`
`Revision 2.1
`
`7.7.6. Physical Requirements .................................................................................... 232
`
`7.7.6.1. Routing and Layout of Four Layer Boards ....................................... 232
`
`7.7.6.2. Planar llnpedance ............................................................................. 232
`
`7.7.7. Connector Pin Assigmnents ............................................................................. 232
`
`7.8. Add-in Board Specifications ........................................................................................... 232
`
`Appendix A Special Cycle Messages .......................................................... 233
`
`Appendix B State Machines .............................................................................. 235
`
`Appendix C Operating Rules ............................................................................ 245
`
`Appendix D Class Codes .................................................................................... 2s1
`
`Appendix E System Transaction Ordering .............................................. 257
`
`Glossary ........................................................................................................................... 269
`
`lndex ................................................................................................................................... 275
`
`X
`
`Patent Owner Monterey Research, LLC
`Exhibit 2009, 0010
`
`

`

`Revision 2.1
`
`Figures
`
`E!!.91
`
`Figure 1-1: PCI Local Bus Applications ..................................................................................... 2
`
`Figure 1-2: PCI System Block Diagram ..................................................................................... 3
`
`Figure 2-1: PCI Pin List ............................................................................................................. 7
`
`Figure 3-1: Basic Read Operation ............................................................................................ 36
`
`Figure 3-2: Basic Write Operation ............................................................................................ 37
`
`Figure 3-3: Master Initiated Termination .................................................................................. 39
`
`Figure 3-4: Master-Abort Termination ..................................................................................... 40
`
`Figure 3-5: Retry ...................................................................................................................... 44
`
`Figure 3-6: Disconnect With Data ............................................................................................ 45
`
`Figure 3-7: Master Completion Tennination ........................................................................... .45
`
`Figure 3-8: Disconnect-I Without Data Tennination ............................................................... .46
`
`Figure 3-9: Disconnect-2 Without Data Tennination ............................................................... .4 7
`
`Figure 3-10: Target-Abort ........................................................................................................ 48
`
`Figure 3-11: Basic Arbitration .................................................................................................. 57
`
`Figure 3-12: Arbitration for Back-to-Back Access .................................................................... 61
`
`Figure 3-13: Starting an Exclusive Access ................................................................................ 77
`
`Figure 3-14: Continuing an Exclusive Access .......................................................................... 78
`
`Figure 3-15: Accessing a Locked Agent.. ................................................................................. 78
`
`Figure 3-16: DEVSEL# Assertion ........................................................................................... 80
`
`Figure 3-17: Address Stepping ................................................................................................. 84
`
`Figure 3-18: Configuration Read .............................................................................................. 86
`
`Figure 3-19: Configuration Access Formats ............................................................................. 87
`
`Figure 3-20: Layout ofCONFIG_ADDRESS Register.. ........................................................... 89
`
`Figure 3-21: Bridge Translation for Type O Configuration Cycles ............................................ 90
`
`Figure 3-22: Configuration Space Enable Register Layout ....................................................... 92
`
`Figure 3-23: Translation to Type O Configuration Cycle ........................................................... 93
`
`Figure 3-24: Translation to Type 1 Configuration Cycle ........................................................... 93
`
`Figure 3-25: Interrupt Acknowledge Cycle ............................................................................... 94
`
`Figure 3-26: Parity Operation ................................................................................................... 96
`
`Figure 3-27: Wait States