Michael C. Brogioli, Ph.D.
`
`Contact
`Information
`
`Expertise
`
`Michael C. Brogioli, Ph.D.
`Polymathic Consulting
`100 Congress Avenue, Suite 2000
`Austin, TX 78701 USA
`
`Office: (512) 370-4936
`Cell (preferred): (713) 732-0217
`Fax: (512) 469-6306
`E-mail: michael@polymathicconsulting.com
`
`Software Analysis, Software Architecture, Embedded Computing, Microprocessor Designs, Software
`Based Simulation, Computer Hardware Design, Computer Networks, Computer and Network Based
`Gaming Platforms, High Performance Computing, Digital Signal Processing.
`
`Education
`
`Rice University, Houston, Texas USA
`
`Ph.D., Electrical and Computer Engineering, 2007
`
`• Dissertation Topic: “Reconfigurable Heterogeneous DSP/FPGA Based Embedded Architec-
`tures for Numerically Intensive Embedded Computing Workloads.”
`• Advising Committee: Dr. Joseph R. Cavallaro, Dr. Keith D. Cooper, Dr. Scott Rixner
`
`Rice University, Houston, Texas USA
`
`M.S., Electrical and Computer Engineering, 2003
`
`• Dissertation Topic: “Dynamically Reconfigurable Data Caches in Low Power Computing.”
`• Advising Committee: Dr. Keith D. Cooper, Dr. Scott Rixner, Dr. Robert Jump
`
`Rensselaer Polytechnic Institute, Troy, New York USA
`
`B.S., Electrical Engineering, Cum Laude - 1999
`
`• Advisor: Dr. William Pearlman
`
`Professional
`Experience
`
`Polymathic Consulting, TX USA
`2011 - Present
`Managing Director
`Founder and managing director of Polymathic Consulting, servicing clients ranging from early stage
`technology start-up endeavors to Fortune 100 and beyond. Clients turn to Polymathic for expansive,
`proven engineering, research and development, intellectual property and technical leadership to
`effectively advance their real world business needs.
`
`IEEE and ACM Design Automation Conference, USA
`Steering Committee
`2016 - Present
`Conference Chair, Embedded Systems and Software Track
`Design Automation Conference is the premiere technical conference and trade show specializing
`in Hardware, Software, Internet of Things, Embedded Systems and related Design Methodologies.
`Conference chair, responsible for the review, critique, and acceptance of academia and industry
`based publications in the areas of embedded systems, embedded software, and embedded system
`design.
`
`Rice University, TX USA
`2009 - Present
`Adjunct Professor, Electrical and Computer Engineering
`Professor of Ph.D. candidate level courses in wireless telecommunications, embedded computing soft-
`ware, embedded computing hardware, and software/hardware optimization in modern computing
`systems utilizing modern high level programming languages. Advisor of senior and graduate stu-
`dent based projects revolving around multi-core heterogeneous systems as they pertain to wireless
`telecommunications, medical and video.
`
`RISC-V Foundation, Berkeley, CA USA
`
`Page 1
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`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0001
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`2018 - Present
`Technical Committee
`RISC-V is an open CPU instruction set architecture (ISA) based on established reduced instruction
`set computing (RISC) principles. The RISC-V Foundation is a non-profit consortium chartered to
`standardize, protect, and promote the free and open RISC-V instruction set architecture together
`with its hardware and software ecosystem for use in all computing devices.
`
`Freescale Semiconductor, TX USA
`2009 - 2011
`Chief Architect, Senior Member Technical Staff
`Technical architect of Freescale’s DSP compilers and related technology. Responsible for manage-
`ment of technology, engineering roadmaps, design lead on compiler infrastructure and optimizations
`(high level and low level), next generation ABI definitions and next generation architecture solutions.
`Technical lead on multi-year engagement with processor architects in design of next generation DSP
`cores. Developed software infrastructure for migrating OEM competitor software stacks to Freescale
`solutions, tools generation, software packages, migration strategies and white papers. Technical
`lead on Tier-1 OEM customer relationships, evaluations of 3rd party technologies for potential
`partnerships and acquisitions, led various university research collaborations on behalf of Freescale.
`Development and deployment of internal software engineering policies and practices.
`
`Freescale Semiconductor, TX USA
`Senior Compiler Engineer V
`2008 - 2009
`High Performance Compiler Design, Processor Architecture
`Team leader on compiler engineering effort to provide intuitive, interactive end user experience for
`DSP compiler tool suite. Designed a framework to guide users in achieving highly optimized compiled
`VLIW code. Assembly listing reports for optimization failure advice, porting advice when migrating
`from competitor architectures, advice on code modifications for optimization enablement. Lead
`designer, engineering effort director, project planning and scoping, release schedule, and drafting
`of specification. Development of various compiler optimizations for VLIW processing as well as
`software emulation layers for running competitor software solutions on Freescale silicon.
`
`Advising of next-gen DSP core architecture team in creating a highly orthogonal, compiler targetable
`multi-clustered VLIW based digital signal processor architecture. Work with future basestation
`architecture teams on designing next-gen basestation architecture for 4G LTE incorporating control
`and data plane processing with appropriate programming models.
`
`Method Seven, MA USA
`Technical Co-Founder
`2006 - 2007
`High Performance Software and Hardware Systems Architecture
`Founded Method Seven, a financial engineering company applying biologically inspired machine
`learning to financial market analysis. Principal software systems architect and hardware systems
`architect for both research and deployment platforms. Led research and development of platform
`for scans and overlays covering the NASDAQ, NYSE, and AMEX markets using proprietary tech-
`nologies.
`
`Texas Instruments, TX USA
`Advanced Architecture and Chip Technologies
`2005
`Microprocessor and Systems Architecture
`System modelling and architectural exploration of DavinciTMsystem-on-chip (SOC) architecture
`designed for embedded video processing. SystemC based simulation models of on–chip crossbars,
`bus arbitration and bridge technology, as well as on–chip and off–chip memory controllers within
`application specific heterogeneous SOC architectures.
`
`Fulbright and Jaworski LLP, TX USA
`Scientific Advisor, Intellectual Property
`Electrical, Computer Engineering and Computer Science
`
`2005 - 2007
`
`Page 2
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`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0002
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`Intellectual property consultant and technology advisor on litigation and prosecution work including,
`but not limited to: CDMA2000 3G wireless standards, wireless communications systems, embedded
`computing, and large scale modular software systems. Reverse engineering of source code varying
`from VHDL to high level object oriented applications, as well at patent prosecution and litigation
`work.
`
`Intel Corporation, CA USA
`Microprocessor Research Labs
`2000
`Compiler Engineering
`Implemented speculative multi–threading support in Intel’s IA–64 compiler. Developed new program
`analysis and back end code generation phases to support speculatively launching threads at runtime.
`Analyzed the performance potentials of SPEC95 benchmarks with respect to speculatively multi–
`threaded execution.
`
`Rice University, TX USA
`2000 - 2003
`Computer Architecture and Circuit Design (Instructor)
`Graduate instructor of graduate and undergraduate curriculim in the areas of Electrical and Com-
`puter Engineering, specifically relating to Computer Architecture and Circuit Design. Advised
`student projects, instructed classes and led laboratory work.
`
`Vicarious Visions, NY USA
`1999
`Lead Software Engineer
`Principal engineer on Activision’s “AMF Extreme Bowling” for Nintendo’s Color Gameboy gaming
`console. Developed PC based audio and graphics development tools suite for use with Color Game-
`boy game production. Coded innovative, highly optimized assembly routines for real time speech
`and full motion video on the console’s limited Zilog Z80 processor resources.
`
`Stratus Computer, MA USA
`1997 - 1998
`Hardware Engineering
`Debugged locked step CPU operation and memory management issues in Stratus’ fault tolerant
`UNIX release 3.4. Qualified Hewlett Packard PA–8000 series CPU modules under Stratus’ propri-
`etary OS release, VOS 14.0, during alpha and beta test phases. Wrote C code and UNIX shell scripts
`for recreating documented system failures, and to automate remote kernel updates and OS installs
`as well as data logging.
`
`Rensselaer Polytechnic Institute, NY USA
`1997 - 1998
`Digital Microelectronics Design (Instructor)
`Undergraduate instructor of undergraduate courses in digital microelectronics and circuit design.
`Instructed weekly lessons, computer design labs, graded exams and problem sets.
`
`Rensselaer Electric Motor Sports, NY USA
`1995 - 1997
`Hardware and Software Engineering
`This project was funded by, and led by, General Motors Corporation and Honda of America. Hard-
`ware and software co-design of embedded operating system and hardware platform for electrical
`vehicle prototypes, running on 16-bit Motorola 68K dual processor platform. Designed power engi-
`neering test platform for dynamometers, including hardware and user interface software.
`
`Books and
`Contributed
`Chapters
`
`Brogioli, Michael C., and Kraeling, Mark B., Internet of Things - A Synopsis of the Internet of
`Things, its History, Application, Technology, Architecture, and Challenges Moving Forward, Soft-
`ware Engineering for Embedded Systems - Methods, Practical Techniques and Applications, 2nd
`Edition, Elsevier Publishing, 2019.
`
`Brogioli, Michael C., Software and Compiler Optimization for Microcontrollers, Embedded Proces-
`sors and DSPs, Software Engineering for Embedded Systems - Methods, Practical Techniques and
`
`Page 3
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`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0003
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`

`Applications, 2nd Edition, Elsevier Publishing, 2019.
`
`Brogioli, Michael C., Embedded and Multicore System Architecture - Design and Optimization, Soft-
`ware Engineering for Embedded Systems - Methods, Practical Techniques and Applications, 2nd
`Edition, Elsevier Publishing, 2019.
`
`Leotescu, Florin, and Cristian, Marius and Brogioli, Michael C., Performance Analysis using NXP’s
`i.MX RT1050 Crossover Processor and the Zephyr Real-Time Operating System, Software Engineer-
`ing for Embedded Systems - Methods, Practical Techniques and Applications, 2nd Edition, Elsevier
`Publishing, 2019.
`
`Wu, Michael and Sun, Yang and Wang, Guohui and Brogioli, Michael C. and Cavallaro, J. R.,
`Implementation of a High Throughput 3GPP Turbo Decoder on GPU Architectures, Software De-
`velopment for Networking Applications – Expert Guides Series, Elsevier Publishing, Atlanta, GA,
`2018.
`
`Brogioli, M. C., On The C++ Programming Language for Embedded Software, Systems, and Plat-
`forms, Software Engineering for Embedded Systems – Expert Guides Series, Elsevier Publishing,
`Atlanta, GA, 2013.
`
`Brogioli, M. C., Software Optimizations for Memory Performance in Embedded Systems, Software
`Engineering for Embedded Systems – Expert Guides Series, Elsevier Publishing, Atlanta, GA, 2013.
`
`Invited Co-Author, Signal Processing Systems Handbook, Second Edition, Springer Publishing Com-
`pany, 11 West 42nd Street, New York, NY, 2012.
`
`Brogioli, M. C., Software Programmable DSP Architectures, Expert Guide DSP for Embedded and
`Real-Time Systems, pp. 63-75, Elsevier Publishing, Atlanta, GA, 2012.
`
`Brogioli, M. C., The DSP Hardware / Software Continuum, Expert Guide DSP for Embedded and
`Real-Time Systems,, pp. 103-113, Elsevier Publishing, Atlanta, GA, 2012.
`
`Brogioli, M. C., DSP Optimization - Memory Optimization, Expert Guide DSP for Embedded and
`Real-Time Systems, pp. 217-241, Elsevier Publishing, Atlanta, GA, 2012.
`
`Brogioli, M. C. and Dew, Stephen, Optimizing DSP Software - High level Languages and Program-
`ming Models, Expert Guide DSP for Embedded and Real-Time Systems,, pp. 167-179, Elsevier
`Publishing, Atlanta, GA, 2012.
`
`Sun, Yang, Amiri, Kiarash, Brogioli, Michael, Wang, Guohui, and Cavallaro, Joseph R., DSP Hard-
`ware Accelerator Architectures for Communication Applications, Springer Publishing, New York,
`NY, Spring 2012.
`
`Sun, Yang, and Amiri, Kiarash, and Brogioli, Michael C., and Cavallaro, Joseph, Application-Specific
`Accelerators for Communications, Springer Publishing Company, 11 West 42nd Street, New York,
`NY, 2010.
`
`Invited Co-Author, Signal Processing Systems Handbook, First Edition, Springer Publishing Com-
`pany, 11 West 42nd Street, New York, NY, 2010.
`
`Publications and
`Invited Papers
`
`Brogioli, Michael, C., and Games, William, and Moats, Richard, Current and Future Challenges
`in Internet of Things (IoT) Development Silos (Part I), Embedded Computing Design Magazine,
`USA, 2020.
`
`Page 4
`Generated: Tuesday 2nd March, 2021
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`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0004
`
`

`

`Brogioli, Michael, C., and Games, William, and Moats, Richard, On Solving the IoT Development
`Silo Problem IEEE Real-Time and Embedded Technology and Applications Symposium, Tools and
`Demos Session, Montreal, Canada, 2019.
`
`Moats, Richard, and Games, Bill, and Brogioli, M. C., Arch - A New Language For The Next Wave
`of Network-Connected Embedded Development, Design Automation Conference, Austin, Texas, 2017.
`
`Moats, Richard, and Games, Bill, and Brogioli, M. C., Network Native - The Next Wave of Connected
`Embedded Development, Network Native Inc., Austin, Texas, 2017.
`
`Invited Paper, Arokia I, Brogioli, Michael, Jain, Nitjin and Garg, Umang, LTE Layer 1 Software
`Design on Heterogeneous Multicore DSP Platforms, IEEE 45th Asilomar Conference on Signals,
`Systems and Computers, Pacific Grove, CA, 2011.
`
`Kyriakopoulous, Konstantinos, Brogioli, Michael C., and Zhang, Ruihao, Improving Software Sys-
`tems Quality through Well Defined Development Methodologies, 2011 Test Methodology and Effi-
`ciency Symposium, Freescale Semiconductor, Austin, TX, USA, 2011.
`
`Brogioli, Michael C., and Cavallaro, J.R., Compiler Driven Architecture Design Space Exploration
`for Embedded DSP Workloads: A Study in Software Programmability Versus Hardware Acceleration,
`IEEE 43rd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2009.
`
`Brogioli, Michael C., and Zhang, Ruihao, Compiler Feedback: Guiding Performance of Compiled C
`Code, Freescale Semiconductor White Paper, Austin, TX, 2009.
`
`Brogioli, M.C., and Cavallaro, J., RISD: A Retargetable Compiler Infrastructure for Scalable Multi-
`Clustered VLIW DSP Architectures, IEEE 5th Dallas Circuits and Systems Workshop, Dallas, TX,
`2007.
`
`Brogioli, Michael C., Radosavljevic, P., and Cavallaro, J., A General Hardware/Software Codesign
`Methodology for Embedded Signal Processing and Multimedia Workloads, IEEE 40th Asilomar Con-
`ference on Signals, Systems, and Computers, Pacific Grove, CA, 2006.
`
`Brogioli, Michael C., Radosavljevic, P., and Cavallaro, J., Hardware/Software Co-design Methodology
`for DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.5G
`Mobile Receivers, 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan,
`Puerto Rico, 2006.
`
`Brogioli, Michael C., Willmann, P.D., and Rixner, S., Parallelization Strategies for Network Interface
`Firmware, IEEE/ACM 4th Annual Workshop on Optimizations for DSP and Embedded Systems
`(In Conjunction with IEEE/ACM International Symposium on Code Generation and Optimization),
`Manhattan, NY, 2006.
`
`Brogioli, Michael C., Gadhiok, M., and Cavallaro, J., Design and Analysis of Heterogeneous DSP/FPGA
`Based Architectures for 3GPP Wireless Systems, IEEE Real-Time and Embedded Technology and
`Applications Symposium Work-in-Progress Sessions, San Jose, CA, 2006.
`
`Brogioli, Michael C., and Cavallaro, J., Modelling Heterogeneous DSP-FPGA Based System Parti-
`tioning with Extensions to the Spinach Simulation Environment, IEEE 39th Asilomar Conference
`on Signals, Systems, and Computers, Pacific Grove, CA, 2005.
`
`Joseph R. Cavallaro, Michael C. Brogioli, Alexandre de Baynast, and Predrag, Radosavljevic, Re-
`configurable Architectures for Wireless Systems: Design Exploration and Integration Challenges,
`Wireless World Research Forum, Toronto, CA, 2004.
`
`Page 5
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`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0005
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`

`

`Brogioli, Michael C., Pai, V.S., Willmann, P.D., Spinach: A Liberty–Based Simulator For Pro-
`grammable Network Interface Architectures, ACM SIGPLAN/SIGBED Conference on Languages
`Compilers and Tools for Embedded Systems, San Diego, CA, 2004.
`
`Brogioli, Michael C., Dynamically Reconfigurable Data Caches in Low Power Computing, Masters
`Thesis, Rice University, Houston Texas, 2002.
`
`Brogioli, Michael C., and Jones, Bryan, Dynamically Configurable Caches in Low Power Computing,
`Internal White Paper, Rice University, Houston Texas, 2001.
`
`Patents
`
`Michael C. Brogioli and Gregory D. Chiocco, Systems and Methods for Connected Computation
`in Network Constrained Systems, U.S. Patent Application 62907727, filed October 2019. Patent
`Pending.
`
`Donald W. Games, Michael C. Brogioli Ph.D., Richard Moats, System And Method for Holistic
`Application Development and Deployment in a Distributed Heterogeneous Computing Environment,
`U.S. Patent Application 62782009, filed December 2018. Patent Pending.
`
`Michael C. Brogioli, Ph.D., Cesar Taylor M.D., and Howard Roberts, Location Agnostic Plat-
`form for Medical Condition Monitoring and Prediction and Method of Use Thereof, Patent No:
`147145.010100/US, 2014.
`
`Cesar Taylor M.D., and Michael C. Brogioli Ph.D., and Howard Roberts, System for Holistic Pain
`Monitoring and Prediction and Method of User Thereof, Patent No: 147145.010200/US, 2014.
`
`Cesar Taylor M.D., and Michael C. Brogioli Ph.D., and Howard Roberts, System for Prevention of
`Narcotic Diversion and Method of Use Thereof, Patent No: 147145.010300/US, 2014.
`
`Howard Roberts, Cesar Taylor M.D., and Michael C. Brogioli Ph.D., Magnetometer Breathing Sensor
`and Method of User Thereof, Patent No: 147145.010400/US, 2014.
`
`Leadership and
`Board
`Membership
`
`MIT MassChallenge USA
`2017 - Present
`Mentor, Speaker
`MassChallenge is a global startup accelerator with a focus on high-impact, early-stage entrepreneurs.
`Through its global network of accelerators in Boston, London, Mexico City, Geneva, Jerusalem and
`Texas, coupled with unrivaled access to our corporate partners, MassChallenge has driven growth
`and created value the world over. To date, MassChallenge has raised over $2B in funding, generated
`over $900M in revenue, and created over 65,000 jobs.
`
`ScribeSense, TX USA
`2017
`Board of Directors
`ScribeSense is a patented cloud-based grading platform for schools and the only solution for grad-
`ing free-form paper tests. ScribeSense automatically grades handwritten tests with 99% accuracy.
`Teachers scan and upload their own tests using a standard school scanner. ScribeSense’s visual
`analytics enables data-driven decision making so schools can improve student learning and retain
`top teacher talent.
`
`Southwest Angel Network for Social Impact, TX USA
`2015 - 2019
`Board of Directors
`The Southwest Angel Network for Social Impact ( SWAN Impact ) is a community of like-minded
`investors who enjoy working together to Make the world a better place, one company at a time. We
`believe that we can have the most significant impact by funding for-profit start-up companies who
`are building sustainable businesses.
`
`Page 6
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`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0006
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`

`Network Native, TX USA
`2015 - Present
`Board of Directors, Co-Founder, Interim CTO
`Board member and co-inventor, advising in the areas of Internet of Things technologies, specifically
`related to product developer solutions, programming languages and platforms, security and infras-
`trucure. Business development, marketing, and fund raising. Have held various roles, including but
`not limited to interim CTO.
`
`NewCrew, TX USA
`2015 - 2016
`Advisory Board
`Board member advising in the areas of mobile computing, social computing, and geofencing tech-
`nologies. Business development, marketing, and fund raising.
`
`AngelSpan, TX USA
`2015 - 2016
`Advisory Board
`Board member advising in the areas of professional investor relations to start-ups, resource allocation,
`and a platform for increased efficiency and valuation of early stage companies and venture capital
`portfolios.
`
`Student Loan Genius (now Vault), TX USA
`2013 - 2014
`Advisory Board, Interim CTO
`Advisory board member and interim CTO advising in the areas of financial transactions systems
`and enterprise software, as they pertain to solving the student loan debt crisis for early stage science,
`technology, engineering and medicine (STEM) employees. Technology, recruiting, fund raising.
`
`HealthBits, TX USA
`2013 - 2014
`Board Member, Co-Inventor
`Board member advising in the areas of large scale enterprise software systems, real-time computing
`and medical sensing devices across complex event processing systems.
`
`Osmek, TX USA
`2012 - 2014
`Interim CTO, Advisory Board
`Interim CTO and board member advising in the areas of large scale cloud based content management
`software systems. Providing innovative media content management for heterogeneous web enabled
`devices with geolocational services, primarily using PHP and Python programming languages.
`
`Rice University, Houston, Texas USA
`2005 - 2009
`DSP Compiler Design
`Developed RISD, a retargetable compiler infrastructure for clustered VLIW DSP architectures. By
`taking pre-existing code schedules and binaries for existing DSP applications, RISD takes a flexible
`machine definition for which the code should be recompiled. Users can specify the number of VLIW
`clusters, functional units per VLIW cluster, functional unit mix per VLIW cluster, register file
`sizes, cluster interconnect topology (point-to-point versus 2d mesh network), multi-cluster scheduling
`algorithms, and inter-cluster cross-register file bandwidth and latencies.
`
`Compiler framework was used to perform compiler driven design space exploration of massively
`multi-clustered VLIW based architectures versus FPGA and ASIP implementations of software
`kernels. RISD was used in studies comparing tradeoffs in computational throughput versus gates
`required to implement programmable DSP cores containing many register files and VLIW compute
`clusters, versus FPGA efficiency when including routing overhead for large scale problems.
`
`Rice University, Houston, Texas USA
`2004 - 2009
`DSP/FPGA Based System-On-Chip Architectural Simulator Design
`Developed Spinach DSP-FPGA, a modular and composable simulator design infrastructure for pro-
`grammable and reconfigurable embedded SOC architectures. Designed and developed modular and
`
`Page 7
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`Academia
`
`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0007
`
`

`

`composable software modules to bit-true, cycle accurately simulate Texas Instruments C62x and
`C64x DSPs and MIPS style processors. Additionally designed and developed support for SRAM
`and DRAM style memories, heterogeneous memory systems, heterogeneous clock domains, as well
`as runtime reconfigurable Xilinx Virtex II based FPGA computing elements, cache and memory
`controllers, bus arbiters, and on-chip interconnect fabric.
`
`System was validated against compiled code DSP firmware from Texas Instruments’ Code Composer
`Studio running on the simulator versus actual hardware benchmarks. Simulation platform was used
`to investigate highly heterogeneous multi-processor DSP based SOC architectures containing one or
`more Xilinx style FPGA based hardware coprocessors. Studies in 3.5G wireless telecommunications
`as well as H.26x video processing were performed to gain insight into overall system bottlenecks,
`hardware and software partitioning strategies, and tradeoffs of overall system design.
`
`Rice University, Houston, Texas USA
`Programmable Network Interface Architecture Simulator Design
`National Science Foundation Grant Nos. CCF-0532448 and CNS-0532452
`Developed Spinach, a simulator design toolset for modelling programmable network interface archi-
`tectures. Spinach models system components common to all programmable environments (ALUs,
`control and data paths, register files, instruction processing), as well as components specific to em-
`bedded computing (software controlled SRAM scratchpad memory, hardware assists for DMA and
`medium access control). Spinach is a simulator design infrastructure, rather than a simulator per
`se. As such, the same underlying C code framework is used to model a uniprocessor Gigabit net-
`work interface, a multi-processor Gigabit network interface, or a 10 Gigabit multi-processor network
`interface with highly heterogeneous memory systems. Only a small number of lines of high level
`scripting language code is required to describe each of the various systems.
`
`2002 - 2004
`
`Spinach was validated by modeling the Tigon-2 programmable Ethernet controller by Alteon Web-
`systems, running actual compiled code Ethernet processing firmware and by comparing the reported
`results to actual hardware benchmarks. Spinach was also used to obtain new insights into the per-
`formance of Gigabit and 10 Gigabit network interfaces both in terms of hardware architecture and
`firmware parallelization strategies. Public Website: https://sourceforge.net/projects/spinach/
`
`Rice University, Houston, Texas USA
`2000
`Software Engineering and Consulting
`Implemented instruction selection and register allocation optimizations in UHFFT, an adaptive and
`portable software library for the Fast Fourier Transform. Performed in depth analysis of register
`pressure, compiler generated spill code, memory hierarchy utilization, and instruction selection for
`non–trivially sized FFT matrices running on commercially available hardware platforms. Utilized
`reverse Cuthill–McKee technique to achieve near optimal computation orderings and minimize live
`data set sizes, as well as optimize register allocation and instruction selection phases of compilation.
`
`Appointed
`Conference
`Committees and
`Organizations
`
`IEEE and ACM Design Automation Conference, USA
`2019 - Present
`Technical Steering Committee, Embedded Computing Track
`Technical Steering Committee member responsible for the review, critique, and acceptance of academia
`and industry based publications and research in the area of embedded computing and related sys-
`tems, including embedded hardware, embedded software, firmware and tools.
`
`IEEE and ACM Design Automation Conference, USA
`2014 - 2019
`Program Committee, Embedded Systems and Software Track
`Program Committee member responsible for the review, critique, and acceptance of academia and
`industry based publications in the areas of embedded systems, embedded software, and embedded
`system design. Design Automation Conference is an annual technical conference and trade show
`specializing in electronic systems.
`
`Page 8
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`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0008
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`

`

`IEEE and ACM Design Automation Conference, USA
`2011 - Present
`Program Committee, Designer and User Track
`Program Committee member responsible for the review, critique, and acceptance of academia and
`industry based publications in the areas of automated system design, both of hardware, software,
`and system analysis. Design Automation Conference is an annual technical conference and trade
`show specializing in electronic systems.
`
`ACM Great Lakes Symposium on VLSI, Stresa-Lago Maggiore, Italy
`2007
`Program Committee
`Reviewer and committee member in the area of system-on-chip architectures, VLSI design, and
`compiler driven architecture design space exploration.
`
`IEEE International Symposium on Personal Indoor and Mobile Radio Communications,
`Helsinki, Finland
`2006
`Program Committee
`Reviewer and committee member in the area of personal and mobile area radio communications and
`related systems.
`
`ACM International Conference on Parallel Architectures and Compilation Techniques,
`Charlottesville, VA, USA
`2002
`Program Committee
`Reviewer and committee member in the area of parallel computer architectures, programming lan-
`guages and related compiler technologies.
`
`Selected Expert
`Witness,
`Consulant
`Engagements
`
`Advanced Micro Devices Inc. v. Monterey Research LLC*
`Desmarais LLP, NY, USA
`2021 - Present
`Expert Witness in memory systems, interconnects
`Case Subject Matter - SRAM and DRAM technology, multi-ported memory systems and related
`technologies.
`Work Performed - Expert consulting, declarations.
`
`Analog Devices Inc. v. Xilinx Inc.*
`Morrison & Foerster LLP, CA, USA
`2020 - Present
`Expert Witness in FPGAs and configurable computing
`Case Subject Matter - FPGAs and solutions related to crossbar interconnects, and configurable
`computing.
`Work Performed - Expert consulting, declarations.
`
`TriOptima AB v. Quantile Technologies Limited*
`Caldwalader Wickersham & Taft, New York, USA
`2020
`Expert Witness in Source Code for FinTech Systems
`Case Subject Matter - Technology implementations of financial services related to compression and
`derivatives markets.
`Work Performed - Expert consulting, source code review.
`
`Karya Property Management, LLC* v. ResMan, LLC
`Baker Botts LLP, Houston, Texas, USA
`2020 - Present
`Expert Witness in Distributed Software Systems
`Case Subject Matter - Expert witness in the areas of distributed software systems, including data
`base technologies, as they relate to propety management software and related systems.
`Work Performed - Expert consulting, claim construction, IPR declarations, CBM declarations, de-
`position.
`
`Certain Touch-Controlled Mobile Devices, Computers, and Components Thereof, Inv.
`
`Page 9
`Generated: Tuesday 2nd March, 2021
`
`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0009
`
`

`

`No. 337-TA-1193
`Neodron Limited*
`Russ, August, and Kabat LLP, Los Angeles, CA, USA
`2020
`Expert Witness in Touch Screen Technology and Related Systems
`Case Subject Matter - Expert witness in hardware/software systems for touch screen techology in
`mobile devices.
`Work Performed - Expert consulting.
`
`VLSI Technology LLC* v. Intel Corporation
`Irell & Manella LLP, Los Angeles, CA USA
`2020 - Present
`Expert Witness in Computer Architecture
`Case Subject Matter - Expert witness in the area of computer architecture, and low power manage-
`ment.
`Work Performed - Expert consulting and source code review, expert reports, deposition.
`
`Optimum Imaging Technologies LLC* v. Canon Inc.
`Ruyak Cherian LLP, Washington D.C., USA
`2019 - Present
`Expert Witness in FPGA Based Image Processing Systems
`Case Subject Matter - Expert witness and consultant in the area of heterogeneous FPGA/DSP/CPU
`based systems as applied to image and video processing technology.
`Work Performed - Expert consulting, claim construction declarations, expert reports, depositions,
`IPR declarations (to date).
`
`Dish Network, LLC v. Contemporary Display LLC*
`Toler Law Group, P.C., Texas., USA
`2020
`Expert Witness in Real Time Video Processing
`Case Subject Matter - Expert Witness in real-time video processing technology over Internet, in-
`cluding related user interfaces and quality of service.
`Work Performed - Consulting, IPR declarations, deposition.
`
`Dish Network, LLC v. Contemporary Display LLC*
`Toler Law Group, P.C., Texas., USA
`2020
`Expert Witness in Real Time Video Processing
`Case Subject Matter - Expert Witness in real-time video processing technology over Internet, in-
`cluding related user interfaces and quality of service.
`Work Performed - Consulting, IPR declarations, deposition.
`
`Multimedia Content Management LLC* v. Dish Network LLC
`Sheridan Ross P.C., Colorado, USA
`2019 - 2020
`Expert Witness in Real Time Video Processing
`Case Subject Matter - Expert Witness in Internet based real-time video processing set top boxes,
`and related content processing and distribution.
`Work Performed - Expert consulting.
`
`Exegy Inc. et al v. ACTIV Financial Systems, Inc.*
`Wolf Greenfield & Sachs P.C., USA
`2019 - Present
`Expert Witness High Speed Computing for Financial Services
`Case Subject Matter - Expert Witness in microprocessor and FPGA based system design for high
`speed financial services.
`Work Performed - Expert consulting, IPR declarations (to date).
`
`Certain Touch-Controlled Mobile Devices, Computers, and Components Thereof, Inv.
`No. 337-TA-1162
`Neodron Limited*
`
`Page 10
`Generated: Tuesday 2nd March, 2021
`
`Patent Owner Monterey Research, LLC
`Exhibit 2005, 0010
`
`

`

`Russ, August, and Kabat LLP, Los Angeles, CA, USA
`2019 - 2020
`Expert Witness in Touch Screen Technology and Related Systems
`Case Subject Matter - Expert witness in hardware/software systems for touch screen techology in
`mobile devices.
`Work Performed - Expert consulting, cl