Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________________________________
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`__________________
`
`Case IPR2020-00985
`
`U.S. Patent No. 6,651,134
`__________________
`
`DECLARATION OF MICHAEL C. BROGIOLI, PH.D.
`
`DRAFT DECLARATION – PRIVILEGED & CONFIDENTIAL
`PROTECTED UNDER PEVARELLO V. LAN
`
`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0001
`
`

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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`TABLE OF CONTENTS
`
`Page
`
`I.
`
`II.
`
`Introduction .................................................................................................. 1
`
`Bases for Opinions ....................................................................................... 1
`
`III. Materials reviewed ....................................................................................... 2
`
`IV. Education and Experience ............................................................................ 2
`
`A. Overview............................................................................................ 3
`
`B.
`
`Experience with Burst Mode Accesses In Memory Devices. .............. 6
`
`V.
`
`Legal standards ............................................................................................ 7
`
`A.
`
`B.
`
`C.
`
`D.
`
`Burden of Proof .................................................................................. 7
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`Anticipation and Obviousness ............................................................ 8
`
`1.
`
`2.
`
`Anticipation ............................................................................. 8
`
`Obviousness ............................................................................. 9
`
`Independent Claims and Dependent Claims ..................................... 12
`
`Claim Construction .......................................................................... 13
`
`VI. Level of Ordinary Skill in the Art ............................................................... 15
`
`VII. Technical Background................................................................................ 16
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`SRAM/DRAM Memory Devices ..................................................... 16
`
`On-Chip Memories........................................................................... 19
`
`Input/Output Devices ....................................................................... 20
`
`Burst Memory Access ...................................................................... 22
`
`Burst Transfer Communications Between Devices In A
`Computing System. .......................................................................... 25
`
`VIII. The ’134 Patent .......................................................................................... 31
`DRAFT DECLARATION – PRIVILEGED & CONFIDENTIAL
`PROTECTED UNDER PEVARELLO V. LAN
`
`
`i
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0002
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`A.
`Priority Date of the ’134 Patent ........................................................ 31
`
`B.
`
`Overview of the ’134 Patent ............................................................. 32
`
`IX. Overview of Wada ..................................................................................... 42
`
`X.
`
`Overview of Secondary References ............................................................ 46
`
`A.
`
`B.
`
`C.
`
`D.
`
`Barrett .............................................................................................. 46
`
`Fujioka ............................................................................................. 51
`
`Reeves .............................................................................................. 52
`
`Lysinger ........................................................................................... 53
`
`XI. Claim Construction .................................................................................... 54
`
`A.
`
`B.
`
`All Challenged Claims: “non-interruptible”. .................................... 54
`
`Claim 16: “means for reading data . . . / means for generating a
`predetermined number of said internal address signals in
`response to (i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals”. ..................................................... 55
`
`XII. Summary of Opinions ................................................................................ 56
`
`XIII. Opinions About the Challenged Claims...................................................... 57
`
`A. Wada does not disclose all elements of Claims 1-3, 8, 12-13,
`16, or 17 (Grounds 1 and 2).............................................................. 57
`
`1. Wada Does Not Disclose “generating a predetermined
`number of said internal address signals.” ................................ 58
`a. Wada’s Conventional Embodiment Does Not
`Generate A Predetermined Number Of Internal
`Address Signals. ........................................................... 60
`
`b. Wada’s Second Embodiment Does Not Generate A
`Predetermined Number Of Internal Address
`Signals. ........................................................................ 66
`
`ii
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0003
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`2. Wada Does Not Disclose “wherein said generation of
`said predetermined number of internal address signals is
`non-interruptible..................................................................... 71
`a. Wada’s Conventional And Second Embodiments
`Disclose Terminating Bursts. ....................................... 72
`
`b. Wada Is Not Directed To Preventing Interruptions
`Within A Burst ............................................................. 76
`
`Claims 1-4, 8, 12-14, and 16-17 are not obvious over
`Wada (Ground 2) ................................................................... 79
`
`In February 2000, a POSITA would not have had reason
`to modify Wada to achieve the challenged claims. ................. 80
`
`A Person Of Ordinary Skill In The Art Would Not Have
`Expected The Modified Version Of Wada To Succeed. ......... 81
`
`3.
`
`4.
`
`5.
`
`B.
`
`Claims 1-4, 8, 12-14, 16, and 17 Are Not Obvious Over Wada
`In Combination With Barrett (Ground 2a). ....................................... 82
`
`1.
`
`2.
`
`3.
`
`The Combination Of Wada And Barrett Does Not
`Disclose “generating a predetermined number of [said]
`internal address signals”. ........................................................ 83
`
`The Combination of Wada And Barrett Does Not
`Disclose “wherein said generation of said predetermined
`number of internal address signals is non-interruptible”. ........ 84
`
`In February 2000, A POSITA Would Not Have Been
`Motivated To Combine And Modify Wada And Barrett
`To Achieve The Challenged Claims. ...................................... 88
`a. Wada And Barrett Describe Different Burst
`Operations. ................................................................... 88
`
`b. Wada And Barrett Are Directed To Different
`Operational Procedures. ............................................... 92
`
`c. Wada And Barrett’s Different Systems Operate At
`Different Speeds And Scales Of Data. .......................... 98
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`iii
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0004
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`d. Wada And Barrett’s Different Systems Operate
`According To Different Timing Requirements. .......... 100
`
`e.
`
`f.
`
`Combining Wada And Barrett Would Destroy A
`Key Objective Of Each Reference. ............................. 103
`
`Wada And Barrett Are Not Directed To The Same
`Purpose. ..................................................................... 105
`
`4.
`
`A Person Of Ordinary Skill In The Art In February 2000
`Would Not Reasonably Expect The Combination Of
`Wada And Barrett To Succeed. ............................................ 105
`
`C.
`
`Claims 3–7, 13, 18–20, and 22 are not obvious over Wada,
`alone or in combination with the asserted secondary references
`(Grounds 3, 3a, 4, 4a, 5, 5a). .......................................................... 111
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`Claims 4-7 and 18-20 Are Not Obvious Over Wada
`Combined With Fujioka (Ground 3). .................................... 111
`
`Claims 4-7 and 18-20 Are Not Obvious Over Wada
`Combined With Barrett And Fujioka (Ground 3a). ............... 112
`
`Claims 9-10, 14, And 21 Are Not Obvious Over Wada
`Combined With Reeves (Ground 4). .................................... 112
`
`Claims 9-10, 14, And 21 Are Not Obvious Over Wada
`Combined With Barrett and Reeves (Ground 4a). ................ 113
`
`Claims 11 And 15 Are Not Obvious Over Wada
`Combined With Lysinger (Ground 5). .................................. 113
`
`Claims 11 And 15 Are Not Obvious Over Wada
`Combined With Barrett And Lysinger (Ground 5). .............. 114
`
`No Reasonable Expectation of Success ................................ 114
`
`D.
`
`Objective Indicia of Non-Obviousness ........................................... 115
`
`1.
`
`JEDEC DDR-Compliant Memory Is A Commercial
`Embodiment Of The ’134 Patent. ......................................... 115
`a.
`Independent Claim 1 .................................................. 116
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`iv
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0005
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`a.
`
`b.
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`c.
`
`Element 1p: A circuit comprising ..................... 116
`
`Element 1a: a memory comprising a plurality of
`storage elements each configured to read and write
`data in response to an internal address signal; and
` ......................................................................... 116
`
`Element 1b: a logic circuit configured to generate a
`predetermined number of said internal address
`signals in response to (i) an external address
`signal, (ii) a clock signal and (iii) one or more
`control signals, wherein said generation of said
`predetermined number of internal address signals
`is non-interruptible. .......................................... 118
`
`b.
`
`Independent Claim 16 ................................................ 121
`
`a.
`
`b.
`
`c.
`
`Element 16p: A circuit comprising: ................. 121
`
`Element 16a: means for reading data from and
`writing data to a plurality of storage elements in
`response to a plurality of internal address signals,
`and ................................................................... 122
`
`Element 16b: means for generating a
`predetermined number of said internal address
`signals in response to (i) an external address
`signal, (ii) a clock signal and (iii) one or more
`control signals, wherein said generation of said
`predetermined number of internal address signals
`is non-interruptible. .......................................... 124
`
`c.
`
`Independent Claim 17 ................................................ 127
`
`a.
`
`b.
`
`c.
`
`Element 17p: A method of providing a fixed burst
`length data transfer comprising the steps of: ..... 127
`
`Element 17a: accessing a memory in response to a
`plurality of internal address signals, and ........... 128
`
`Element 17b: generating a predetermined number
`of said internal address signals in response to (i) an
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`v
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0006
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`

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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
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`external address signal, (ii) a clock signal and (iii)
`a control signal, wherein said generation of said
`predetermined number of internal address signals
`is non-interruptible. .......................................... 128
`
`2.
`
`3.
`
`Benefits of the Invention ...................................................... 128
`
`Long-Felt, But Unmet Need ................................................. 129
`
`XIV. Appendix A: The Challenged Claims Of the ’134 Patent ......................... 137
`
`XV. Appendix B: Materials Reviewed ............................................................. 141
`
`vi
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0007
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`

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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`I.
`INTRODUCTION
`
`I, Dr. Michael C. Brogioli, Ph.D., a resident of Austin, Texas, over 18 years
`
`of age, hereby declare as follows:
`
`1.
`
`I have personal knowledge of all of the matters about which I testify in
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`this declaration.1
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`2.
`
`Desmarais LLP retained me on behalf of Monterey Research, LLC
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`(“Monterey”) to provide my technical opinions and testimony about the petition for
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`inter partes review (“Petition”) filed by Advanced Micro Devices, Inc. (“AMD”)
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`against Claims 1-21 of U.S. Patent No. 6,651,134 (“the ’134 Patent”). I refer to
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`those claims as the “challenged claims.” The full text of the challenged claims
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`appears in Appendix A to my declaration.
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`3.
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`For my work in this matter, I am being compensated at my usual
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`consulting rate of $700/hour, and I am receiving reimbursement for expenses
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`incurred in the course of my work. My compensation is not contingent in any way
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`on either the opinions I have reached or the outcome of this case.
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`II.
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`BASES FOR OPINIONS
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`4.
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`I have reviewed and considered the documents and other materials
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`listed below in Section III in light of my specialized knowledge provided by my
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`education, training, research, and experience, as summarized in Section IV and
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`1 All emphases in quotations in this declaration are added unless otherwise specified.
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`1
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0008
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`described in detail in my CV, which is provided as Exhibit 2005. My analysis of
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`those materials, combined with the specialized knowledge that I have obtained over
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`the course of my education and career, form the bases for my opinions in this
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`declaration.
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`III. MATERIALS REVIEWED
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`5.
`
`I have reviewed and analyzed the parties’ papers and exhibits in this
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`proceeding, including the ’134 Patent (Ex-1001) and its prosecution history (Ex-
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`1004), AMD’s petition (Paper 1) and its associated exhibits, including the Wada
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`reference (Ex-1005) and the declaration of Dr. Baker (Ex-1002); Monterey’s
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`preliminary response and associated exhibits (Paper 9); AMD’s Reply to Monterey’s
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`preliminary response and associated exhibits (Paper 10); Monterey’s Sur-Reply
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`(Paper 11); the Board’s institution decision (Paper 13); and the transcript of Dr.
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`Baker’s February 12, 2021 deposition (Ex-2006). I have also reviewed and analyzed
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`the exhibits and documents cited in this declaration. Attached as Appendix B is a
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`complete list of the documents I have reviewed in preparing this report.
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`IV. EDUCATION AND EXPERIENCE
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`6.
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`Below is a summary of my education and experience. My CV, attached
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`as Exhibit 2005, records my education, experience, and publications in greater detail.
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`2
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0009
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`A. Overview
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`7.
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`I am currently an Adjunct Professor of Electrical and Computer
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`engineering at Rice University in Houston, Texas, and Managing Director of
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`Polymathic Consulting in Austin, Texas. I received my Bachelor of Electrical
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`Engineering from Rensselaer Polytechnic Institute in 1999, my Master of Science in
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`Electrical and Computer Engineering from Rice University in 2003, and my
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`Doctorate of Electrical and Computer Engineering from Rice University in 2007.
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`8. While at Rice University, I developed various computer architecture
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`designs for embedded and high performance systems. For example, from 1999 to
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`2003, I worked in the area of low-power computing, specifically focusing on
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`dynamic power management and performance of configurable memory systems,
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`including SRAM based caches. From 2002 to 2004, I developed Spinach, a computer
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`architecture design and modeling toolset, which models system components
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`common to all programmable computing environments, including memory systems,
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`microprocessors, interconnects, etc. From 2004 to 2009, I developed Spinach DSP-
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`FPGA, a modular and composable simulator design infrastructure for programmable
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`and reconfigurable embedded SOC architectures specifically targeting mobile, low-
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`power, and embedded and portable computing devices. From 2005 to 2009, I
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`developed and published a retargetable compiler infrastructure and hardware design
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`exploration toolkit for systems related to embedded computing technologies, which
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`3
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0010
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`is also used in the design space exploration of memory systems and related
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`technologies. Many of these tools have been used at United States universities in the
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`area of electrical and computer engineering research.
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`9.
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`In the late 1990s, I was a hardware and software developer at Vicarious
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`Visions in New York, developing third-party titles for Nintendo’s handheld
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`consoles, in addition to various hardware interfaces and software optimizations
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`related to the limited memory I/O and size. During my career, I have served as Chief
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`Technology Officer, often in co-founding roles.
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`10. From June 2006 to August 2007, I worked as the Technical Co-Founder
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`of Method Seven LLC in Boston, MA, working with high-performance software and
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`hardware systems architecture. I am currently a co-founder, co-inventor, and Chief
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`Technology Officer of Network Native, an Internet of Things technology company.
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`11.
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`I have held the position of Adjunct Professor at Rice University since
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`2009 and the position of Managing Director at Polymathic Consulting since 2011.
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`At Rice University, I instruct graduate-level curriculum in the areas of computer
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`architecture, hardware and software systems. I also advise on university research and
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`various design initiatives. At Polymathic Consulting, I work with a range of
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`technologists from early stage start-ups to Fortune 500 companies on similar
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`technologies.
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`4
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0011
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`12. From 2008 to 2009, I was Senior Engineer working in high-
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`performance compiler designs and next-generation microprocessors and
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`architectures at Freescale Semiconductor in Austin, TX. From November 2009 to
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`October 2011, I was Chief Architect, Senior Member Technical Staff, at Freescale
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`Semiconductor in Austin, TX (formerly Motorola), responsible for management of
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`technology, engineering roadmaps, design lead on software infrastructure, and next-
`
`generation microprocessor architectures for embedded computing. During my tenure
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`at Freescale Semiconductor, I was in charge of system developer tools for processor
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`design, both in the hardware and software spaces. These included tools used for the
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`programming of processors, simulation and design of processors, and related
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`technologies.
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`13.
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`I have previously worked for Texas Instruments’ Advanced
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`Architecture and Chip Technology division in Houston, Texas, in the areas of high-
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`performance mobile and embedded systems design at the hardware and systems
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`software level, specifically around heterogeneous computing, high-speed bus, and
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`interconnect technologies. I also have worked at Intel Corporation’s Microprocessor
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`Research Labs in the areas of computer architecture and compiler technologies.
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`14.
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`I am recognized as an expert in the field of computer architecture,
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`computer hardware and computer software systems as they relate to the subject
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`matter at hand. I am a member of the Institute of Electrical and Electronics Engineers
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`5
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0012
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`(IEEE) and have been a Program Committee member for the IEEE and ACM Design
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`Automation Conference from 2011 to the present, and have held the role of Program
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`Chair of Design Automation Conference in the area of Embedded Computing.
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`15. Over the past 15+ years, I have authored numerous peer-reviewed
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`publications, as well as engineering books in the area of computer hardware and
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`software design. Many of these incorporate technologies specific to the subject
`
`matter at hand, including memory system design, optimization for memory systems,
`
`and interconnect technology. These publications are disclosed in my curriculum
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`vitae, attached as Exhibit 2005. My curriculum vitae contains more information on
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`my background and experience, as well as the cases in which I have served as an
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`expert witness the past four years.
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`16.
`
`I am a named inventor on multiple pending United States patent
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`applications.
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`17.
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`I have previously served as an engineering consultant and testifying
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`witness on matters related to, and including, microprocessors, chip technology,
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`memory systems and interconnects.
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`B.
`
`18.
`
`Experience with Burst Mode Accesses In Memory Devices.
`
`I have extensive firsthand experience with the technology underlying
`
`the ’134 Patent. I have worked with various SRAM and DRAM technologies,
`
`including those with burst mode, since the late 1990s. My development of various
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`6
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0013
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`embedded systems work in the late 1990s include SRAM technologies and high
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`speed access of said systems. My work in the early 2000s was around the use of
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`configurable memory systems and caches comprised of SRAM technologies, and
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`the optimization of memory accesses to maximize CPU compute throughput. I have
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`designed memory system architectures, and system simulation and design
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`technologies both in my doctoral research and publications, as well as within my
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`various roles in industry going back to the early and mid 2000s.
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`V. LEGAL STANDARDS
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`19. Monterey’s attorneys have explained to me the legal standards that
`
`apply in this case. My understanding of those standards is stated below. I am not
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`an attorney and have no formal training in the law concerning patents, but I have
`
`used my understanding of the legal principles, as set forth below, in reaching my
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`opinions.
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`A. Burden of Proof
`
`20.
`
`I understand that in this proceeding, AMD has the burden of proving
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`that the challenged claims are unpatentable by a “preponderance of the evidence.” I
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`understand “preponderance of the evidence” to mean evidence sufficient to show
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`that a fact is more likely true than not true.
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`7
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0014
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`B. Anticipation and Obviousness
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`21.
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`I understand that for a patent claim to be patentable and valid it must
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`be, among other things, new and not obvious in light of knowledge that was publicly
`
`available before the invention. I understand that knowledge that was publicly
`
`available before the claimed invention is generally referred to as “prior art.”
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`22.
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`I understand that whether a patent claim is new and not obvious is
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`judged from the perspective of a “person of ordinary skill in the art.” I understand
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`that a person of ordinary skill in the art is presumed to know all prior art and is a
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`hypothetical person of ordinary creativity who can use common sense to solve
`
`problems. I describe a person of ordinary skill in the art in greater detail in Section
`
`VI below.
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`1.
`
`Anticipation
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`23.
`
`I understand that a prior art reference that demonstrates a patent claim
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`is not new is said to “anticipate” that claim. I understand that to anticipate a claim of
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`a patent, a single prior art reference must disclose, either expressly or inherently,
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`each “limitation” (or “element”) of that claim combined in the same way as recited
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`in the claim. I understand further that even if a prior art reference does not expressly
`
`spell out all of the limitations arranged or combined as in the claim, it can still
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`anticipate if a person of ordinary skill in the art, reading the reference, would at once
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`envisage the claimed arrangement or combination.
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`8
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0015
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`24.
`I understand that a limitation is disclosed inherently in a reference only
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`if it is necessarily present in the process or product described in the prior art
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`reference. That is, I understand that probabilities or possibilities are insufficient to
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`show that a prior art reference inherently discloses something beyond what it
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`discloses explicitly. However, I understand further that it is not required that a person
`
`of ordinary skill in the art recognize or appreciate the inherent feature at the time the
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`prior art was first known or used.
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`25.
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`I understand that for a reference to anticipate a claim, the reference must
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`be complete enough to enable a person of ordinary skill in the art to carry out the
`
`claimed invention.
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`2. Obviousness
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`26.
`
`I understand that a claim is invalid for “obviousness” if the differences
`
`between the claim and the prior art are such that the subject matter as a whole would
`
`have been obvious at the time the invention was made to a person of ordinary skill
`
`in the art to which the subject matter pertains at the time of the invention. I
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`understand that obviousness is a question of law based on underlying factual issues.
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`Those factual issues are: (1) the scope and content of the prior art; (2) differences
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`between the prior art and the inventions of the claims at issue; (3) the level of
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`ordinary skill in the art at the time the invention was made; and (4) whether objective
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`factors indicating obviousness or non-obviousness are present.
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`9
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0016
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`27.
`I understand that such objective factors, sometimes referred to as
`
`“objective indicia,” may include: (a) commercial success of products covered by the
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`patent claims; (b) a long-felt, but unmet, need for the invention; (c) skepticism by
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`others in the field; (d) failed attempts by others to make the invention or solve the
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`problem solved by the invention; (e) copying of the invention by others working in
`
`the field; (f) unexpected results achieved by the invention; and (g) the fact that the
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`patentee proceeded contrary to the accepted wisdom of the prior art. For the
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`objective factors to be relevant, I understand that the evidence relating to these
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`factors must have a connection or causal “nexus” to the subject matter as claimed.
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`28.
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`I understand that a claim is not invalid for obviousness unless every
`
`limitation of the claim would have been obvious to a person of ordinary skill in the
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`art (or anticipated) at the time of the invention.
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`29.
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`I understand that a claim is not obvious merely because each claim
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`element was known in the prior art. I also understand that, in assessing obviousness,
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`I should consider whether a reason existed that would have prompted a person of
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`ordinary skill in the art to combine the prior art elements in the way they are
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`combined in the patent claim. I understand an expansive and flexible approach
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`should be applied to determine whether there was an apparent reason to combine the
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`known elements in the fashion claimed by the patent at issue.
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`10
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0017
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`30.
`I understand that an obviousness case based on modifying or combining
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`one or more prior art references also requires the petitioner to show that a person of
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`ordinary skill in the art would have had a reasonable expectation of successfully
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`achieving the claimed invention.
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`31.
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`I understand that example reasons to combine or modify prior art
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`references that may support a conclusion of obviousness include combining prior art
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`elements according to known methods to yield predictable results; simple
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`substitution of one known element for another to obtain predictable results; use of a
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`known technique to improve similar techniques; combining elements in a way that
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`would be ‘obvious to try’ where there exists a finite number of identified, predictable
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`solutions and a reasonable expectation of success; design incentives or market forces
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`that would prompt variations of known work if those variations were predictable to
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`a person of ordinary skill in the art; a teaching, suggestion, or motivation in the prior
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`art to combine or modify prior art references to arrive at the claimed subject matter;
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`and optimization of a recognized result-effective variable by a person of ordinary
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`skill in the art if that optimization would be routine.
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`32.
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`I understand that there are also reasons that would prevent a person of
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`ordinary skill in the art from modifying or combing prior art references. Examples
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`of prior art references that a person of ordinary skill in the art would not combine or
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`modify to achieve the claimed invention include prior art references that “teach
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`11
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0018
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`

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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`away” (discourage or lead away) from one another or from the claimed invention;
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`prior art references whose combinations or modification would change the principle
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`of operation of either prior art reference; prior art references whose combination or
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`modification would render them inoperable or unsuitable for their intended purpose;
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`and prior art references whose combination or modification would destroy a key
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`objective of that prior art reference.
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`33.
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`I understand that in determining whether a person of ordinary skill in
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`the art would combine or modify prior art references, the entire contents of each
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`prior art reference must be considered, including parts of those references that would
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`suggest against the proposed combination or modification.
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`C.
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`34.
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`Independent Claims and Dependent Claims
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`I understand that patents have two types of claims: “independent
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`claims,” which do not refer to other claims in a patent, and “dependent claims,”
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`which refer to at least one other claim in a patent. I understand that a dependent
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`claim incorporates every limitation of the claim or claims to which it refers, or
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`“depends.” Thus, if a claim is not anticipated, then any claim that depends from that
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`claim is not anticipated either. And if a claim is not obvious, then any claim that
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`depends from that claim is not obvious either.
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`
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`12
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0019
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`D. Claim Construction
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`35.
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`I understand that the language of claims are interpreted, or “construed,”
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`in accordance with the plain and ordinary meaning of such claims as understood by
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`one of ordinary skill in the art in light of the patent’s specification and prosecution
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`history of the patent. I understand that when a patent explicitly defines language
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`used in the claims, that definition applies to the claims even if it varies from the plain
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`and ordinary meaning of the language.
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`36.
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`I understand that “intrinsic evidence” is the primary means by which
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`claim terms are interpreted. Intrinsic evidence includes the claims themselves; the
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`specification of the patent in which the claims appears; and the prosecution history
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`of the patent.
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`37.
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`I understand that, during the prosecution history of the patent, an
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`applicant for a patent may state that the claims do not cover a particular feature or
`
`embodiment, and that such statement, a “prosecution history disclaimer,” by an
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`applicant may limit the scope of the claim language. However, I also understand
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`that proving a disclaimer requires a showing of clear intent by the applicant to
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`redefine the claim language in order to overcome prior art, on the basis of a specific
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`claim element. Further, it is my understanding that a general description of the
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`invention is not sufficient to limit the claim language.
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`13
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`Patent Owner Monterey Research, LLC
`Exhibit 2004, 0020
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`38.
`I understand that a claim term should not be given a meaning that
`
`renders portions of the claim language meaningless or superfluous.
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`39.
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`I understand that “extrinsic evidence,” such as expert and inventor
`
`testimony, dictionaries, and learned treatises, can also inform the meaning of a claim
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`term. However, extrinsic evidence is less significant than the intrinsic evidence in
`
`determining the meaning of a claim term. Further, I understand that ext