US007948290B2
`
`US 7,948,290 B2
`(10) Patent No:
`a2) United States Patent
`Kato
`(45) Date of Patent:
`May 24, 2011
`
`
`(54) DIGITAL PLL DEVICE
`:
`.
`3
`Inventor:
`Syuji Kato, Osaka(JP)
`;
`(73) Assignee: Panasonic Corporation, Osaka (JP)
`
`(75)
`
`(*) Notice:
`
`(21) Appl. No.:
`
`Subject to any disclaimer, the termofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`12/439.644
`
`11/1998 Dent ossccccccsccccsssnen 332/127
`5,834,987 A *
`8/1999 Yanagiuchi
`5,945,856 A
`$970,110 A *® 10/1999 Li
`cecsssssccsssssssseeeessseee 377/48
`6.097.777 A
`8/2000 Tateishi et al.
`611470 A ®
`8/2000 Dufour ccccscccssesesse 331/17
`2/2001 Fallisgaard et al, was... 331/18
`6,188,290 BL*
`
`vee 33L/2
`6.333.678 BL*
`12/2001 Brownetal.
`..
`...rvrseoner 331/78
`6,650,193 B2* 11/2003 Endo et al.
`Scie BE
`DAS Manikews
`(Continued)
`FOREIGN PATENT DOCUMENTS
`1409490 A
`4/2003
`
`CN
`
`(22)
`
`PCTFiled:
`
`Jul. 8, 2008
`
`(Continued)
`
`(86)
`
`PCT No.:
`
`PCT/JP2008/001827
`
`OTHER PUBLICATIONS
`
`§ 371 (c)(1),
`(2), (4) Date: Mar. 2, 2009
`PCT Pub. No.: W02009/013860
`PCT Pub. Date: Jan. 29, 2009
`
`Prior Publication Data
`US 2010/0001773 Al
`Jan. 7, 2010
`
`Foreign Application Priority Data
`
`(87)
`
`(65)
`
`(30)
`
`Jal: 23; 2007
`
`(GB) vans200T 190405
`
`(51)
`
`Int. Cl.
`(2006.01)
`HO3L 7/06
`(52) US. C1 cesses 320/159; 327/150
`(58)
`Field of Classification Search ........................ None
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,813,005 A *
`5,028,887 A *
`5,265,081 A
`
`3/1989 Redigetal. uc. FO2/117
`7/1991 Gilmore .......cceereeeereere 331/18
`[1/1993 Shimizumeetal.
`
`High-Definition Multimedia Interface Specification Version |.3a,
`Nov. 10, 2006.
`
`(Continmed)
`Primary Examiner — Cassandra Cox
`(74) Attorney, Agent, or Firm — McDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`frequency-divides an input
`An input clock dividing unit
`clock, and an input clock multiplying unit frequency-multi-
`plies the input clock. An operationclock selecting unit selects
`the frequeney-divided clock when the input clock is fast and
`selects the frequency-multiplied clock when the input clock is
`slow, based on the frequency detection result of frequency
`detecting unit. The operationclockselecting unit then outputs
`the selected clock to a phase comparing unit as an operation
`clock. The phase comparing unit operates according to the
`frequency-divided or frequency-multiplied clock, and con-
`trols an oscillating unit so that the phase difference betweena
`reference signal and a comparison signal becomes zero, The
`phase of an output clock is thus caused to track the phase of
`the referencesignal.
`
`11 Claims, 7 Drawing Sheets
`
`INPUT
`
`CLOCK
`
`INPUT GLOCK
`MULTIPLYING
`UNIT
`
`OPERATION CLOCK
`
` 1
`
`[2
`
`REFERENCE
`
`
`SIGNAL n DIVIDING
`
`
`
`OSCILLATING
`UNIT
`UNIT
`
`
`
`
`
`COMPARISON
`SIGNAL
`
`m DIVIDING
`UNIT
`
`
`
`OUTPUT
`GLOCK
`
`Roku EX1040
`U.S. Patent No. 9,716,853
`
`Roku EX1040
`U.S. Patent No. 9,716,853
`
`

`

`US 7,948,290 B2
`Page 2
`
`FOREIGN PATENT DOCUMENTS
`U.S. PATENT DOCUMENTS
`10-224336
`8/1998
`JP
`Bl*
`5/2004 Welland etal. .........
`aa0s 455/260
`6,741,846
`2003-347933
`12/2003
`B2*
`6/2004 McCollum etal,
`JP
`6,753,711
`327/156
`
`2004-289557
`10/2004
`BL*
`4/2005 Hoetal.
`...........
`JP
`6,882,229
`33ULA
`
`2007-082001
`3/2007
`B2*
`5/2007 Yamamotoetal.
`7,215,165
`JP
`327/156
`2007-088898
`4/2007
`B2* 11/2007 Hino ow.
`7,301,414
`331/179=JP
`
`327/536
`7,312,649
`
`B2* 12/2007 Origasa et al.
`OTHER PUBLICATIONS
`B2*
`7/2008 Chienetal. ...
`375/316
`7,394,870
`7,436,264
`B2* 10/2008 Yu ou...
`» 331/17
`BL*
`3/2009 Erol...
`7,512,205
`
`375/376
`2001/0017573
`Al*
`§/2001 Fallisgaard et al.
`..........
`a S3L/18
`2006/017 1496
`Al
`§/2006 Nakamuta etal.
`2006/0176525
`Al*
`8/2006 Mizutaetal. ...........
`sen 358/474
`
`Japanese Notice of Reasons for Rejection, with English translation,
`issued in Japanese Patent Application No. 2008-55453, dated Jun.
`29, 2010.
`
`* cited by examiner
`
`

`

`U.S. Patent
`
`May24, 2011
`
`Sheet 1 of 7
`
`US 7,948,290 B2
`
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`

`

`U.S. Patent
`
`May24,2011
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`Sheet 2 of 7
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`US 7,948,290 B2
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`

`U.S. Patent
`
`May 24
`
`, 2011
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`Sheet 3 of 7
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`US 7,948,290 B2
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`U.S. Patent
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`May 24
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`, 2011
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`Sheet 4 of 7
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`US 7,948,290 B2
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`U.S. Patent
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`May 24
`
`, 2011
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`Sheet 5 of 7
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`US 7,948,290 B2
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`U.S. Patent
`
`May 24
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`2011
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`U.S. Patent
`
`May24, 2011
`
`Sheet 7 of 7
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`

`US 7,948,290 B2
`
`2
`signal is causedtotrack the phase ofthe referencesignal. By
`thus locking the output clock to (128xFs), Fs can be regen-
`erated by the sink device.
`1: High-Definition Multimedia
`Non-patent document
`Interface Specification Version |.3a
`
`DISCLOSURE OF THE INVENTION
`
`Problemsto be Solved by the Invention
`
`5
`
`10
`
`20
`
`5
`
`Whena transmitted clockis fast in the above conventional
`digital PLL device, an operation clock is fast, causing
`increase in circuit scale and significant increase in power
`consumption. Whenthe transmitted clockis slow,onthe other
`5 hand, the operation clock is slow, causing increase injitter
`and increase in tracking time.
`The transmitted clock has been increasingly becoming
`faster especially due to Deep Color defined in the HDMI
`specification, recent higher definition of image, andthelike.
`Undersuch circumstances, conventionaldigital PLL devices
`have been increasingly suffering from problems such as
`increased circuit scale and significantly increased power con-
`sumption.
`The conventional PLL devices thus have problems such as
`increased circuit
`scale,
`increased power consumption,
`increased jitter, and increased tracking time depending onthe
`transmitted clockrate.
`In view of the above problems,it is an object of the present
`invention to provide a digital PLL device having a structure
`capable ofsuppressing increase in circuit scale and increase
`in power consumption whena transmitted clockis fast, and to
`provide a digital PLL device having a structure capable of
`suppressing increase in jitter and increase in tracking time
`when a transmitted clock is slow.
`
`35
`
`Means for Solving the Problems
`
`1
`DIGITAL PLL DEVICE
`
`RELATED APPLICATIONS
`
`‘This application is the U.S. National Phase under 35 U.S.C.
`§371 of International Application No. PCT/JP2008/001827,
`filed on Jul. 8, 2008, which in turn claims the benefit of
`Japanese Application No. 2007-190405, filed on Jul. 23,
`2007, the disclosures of which Applications are incorporated
`by reference herein,
`
`TECHNICAL FIELD
`
`The present invention generally relates to a digital PLL
`device. More particularly, the present invention relates to a
`digital PLL device thatis used for, for example, regeneration
`of an audio clock froma clock transmitted througha digital
`interface such as IEEE 1394 and HDMI (High-Definition
`Multimedia Interface) used in a digital television and an AV
`amplifier.
`
`BACKGROUND ART
`
`Manydigital interfaces employ a system in which a param-
`eter is created by a transmitting party according to a prede-
`termined formula and a required audio clock is regenerated
`from a transmitted clock by using the parameter. As a typical
`structure ofthis system, a digital PLL is used byitself or in
`combination with an analog PLL.
`It has been commonin the art to use a transmitted clock as
`an operation clock of a digital PLL for regenerating a clock
`(e.g., see Non-patent document1).
`FIG. 7 is a block diagram showing a structure of a conven-
`tional digital PLL device.
`The conventional digital PLL device ofFIG.7 includes an
`n dividing unit 1, a phase comparingunit 2, an oscillating unit
`3, and an m dividing unit 4.
`As shownin FIG. 7,the ndividing unit 1 frequency-divides
`aclocktransmitted through a digital interface by n to produce
`a digital PLL reference signal. The phase comparing unit 2
`operates by using the transmitted clock as an operation clock.
`The phase comparing unit 2 obtains the phase difference
`betweenthe reference signal generated by the n dividing unit
`1 and a comparison signal generated by dividing an output
`clock by m in the m dividing unit 4, and outputs a control
`signal so as to reduce the phase difference. The oscillating
`unit 3 changes the output clock by the control signal received
`fromthe phase comparing unit 2. This operationis repeated as
`a feedback loop, whereby the phase of the output clock is
`caused totrack (lock to) the phase of the reference signal.
`For example, in an HDMIspecification, parameters N and
`CTSare prepared as parameters for regenerating an audio
`clock. These parameters are defined by the following for-
`mula:
`
`In order to achieve the above object, a digital PLL device
`according to one aspect of the present invention includes: an
`operation clock generating unit configured to output a fre-
`quency-divided or frequency-multiplied input clock as an
`operation clock; anndividing unit configured to frequency-
`divide an input clock by n to output a reference signal; a phase
`comparing unit configured to compare the reference signal
`5 with a comparison signal and output a control signal; an
`oscillating unit configured to changeanoscillation frequency
`ofan output clock according to the control signal: and an m
`dividing unit configured to frequency-divide the output clock
`by m to output the comparison signal.
`In the digital PLL device according to the above aspect of
`the presentinvention, the operation clock generating unitis an
`output clock dividing unit configuredto frequency-dividethe
`input clock and output the resultant clock as the operation
`clock.
`
`50
`
`55
`
`In this case, the n dividing unit frequency-divides the
`operation clock instead of the input clock by n to output the
`referencesignal, and the digital PLL device further includes
`aninput clock multiplying unit configured to frequency-mul-
`tiply anoutputofthe oscillating unit and outputthe resultant
`clock.
`In the digital PLL device according to the above aspect of
`the present invention,the operation clock generating unitis an
`input clock multiplying unit configured to frequency-multi-
`ply the input clock and output the resultant clock as the
`operation clock.
`In this case, the n dividing unit frequency-divides the
`operation clock instead ofthe input clock by n to output the
`
`CTS=(transmitted clackxN\/(128xF's)
`
`where F's (Sampling Frequency) indicates an audio clock.
`A source device as a transmitter determines the value of
`CTSby counting the numberoftransmitted clocks in each of 60
`the (128xFs/N) clocks. A sink device as a receiver frequency-
`divides the transmitted clock by CTS to generate a digital
`PLL reference signal. By repeating an operation of compar-
`ing the phase ofa comparison signal generated by frequency-
`dividing an outputsignal by N with the phase ofthe generated
`reference signal and controlling the output clock so that the
`phase difference becomes zero, the phase of the comparison
`
`

`

`US 7,948,290 B2
`
`4
`the low-speed operation, for example, can be suppressed by
`operating the digital PLL device based on a frequency-mul-
`tiplied transmitted clock.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Wa
`
`3
`reference signal, and the digital PLL device furtherincludes
`an output clock dividing unit configured to frequency-divide
`an output of the oscillating unit and output the resultant clock.
`In the digital PLL device according to the above aspectof
`the present invention, the operation clock generating unit
`further includes an input clock dividing unit configured to
`frequency-divide the input clock and output the resultant
`FIG, 1 is a block diagram showing a structure ofa digital
`clock, an input clock multiplying unit configured to fre-
`PLL device according to a first embodiment of the present
`invention;
`quency-multiply the input clock and output the resultant
`clock, and an operation clock selecting unit configured to
`FIG. 2 is a block diagram showing a structure of a digital
`select the output of the input clock dividing unit or the output
`PLL device according to a second embodimentofthe present
`invention;
`of the input clock multiplying unit and output the selected
`output as the operation clock.
`FIG, 3 is a block diagram showingastructure of a digital
`In this case, the digital PLLdevice further includesa fre-
`Fi
`PLL device according to a third embodimentofthe present
`quency detecting unit configured to detect a frequency of the
`invention:
`e
`input clock and output a frequency detectionresult, wherein
`‘IG. 4 is a block diagram showing astructure of a digital
`the operation clock selecting unit selects the output of the
`PLL device according to a fourth embodimentofthe present
`input clock dividing unit or the output of the input clock
`invention:
`multiplying unit based on the frequency detectionresult.
`IG. § is a block diagram showing a structure of a digital
`In the digital PLL device according to the aboveaspect of
`PLLdevice accordingtoa fifth embodimentofthe present
`the present invention, the n dividing unit frequency-divides
`invention;
`the operation clock from the operation clock selecting unit
`FIG. 6 is a block diagram showing a structure ofa digital
`instead ofthe input clock by nto output the referencesignal,
`PLL device according to a sixth embodimentofthe present
`and the digital PLL device further includes: an output clock
`invention; and
`"Ti
`multiplying unit configured to frequency-multiply an output
`IG. 7 is a block diagram showinga structure of a conven-
`of the oscillating unit and outputthe resultant clock; an output
`tional digital PLL device.
`clock dividing unit configured to frequency-divide the output
`of the oscillating unit and output the resultant clock; and an
`output clock selecting unit configured to select the output of
`the output clock multiplying unit or the output of the output
`clock dividing unit and output the selected output.
`In this case, the digital PLL device further includes a fre-
`quency detecting unit configured to detect a frequencyof the
`input clock and output a frequencydetectionresult, the opera-
`tion clock selecting unit selects the output of the input clock
`dividing unit or the output of the input clock multiplying unit
`based on the frequency detectionresult, and the output clock
`selecting unit selects the output of the output clock multiply-
`ing unit or the output ofthe output clock dividing unit based
`on the frequency detection result.
`In the digital PLL device according to the above aspectof
`the present invention,
`the phase comparing unit operates
`accordingto the operation clock.
`In the digital PLL device according to the above aspectof
`the presentinvention, the input clock is transmitted through a
`digital interface.
`In the digital PLL device according to the above aspect of
`the present invention, the digital interface is IEEE 1394 or
`HDMI.
`
`o
`
`20
`
`40
`
`45
`
`50
`
`DESCRIPTION OF THE REFERENCE
`NUMERALS
`
`1 n dividing unit
`2 phase comparingunit
`3 oscillating unit
`4 m dividingunit
`5 input clock dividing unit
`6 input clock multiplying unit
`7 operation clock selecting unit
`8 frequency detecting unit
`9 output clock multiplying unit
`10 output clock dividing unit
`11 outputclock selecting unit
`
`BEST MODE FOR CARRYING OUTTHE
`INVENTION
`
`Hereinafter, embodiments ofthe present invention will be
`described with reference to the accompanying drawings.
`
`First Embodiment
`
`Effects of the Invention
`
`the digital PLL device
`As has been described above,
`according to one aspectofthe present invention can reduce
`the circuit scale, power consumption,jitter, and tracking time
`regardless of the transmitted clock rate, as compared to con-
`ventional digital PLL devices.
`‘The transmitted clock rate has been rapidly increased due
`to, for example, an improved resolution resulting from Deep
`Colordefined by the HDMI specification or recentincrease in
`screensize ofdisplay devices. Accordingly, increasein circuit
`scale and increase in power consumption dueto the high-
`speed operation, for example, can be suppressed by operating
`the digital PLL device based on a frequency-divided fast
`transmitted clock.In the case where the high-speed operation
`of the transmitted clock is not required such as in low-end
`devices, increase in jitter and increase in tracking time due to
`
`FIG, 1 is a block diagram showing a structure ofa digital
`PLLdevice according to a first embodiment of the present
`invention.
`
`The digital PLL device according to thefirst embodiment
`of the present invention shown in FIG. 1 includes an n divid-
`ing unit 1, a phase comparing unit 2, an oscillating unit 3, an
`m dividing unit 4, and aninput clock dividing unit 5.
`Operation ofthe digital PLL device of the present embodi-
`ment having the above structure will now be described.
`As shownin FIG. 1, the n dividing unit 1 frequency-divides
`an input clock transmitted througha digital interface by n (n
`is a natural number) to generate a digital PLL reference sig-
`nal. The input clock dividing unit 5 frequency-divides the
`input clock and outputs the resultant clock to the phase com-
`paring unit 2 as an operation clock. The phase comparing unit
`2 operates according to the operation clock received fromthe
`input clock dividing unit 5. The phase comparing unit 2
`
`

`

`US 7,948,290 B2
`
`a
`obtains the phase difference between the reference signal
`generated by the n dividing unit 1 and a comparison signal
`generated by frequency-dividing an output clock by m(mis a
`natural number)in the m dividing unit 4, and outputs a control
`signal so that the phase difference becomeszero. The oscil-
`lating unit 3 changes the output clock by the control signal
`received from the phase comparing unit2.
`Provided that the input clock frequencyis x hertz and the
`output clock frequency is y hertz, the reference signal fre-
`quency is x/n hertz. Since the phase of the comparisonsignal
`tracks the phase ofthe referencesignal, the comparison signal
`frequency is also x/n hertz. The output clock frequency is
`therefore y=(xxm)/n hertz. A desired output clock is thus
`obtained.
`As has been described above, according to the digital PLL
`device of the first embodimentofthe present invention, the
`phase comparing unit 2 can be operated by using a frequency-
`divided input clock as an operation clock. This structure
`suppresses increase in circuit scale and increase in power
`consumption caused by high-speed operation due to a high-
`speed transmitted clock, as compared to conventional digital
`PLL devices in which the phase comparing unit 2 is operated
`by using an input clock directly as an operation clock.
`Note that
`the input clock and the frequency dividing
`parameters m and n may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`
`cannot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. Examples ofsuch
`a digital interface include audiotransmission of IEEE 1394 or
`HDMI.
`
`Second Embodiment
`
`20
`
`)
`
`40
`
`FIG. 2 is a block diagram showing a structure ofa digital
`PLL device according to a second embodimentofthe present
`invention.
`The digital PLL device according to the second embodi-
`mentof the present invention shownin FIG. 2 includes an n
`dividing unit 1, a phase comparing unit 2, an oscillating unit
`3, an mdividingunit 4, and an input clock multiplyingunit 6.
`Note that, as compared to the structure of the digital PLL
`device ofthefirst embodiment shown in FIG. 1, the structure
`of the digital PLL device of the present embodimentis char-
`acterized by including the input clock multiplying unit 6
`configured to frequency-multiply an input clock instead of 45
`the input clock dividing unit 5 ofthe first embodiment con-
`figured to frequency-divide an input clock.
`Operationof the digital PLL device of the present embodi-
`ment having the abovestructure will now be described.
`As shownin FIG, 2, then dividing unit 1 frequency-divides
`an input clock transmitted through a digital interface by n to
`generate a digital PLLreferencesignal. The input clock mul-
`tiplying unit 6 frequency-multiplies the input clock and out-
`puts the resultant clock to the phase comparing unit 2 as an
`operation clock. The phase comparingunit 2 operates accord-
`ing to the operation clock received fromthe input clock mul-
`tiplying unit 6. The phase comparing unit 2 obtains the phase
`difference between the reference signal generated by the n
`dividing unit 1 and a comparison signal generated by fre-
`quency-dividing an output clock by m in the mdividing unit
`4, and outputs a control signal so that the phase difference
`becomeszero. The oscillating unit 3 changes the output clock
`by the control signal received from the phase comparing unit
`
`)
`
`Provided that the input clock frequency is x hertz and the
`output clock frequency is y hertz, the reference signal fre-
`quencyis x/n hertz. Since the phase of the comparisonsignal
`
`6
`tracks the phase ofthe reference signal, the comparisonsignal
`frequency is also x/n hertz. The output clock frequency is
`therefore y=(xxm)/n hertz. A desired output clock is thus
`obtained.
`As has been described above, according to the digital PLL
`device ofthe second embodimentofthe present invention,the
`phase comparing unit 2 canbe operated by using a frequency-
`multiplied input clock as an operation clock. This structure
`suppresses increase in jitter and increase in tracking time
`caused by low-speed operation due to a low-speed transmit-
`ted clock, as compared to conventional digital PLLdevicesin
`which the phase comparing unit 2 is operated by using an
`input clock directly as an operation clock.
`Note that the input clock and the frequency dividing
`parameters m and n may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`cannot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. Examples ofsuch
`a digital interface include audio transmission of IEEE 1394 or
`HDMI.
`
`Third Embodiment
`
`FIG. 3 is a block diagram showing a structure of a digital
`PLL device according to a third embodimentofthe present
`invention.
`The digital PLL device accordingtothe third embodiment
`of the present invention shownin FIG. 3 includes an n divid-
`ing unit 1, a phase comparing unit 2, anoscillating unit 3, an
`m dividing unit 4, an input clock dividing unit 5, an input
`clock multiplying unit 6, an operation clock selecting unit 7,
`and a frequency detecting unit 8.
`As compared tothestructures ofthe digital PLL devices of
`thefirst and second embodiments shownin FIGS. 1 and 2, the
`
`structure ofthe digital PLL device ofthe present embodiment
`is characterized by includingthe input clock dividing unit 5 of
`the first embodiment configured to frequency-divide an input
`clock and the input clock multiplying unit 6 of the second
`embodiment configured to frequency-multiply an input
`clock, and characterized by further including the operation
`clock selecting unit 7 configured to select
`the clock fre-
`quency-divided bythe input clock dividing unit § or the clock
`frequency-multiplied by the input clock multiplying unit 6
`and output the selected clock as an operation clock. The
`digital PLL device of the third embodiment may further
`include the frequency detecting unit 8 configuredto detect an
`input clock frequency and output the detection result to the
`operation clock selecting unit 7 so that the operation clock
`selecting unit 7 can select an optimal operation clock.
`The digital PLL device of the third embodiment of the
`present invention therefore has the effects of both thefirst and
`second embodiments described above. More specifically, as
`compared to conventional digital PLL devices in which the
`phase comparing unit 2 is operated by using an input clock
`directly as an operation clock, the digital PLL device of the
`third embodiment suppresses increase in circuit scale and
`increase in power consumption caused by high-speed opera-
`tion due to a high-speed transmitted clock and also suppresses
`increase in jitter and increase in tracking time caused by
`low-speed operation due to a low-speed transmitted clock.
`Moreover, since the digital PLLdevice ofthe third embodi-
`ment
`includes the frequency detecting unit 8, an optimal
`operation clock can be selected according to the operation
`speed, based on the input clock frequency. The digital PLL
`device of the third embodiment can therefore operate ratio-
`nally.
`
`

`

`US 7,948,290 B2
`
`7
`the input clock and the frequency dividing
`Note that
`parameters m and n may be transmitted through a digital
`interface, This structure is effective in the case where a clock
`cannot be transmitted directly but a clock synchronized with
`a transmitting party needsto be generated. Examples ofsuch
`adigital interface include audio transmission of IEEE 1394 or
`HDMI.
`
`Fourth Embodiment
`
`FIG, 4 is a block diagram showinga structure ofa digital
`PLL device according to a fourth embodiment of the present
`invention.
`The digital PLL device according to the fourth embodi-
`mentof the present invention shownin FIG. 4 includes an n
`dividing unit 1, a phase comparing unit 2, an oscillating unit
`3, an m dividing unit 4, an input clock dividing unit 5, and an
`output clock multiplying unit 9.
`Operation ofthe digital PLL device of the present embodi-
`ment having the above structure will now be described.
`As shown in FIG. 4, the input clock dividing unit 5 fre-
`quency-divides an input clock transmitted througha digital
`interface and outputsthe resultant clock to the phase compar-
`ing unit 2 and also to the n dividing unit 1 as an operation
`clock. The n dividing unit 1 frequency-divides the clock
`received from the input clock dividing unit 5 by n to generate
`a digital PLL reference signal. The phase comparing unit 2
`operates according to the operation clock received from the
`input clock dividing unit 5. The phase comparing unit 2
`obtains the phase difference between the reference signal
`generated by the n dividing unit 1 and a comparison signal
`generated by frequency-dividing anoutput clock by min the
`m dividing unit 4, and outputs a control signal so that the
`phase difference becomes zero. The oscillating unit 3 changes
`the output clock by the control signal received from the phase
`comparing unit 2. The output clock multiplying unit 9 fre-
`quency-multiplies the clock received from the oscillating unit
`3 and outputs the resultant clock.
`Provided that the input clock frequency is x hertz, the
`output clock frequency is y hertz, and the frequency-dividing
`factor of the input clock dividing unit 5 is a, the reference
`signal frequency is x/(axn) hertz. Since the phase of the
`comparison signal tracks the phase ofthe reference signal, the
`comparisonsignal frequency is also x/(axn) hertz. The output
`clock frequency of the oscillating unit 3 is therefore y'=(xx
`m)/(axn) hertz. A desired output clock is thus obtained by
`using the value a as a frequency-multiplying factor ofthe
`output clock multiplying unit 9.
`As has been described above, according to the digital PLL
`device of the fourth embodimentofthe present invention, the
`phase comparing unit 2 can be operated by using a frequency-
`divided input clock as an operation clock. This structure
`suppresses increase in circuit scale and increase in power
`consumption caused by high-speed operation dueto a high-
`speed transmitted clock, as comparedto conventional digital
`PLL devices in whichthe phase comparing unit 2 is operated
`by using an input clock directly as an operation clock.
`Note that
`the input clock and the frequency dividing
`parameters m and n may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`cannot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. Examples ofsuch
`a digital interface include audio transmission of IEEE 1394 or
`HDMI.
`
`20
`
`30
`
`35
`
`8
`The digital PLL device according to the fifth embodiment
`ofthe present invention shown in FIG. 5 includes an n divid-
`ing unit 1, a phase comparing unit2, an oscillating unit 3, an
`m dividing unit 4, an input clock multiplying unit 6, and an
`output clock dividing unit 10, Note that, as compared to the
`structure of the digital PLL device ofthe fourth embodiment
`shownin FIG. 4, the structure ofthe digital PLL device ofthe
`present embodimentts characterized by including the input
`clock multiplying unit 6 configured to frequency-multiply an
`input clock instead of the input clock dividing unit 5 config-
`ured to frequency-divide an input clock in the fourth embodi-
`ment, and by including the output clock dividing unit 10
`configured to frequency-divide a clock received from the
`oscillating unit 3 and output the resultant clock instead of the
`output clock multiplying unit 9 configured to frequency-mul-
`tiply a clock received from theoscillating unit 3 in the fourth
`embodiment.
`Operation ofthe digital PLL device ofthe present embodi-
`ment having the above structure will now be described.
`As shown in FIG. 5, the input clock multiplying unit 6
`frequency-multiplies an input clock transmitted through a
`digital interface and outputs the resultant clock to the phase
`comparing unit 2 and also to the n dividing unit 1 as an
`operation clock. The n dividing unit 1 frequency-divides the
`clock received fromthe input clock multiplying unit 6 by nto
`generatea digital PLL reference signal. The phase comparing
`unit 2 operates according to the operation clockreceived from
`the input clock multiplying unit 6. The phase comparing unit
`2 obtains the phase difference betweenthe reference signal
`generated by the n dividing unit 1 and a comparison signal
`generated by frequency-dividing an output clock by min the
`m dividing unit 4, and outputs a control signal so that the
`phase difference becomes zero. The oscillating unit 3 changes
`the output clock by the control signal received fromthe phase
`comparing unit 2. The output clock dividing unit 10 fre-
`quency-dividesthe clock received from theoscillating unit 3
`and outputs the resultant clock.
`Provided that the input clock frequency is x hertz, the
`output clock frequencyis y hertz, and the frequency-multi-
`plying factor of the input clock multiplying unit 6 1s b, the
`referencesignal frequencyis (xxb)/n hertz. Since the phase of
`the comparisonsignaltracks the phase ofthe reference signal,
`the comparison signal frequency is also (xxb)/n hertz. The
`output clock frequency of the oscillating unit 3 is therefore
`y'=(xxbxm)/n hertz. A desired output clock is thus obtained
`by using a frequency-dividing factor b in the output clock
`5 dividing unit 10.
`As has beendescribed above, accordingto the digital PLL
`device ofthe fifth embodimentofthe present invention, the
`phase comparing unit 2 canbe operated by using a frequency-
`multiplied input clock as an operation clock. This structure
`suppresses increase in jitter and increase in tracking time
`caused by low-speed operation due to a low-speed transmit-
`ted clock, as compared to conventionaldigital PLLdevicesin
`which the phase comparing unit 2 is operated by using an
`input clock directly as an operation clock.
`Note that
`the input clock and the frequency dividing
`parameters m and n may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`cannot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. Examplesof such
`a digital interface include audio transmission of IEEE 1394 or
`HDMI.
`
`50
`
`55
`
`60
`
`Fifth Embodiment
`
`Sixth Embodiment
`
`
`FIG. 5