DECLARATION OF MIKE STRAWN
`
`1.
`
`My name is Mike Strawn.
`
`I am over the age of twenty-one years, of sound mind,
`
`and capable of making the statements set forth in this Declaration. I am competent to testify about
`
`the matters set forth herein. All the facts and statements contained herein are within my personal
`
`knowledge.
`
`2.
`
`I visited the University of Houston’s MD. Anderson Library (“Anderson Library”)
`
`located at 4333 University Drive, Houston, Texas 27204 on January 22, 2020 and scanned certain
`
`pages from Proceedings 1997 IEEE Multi-Chip Module Conference (“IMCMC”).
`
`3.
`
`Anderson Library’s call number for IMCMC is TKTSM .13238 1997. Anderson
`
`Library had one copy of .IMCMC, which was indexed and shelved as indicated by Anderson
`
`Library’s online catalog, a true and correct copy of which is attached as Appendix A. In the copy
`
`of IMCMC, I scanned the cover, the table of contents, the “Date Due” slip, and the article titled
`
`“Delay .Modet'sfor MCM Interconnects When Response is Non-Monotone” by Andrew B. Kahng,
`
`Kei, Masuko, and Sudhakar Muddu. A true and correct copy of these pages from IMCMC is
`
`attached as Appendix B.
`
`4.
`
`I declare under penalty of perjury that the foregoing is true and correct.
`
`Executed on January 22, 2020 in Houston, Texas, U.S.A.
`
`'
`
`3/
`
`C
`-) ..
`
`Mike Strawn
`
`Qualcomm Incorporated
`Exhibit 1036
`
`Page 1 of 22
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`Qualcomm Incorporated
`Exhibit 1036
`Page 1 of 22
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`

`

`APPENDIX A
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`APPENDIX A
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`Format: x, 171 pages : illustrations ; 29 cm.
`Source: Alma
`
`Identifier: LC: 96079698; ISBN: 0818677899 (softbound); ISBN: 0780339037 (casebound); OCLC:
`(OCoLC)36524697
`
`Availability and location:
`
`University of Houston:
`
`Available:
`
`Creator: IEEE Multi-Chip Module Conference (1997 : Santa Cruz, Calif.)
`Contributor: IEEE Computer Society.
`Subject: Multichip modules (Microelectronics) -- Congresses; Thin films; Neural networks (Computer
`science); CAD/CAM systems; Optoelectronic devices
`Genre: Congresses.
`Contents: Session 1. Flip-chip I -- Session II. Mixed signal MCMs -- Session III. MCM design and CAD
`-- Session IV: Panel: The best road to integration? Single chip or multi-chip? -- Session V: Interconnect
`analysis and simulation -- Session VI. Flip-chip II -- Session VII. Test, technology and infrastructure --
`Session VIII: Optical MCMs -- Session IX: Wrap up panel -- Author index.
`Other title: 1997 IEEE Multi-Chip Module Conference.; IEEE Multi-Chip Module Conference.
`Publisher: Los Alamitos, Calif : IEEE Computer Society Press
`Creation Date: @1997
`
`  
`ÿ

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`0 UH/MD Anderson Library Anderson General Collection TK7874 .I3238 1997
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`

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`APPENDIX B
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`APPENDIX B
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`Page 4 of 22
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`Lmu flufmnncu TI:
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`Proceedings
`
`-
`
`1997
`
`IEEE
`
`Multi-Chip Module
`Conference
`
`
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`Page 8 of 22
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`Proceedings
`
`1997
`
`IEEE
`
`Multi-Chip Module
`Conference
`
`February 4 — 5, 1997
`
`Santa Cruz, California
`
`Sponsored by
`
`IEEE Computer Society
`
`IEEE Circuits and Systems Society
`IEEE Components, Packaging, and
`Manufacturing Technology Society
`IEEE Electron Devices Society
`
`
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`IEEE Computer Society Press
`
`Los Alamitos, California
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`Tokyo
`.
`. Brussels
`Washington
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`

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`
`
`IEEE Computer Society Press
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`Copyright © 1997 by The Institute of Electrical and Electronics Engineers, Inc.
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`

`

`Table of Contents
`
`1997 IEEE Multi-Chip Module Conference
`
`Foreword ................................................................................................................................... viii
`
`Technical Program Committee .............................................................................................. ix
`
`EESSION 1: Flip-Chip I
`Moderator: Don Bouldin, University of Tennessee
`
`|
`
`Area I/O Flip-Chip Packaging to Minimize Interconnect length ............................................... 2
`RJ. Lamar, RB. Brown,
`M. Nanua, and TD. Strong
`
`Determination of Area-Array Bond Pitch for Optimum
`MCM Systems: A Case Study ...................................................................................................... 8
`P. Dehkordi, K. Ramamurthi,
`D. Bouldin, and H. Davidson
`
`A Flip-Chip Implementation of the Data Encryption Standard (DES)..................................... ‘13
`T. Schafier, A. Glaser,
`S. Rae, and P. Frarizon
`
`SESSION 11: Mixed Signal MOMS
`
`Moderator: Peter Iuey, University of Sheflield
`
`
`
`SESSION III: MGM Design and CAD
`Moderator: Wayne Dai, University of California, Santa Cruz
`High Speed 110 Buffer for MGM ................................................................................................. 52
`SJ. Yang, T.C. Chang, Iii-W. Chien, ED. Wang,
`T.J. Gabam, KL. Tai, and RC. Frye
`Wire Length and Width Bound Generation for High-Speed
`MCM and PCB Designs ...................................................................... ....................................... 5
`H. Chen, E. Shragowitz, and J. Lee
`
`An S-Bit 2.5 Gigasample AID Converter Multichip Module for All—Digital Radar
`Receiver for AN/APS 145 Radar on Navy EZ-C Airborne Early Warning Aircraft ................ 20
`
`BL. Thompson, M.J. Degerstrom, WL. Walters, ME. Vickberg,
`P.J. Riemer, ELH. Amundsen, and BK. Gilbert
`
`The Impact of Miniaturization and Passive Component Integration
`in Emerging MGM Applications ................................................................................................ 27
`Y.L. Low and RC. Frye
`
`High Q Inductors for MGM-Si Technology ................................................................................. 33
`N. Klemmer and J. Hartung
`Investigations on Novel Coaxial Transmission Line Structures on MGM-L ............................ 38
`A. Thiei, C. Habiger, and G. Troster
`Precision Embedded Thin Film Resistors for Multichip Modules {MGM-D} ............................ 44
`
`0-31. Lin, EA. Logan, and D. Tuckerman
`
`Page 12 of 22
`
`Page 12 of 22
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`

`

`An Adaptive Wide-Area Design Process Manager for Collaborative
`Multichi‘p Module Design ............................................. . ............................................................ 83
`AM. Madni and C. C. Mancini
`
`Multiscale Thermal Design of MCMs with High Resolution Unstructured
`Adaptive Simulation Tools .................................. . ..................................................................... 73
`
`A.J. Przekwas, Y. Jiang, and Z.Q. Tan
`
`Design of an MCM FFT Processor . ................................ . ............................................................ 83
`R. G. Rozier and RE. Kiamilev
`
`A New Timing-Driven Multilayer MGM/IO Routing Algorithm ............................................... 89
`
`D. Wang and ES. Kuh
`
`SESSION IV: Panel: The Best Road to Integration? Single Chip or Multi—Chi p?
`
`Moderator: Thad Gabaro, Bell Laboratories, Lucent Technologies
`
`Organizers: S. Leanheart, S. Muddhu, P. Franzen, and T. Gabon;
`
`Panel Members: Not finalized at the time ofpublication.
`
`This panel will address the contentious question as to which is the best approach to
`integrating different silicon functions — system on a chip, or system on a MultiChip Module?
`A system typically integrates logic, analog, SRAM, DRAM, RF, MEMS, etc. Does an MCM
`allow you to use the best technology for each of these? Or does the MCM test cost and
`relatively limited interchip connectivity compel you to an integrated process? This panel will
`debate these and other issues.
`
`SESSION V: Interconnect Analysis and Simulation
`
`_
`
`Moderator: S. Muddfiu, Silicon Graphics
`
`Fast Extraction of the Capacitance ‘M'at‘rix of Multilayered Multiconductor
`Interconnects Using the Method of Lines ................................................................................. 98
`X. Jiang, K. Wu, W. Hong, and W. W. -M. Dai
`" Time-Domain Simulation for Lossy Interconnects Employing
`Modified Characteristic Method
`
`L. Xin and L. Zheng-Fan
`Delay Models for MGM Interconnects when Response is Non-Monotone............................... 102
`AB. Kahng, K. Masuko, and S. Muddu
`S Parameter-Based Experimental Modeling of High Q MGM Inductor
`with Exponential Gradient Learning Algorithm ....................................................................
`J. Zhao, W. Dai, RC. Frye. and KL. Tm"
`Modeling the Frequency-Dependant Parameters of High-Speed
`Interconnects: A Neural Network Approach .............................. .
`A. Veluswami, M.S. Nakhla, and Q.-J. Zhang
`
`...........................................
`
`108
`
`114
`
`SESSION VI: Flip-Chip II
`Moderator? Peter Ivey, Universtty ofSheflield
`Intrinsic Area Array 105: What, Why, and How? ....................................................................
`P. Dehkordi, C. Tan, and D. Bouldin
`
`120
`
`“i
`
`Page 13 0f22
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`

`
`
`CAD Tools for AreawDistI-ibuted I/O Pad Packaging ................................................................ 125
`R. Farbarik, X. Liu, M. Rossman,
`P. Parakh, T. Basso, and R. Brown
`
`Flexible Manufacturing of Multichip Modules for Flip Chip ICs ............................................ 130
`I. Yee, B. Miracky, J. Reed, 8. Lunceford,
`M. Wang, D. Cobb, and G. Caldwell
`
`Prototype Devechpment of Flip Chip MCMs ............................................................................. 133
`
`W. Hansford, J. Peltier, P. Franzen,
`S. Lipa, and J. Schaefier
`
`{SESSION VI]: Test, Technology and Infrastructure
`Moderator: Chung Ho, Micromodule Systems
`
`I
`
`Low Cost Test of MCMs Using Testable Die Carriers ............................................................. 138
`
`K. Sasidhar, A. Chatterjee, and M. Swaminathan
`
`Strategies and Structures for Test Access in Mixed-Signal MCMs ........................................ 144
`M. Katoozi, H. Kutz, M. Sam, and S. Huynh
`
`‘ Europractice MCM Service
`H. Hentzell
`
`Comparative Cost Analysis for SmartSubstrate MGM Systems 150
`
`H. Werk mann and B. Hofflinger
`
`SESSION VIII: Optical MCMs
`
`Moderator: Paul Kohl, Georgia Tech
`
`Switched Optical Transmission: Exploration of Trade-offs
`between Packaging Options .................................................................................................... 158
`
`B. Kaminska, Ch. Roy, G. Fortin, and E. Sokolowska
`
`Design of 103 for Flip-Chip Integration with Optoelectronic Device Arrays .......................... 163
`
`F Kiamileu, R. Rozier, A. Krishnamoorthy, J. Rieve,
`C. Hull, R. Farbarik, R. Oettei, and G. Aplin
`
`SESSION 1X: Wrap Up Panel
`
`Organizer and Moderator: Steve Leanheart, GTE
`
`This panel will focus on what was learned at MCMC ’97 and perspectives for the future.
`
`Author Index ........................................................................................................................... 171
`
`"‘ Paper not received in time for publication in proceedings.
`
`Page 14 of 22
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`vii
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`
`
`Delay Models for MCM Interconnects
`When Response is Non-monotone*
`
`Andrew B. Kahng, Kei Masuko
`UCLA Computer Science Department
`Los Angeles, CA 90095-1596
`abk©cs.ucla.edu, masuko©cs.ucla.edu
`
`Sudhakar Muddu
`
`MIPS Technologies, Silicon Graphics, Inc.
`Mountain View, CA 94039
`
`muddu©mti.sgi.com
`
`Abstract
`
`Elmore delay has been extensively used for intercon-
`nect delay estimation because its simplicity of evalua-
`tion makes it appropriate for layout design. However,
`since Elmore delay does not take into account the effect
`of inductance, the discrepancy between actual delay and
`Elmore delay becomes si nificant for long RLC transmis-
`sion lines, such as for M M and PCB interconnects. We
`describe a simple two-pole based analytic delay model
`that estimates arbitrary threshold delays for RLC lines
`when the response is non—monotone; our model is far
`more accurate than the Elmore model. We also describe
`an application of our model for controlling response un— '
`dershoot/overshoot and for the reduction of interconnect
`delay through constraints on the moments.
`
`I
`
`Introduction
`
`Recently, accurate estimation of interconnect thresh-
`olddelays and rise times has become essential
`to the
`desagn of high-speed systems. Many interconnect delay
`models have been advocated; these are classified roughly
`into Simulation based models and closed form analytb
`ca] models. Simulation methods such as SPICE give the
`most accurate insight into arbitrary interconnect struc-
`tures. but are computationally expensive. Faster meth-
`ods based on moment matching techniques are proposed
`In [13, 1d, 15. 17]. but are still
`too expensive to be
`used during layout Optimization. Thus, Elmore delay
`[2]. a first order analytical approximation of delav un—
`der step input, has been the most widelv used model for
`performance-driven layout synthesis.
`.
`Recently. a number of analytical delay formulas have
`been proposed for interconnect delay based on the first
`few moments of the response under step and ramp input
`{5. 4. 10. ll. 18]. The authors of [5] use Elmore delay
`as an upperbound for the 50% threshold delay for RC
`[Interconnection lines under arbitrary input waveforms.
`rah: Vigork ol' [4] gives lower and upper bounds for the
`50cy'pthnpu}: rlcsponse; their (Single-pole) delay model for
`Fliiiorerdifihilidgliggfhcan be obtained by applying the
`.
`’
`c ramp input res onse.
`pigments Work has presented analytical delay mgdldlslbii
`.
`notone response under step and ramp inputs based
`'Pnrt‘all
`I
`_v supported by NSF AMP-9257982. ABK is currently
`t“.
`siting Scientist
`'
`{on sabbatical leave) at Cadence Design Systems.
`In;
`
`on first and second moments {10, ll]. Quite recently. [IS]
`have used the first
`three moments to accurately com-
`pute two poles of the impulse response. Note that all
`of these approaches assume that. the response is mono
`tone (or overdamped) in deriving their respective delay
`models. Howevar. for long lines with sufficient inductive
`impedance the response will he nonsmonotone.
`For RLC lines, which are the necessary representation
`of interconnects whose inductive impedance cannot be
`neglected [8} Elmore and other firsleorder delay models
`cannot accurately estimate signal delay because they are
`independent of inductance. To illustrate the effect olm-
`ductive impedance on the response, we consider a 2-porl
`model for an interconnect driven by a step inputw1th
`finite source impedance. Figure 1 compares the RC and
`RLC line responses computed by SPICE3e: 90% thresh-
`old delay is 288 ps for the RLCT‘ model, but is 358115
`for the RC model. Elmore delay. which does not depend
`on line inductance, will yield the same delay estimated
`386 pa for both the RC and the RLC cases. This in-
`accuracy can be harmful for current performance-drivel]
`routing methods which try to optimize interconnect seg-
`ment lengths and widths (as well as drivers and buffers-l-
`A non-monotone Hie. underdampcdl VOILE-Se response
`oscillates before setting to a steady state Vfilue- SUCh a
`response occurs when the ratio ofinductive impedance ‘0
`resistance exceeds a certain threshold in an interconnect
`linc. MCM substrate interconnects have smaller (inter
`resistance. and inductive impedance greater than res]:
`tive impedance as a consequence of greater Widths an.
`lengths comparcd to their on-chip \vLSI counterpart;
`the voltage response for such interconnects tends to ic
`nonmonotone. Consequently, the effect, Of Induc‘flncg;
`more evident
`in MCM interconnects. To address the In
`ficiencies of thr- Elmore model. this paper Elves a Simp I
`inter-
`yet reasonahlv accurate, analytical delay mOdEI for
`c,-
`connect lincs—which are inductive (in. RLC Hamish;-
`sion lines) and whose voltage response Is not mono;nal
`cally increasing. Our proposed model car‘. 85mm“ Sliiol
`delay for non-monotone I‘eSPOUS'E at alblimry thrl‘sana-
`voltages. Recently,
`[10] proposed a similar set
`(13.35?
`lyrical delay models. but these are restricted 1-0 “ime”,
`ofa monotone voltage response. Prelin‘llflar." ngerl 27‘}?
`tal results show that. our delay estimates are EV‘lhmléw.
`OfSPlCHcomputcd delays (for most cases Within ch as
`while Elmore delay estimates can dificr b! as mliricfh’
`“33% from the SPICE-computed delays- We also
`,
`
`
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`
`
`
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`
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`0-8186-7789-91'97 $10.00 © 1997 lEEE
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`

`bk are called the coefficients of the transfer function and
`are directly related to the moments of the transfer func—
`tion [10] Expanding the transfer function into a Maclau-
`rin series of 5 around 5 = 0 leads to an infinite series
`and to compute the response the series is truncated to
`desired order. We model the source as a resistance R;
`and the load as capacitance C
`.
`.
`‘
`L- For a two- ol
`the transfer function is aPPmXimate-d as
`P 9 model
`
`I
`
`Hm z
`
`1+b15+5353
`
`with coefficients
`
`
`b1 3 R50+ RsCL + R; + RC'L
`.
`2
`q
`b2 : 5532+ Rsl‘fCCi. + (Rci- + R’C‘CL
`L66
`‘
`Z
`24
`6
`+-2‘ + LC;-
`
`{2)
`
`
`
`Figure 2: 2-port mode! ofa distributed RLC line with
`source impedance 25 and load impedance Zr.
`
`When the input at the source is modeled as a step
`waveform, the output response in the transform domain
`is Vanda) : 1:“ H(s). The corresponding time domain
`response using the two-pole model is
`
` s s
`"(U = V0 1-”?e"'+
`l
`‘ig - 51
`51 -— 5!
`
`r'“
`
`(3)
`
`-blilgif—ib,
`.
`2b;
`where 51.2 =
`The condition for the response to be non-monotone is
`for the poles to be complex. Le... bf filling 0 {as noted
`earlier, this corresponds to the inductive impedance ex-
`ceeding a certain value). By writing the‘poles as 5.3 =
`—o :i: .75.
`the non-monotone time domain response he-
`comes
`
`(4)
`
`ult} = it [I a #‘Wc-M ”mm: +pi
`4t -t _
`_
`3%]. p _. fun
`(g)
`where a = fit; 6 2
`ponse first reaches the saturation
`Notice that the res
`15.1; over the intervalt E [0. 71}
`voltage V9 at time! =
`the derivative of the response M!) is positive. taking;-
`spouse is a continuous non-decreasmg function 0 t.
`e
`wish to compute the threshold delay when the response
`
`_1
`
` 1—.-
`“ —
`_
`
`'5' ‘
`.1. —
`I! c
`u- -
`u. -
`
`RLC Handel
`\/
`/
`’
`
`RC Mme]
`
`~
`_
`—.
`.-
`
`_
`
`Iflv-t
`
`f:
`
`jiF
`
`I“ -
`I. '*
`
`If
`L__l
`”-
`
`an
`
`moo
`
`°‘°
`
`ll.-
`
`I-
`
`'ri-nie"
`
`Figure 1: Comparison of HSPICE responses at the
`end of an interconnect
`line driven by a step input
`and terminated with a capacitive load, with the line
`represented using both RC and RLC 2-port models.
`flu: 99% threshold delay is 288 178 for the HLC' model.
`and 3.38 ps for the RC model. The driVer resistance is
`710:0 Q and the load capacitance at the end of the iiiie
`is 2.0 pF. The line parameters are r : 0.075 Q/iim.
`f_=Q.123 pH/pin, c = 8.8 fF/flm; the length of the
`line is 400 pm.
`
`discuss an approach to reduce the threshold delav by
`controlling the overshoot of the voltage response.
`'This
`translates into a condition between the first and. second
`pluments of the interconnect transfer function, which are
`uncuons of driver and interconnect parameters.
`SEER; rgmdmnder of this paper is organized as follows.
`model
`S
`escribes delay computation using our new
`lowin Isnecillm'l 3_expiains minimisation of delay by al-
`suit E
`ringing. Section 4 gives experimentai re—
`13
`s. and Section 0 states our conclusions.
`
`2 New Delay Model for Interconnects
`in :liirdi-liIEPhCity' we consider a single interconnect line
`'Plar [flodglrehponse and delay models. We develop our
`“Ellicienrfl as; a liflt‘t-lon of first and second momentsfor
`delav mode}: ”if transfer function: note that the same
`values 0f arbiim.
`ii .aPPlIEd t0 the corresponding moment
`0fthe transfer rid” interconnect trees. "the denominator
`with source a (inimon- ofa Slugle RLC lnLeI‘C'Ot‘ineCt‘line
`from ABCD n
`oad impedance (Figure 2) is obtained
`Parameters 1] as
`
`His]
`
`i 1
`
`__
`.
`1
`l(1 + gfhtoshwh) + (sf + ggisinhwh)
`i
`________________
`I+bls+5232+...+bg5k+...
`“he!
`.
`a __
`l'” + 508:: is the propagation constant and
`“
`e
`20 = FE:l;lL-
`..c
`Is the characteristic impedance: r : flit :
`pc : i" are resist
`'
`.
`311681 Inductance. and capacnance per
`.
`unii ]
`811th and h is the length of the line. The variables
`
`(1)
`
`Fe 16 0f22.
`
`
`
`103
`
`Page 16 of 22
`
`Page 16 of 22
`
`

`

`
` 1
`2
`first crosses some given threshold voltage, e.g.. at which
`a3 _
`35(UB—LB)2 [UB (31“ +962_3c3-5:1+&"]
`
`‘
`'
`that the
`the logic state changes. Thus, we can assume
`+UBLB(46C1 — 4462 — 74C: - 4464 +46%)
`threshold delay is bounded by the range [0. 1"—-3].
`(The
`
`+L82(3c1 — 5c2 fl 3C3 + ch +3lc5)]
`:I.
`reach we
`line for approximating response over a spec-
`ifi‘dil range isgquite general, in the sense that it canfbe
`
`3
`up
`used to compute threshold delay for the response wrt iin
`"FWBIPF fl )(vu. — 1)
`
`anv range of interest.) We can further reduce the tlp~
`pei- bound of the range as follows. Rearranging (3) For
`
`e2p(—aLB]sin(,flLB)
`a given threshold voltage um wrth corresponding delay
`
`'
`'
`"it al
`,
`”me in (in other words. 1ml : f), we have
`
`= =
`
`C]
`
`exp (—MIAM—Z) m (w)4
`c3 = exp (-EEPQLL'E) sin (MUS;- LBl)
`C4 = exp (_w) sin (Wilt/734+ LHl)
`
`
`
`
`
`C5 :
`
`exp(—oUB)sin(fiUB)
`
`-1 13(1‘ Ural
`(
`a2+l32)
`
`Solving (6) with respect to 1' and subtracting p/fi from
`r yields the threshold delay time
`
`_
`-t12— tin—40a
`in
`= ————-——2a-1”hp/n
`m,
`Note that the twopole approximation assumes that the
`response at the load end of the line begins from t = 0.
`However,
`for interconnects where time of flight. T; =
`vLC, is non-negligible. the response remains zero until
`t = 71'}. Hence, we estimate a given threshold delay as
`the maximum of time of flight and the delay estimate
`from (7), i.e., maleme]. We can estimate the risetlme
`between tw0 threshold voltages as the difference of the
`respective threshold delay estimates.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a.“
`
`‘
`
`_
`‘
`
`“of3 + fizsifllmrn + P)
`n1 - m)
`
`.‘iinco r‘”'" 2 l.
`
`i
`.‘
`"Til
`
`it +
`[h
`
`Pl
`
`in,
`
`[3(1 "— UNI)
`> —---——
`02+}?
`_,
`
`ir—p
`l
`.
`{3 —-Esrn
`
`S
`
`l'sing a new time variable r that shifts the time t”. as
`r = I”. +p/fi, we obtain the bound on r
`
`M‘3 S 1' S
`
`(bra/£3
`
`where: z sin‘ll’jizifl). Rewriting t by using 1’ and
`rearranging (4) yields
`
`5"" v sinlfir} +
`
`6
`¢=W
`
`a
`-—-B£-)(vu. -1).= U
`
`(5)
`
`The delay at a given threshold voltage on, cannot be
`calculated directly from this equation,
`so we adopt
`the approach of approximating e‘“ t 5111087) with a
`degree-two polynomial
`[7].
`Specifically, we approxi—
`mate Ill”) = {cpl—otmlsinldtm} over
`the interval
`t = [£13. [I B] nsrng a vector space representation. where
`
`Us ‘2'
`
`LB ".5!
`
`upper bound of the approximation interval
`
`lower bound of the approximation interval
`
`The Gramm-Schmidt technique [7] yields the following
`approximation of 8"” t sinfflr) over
`'
`l B] by a degree-two polynomial (see [lgffdi-msggilstB‘
`2
`“IT +a3r+a3=0
`
`(5)
`
`Where
`
`"l
`
`(lg
`
`=
`
`:———3____ 2
`rlUB- LBFi Cl " C? " 2Ca - 64 + 2C5)
`: _____]'____
`35(UB _. LBF [Um-108m -l- 2662 -l- 8063 + 5464
`~3265l + LBl—5261 + 5462 + 8063 -l- 2664 - 10805 )]
`
`—-——-l("§_é] maybe
`Finally, because the range 1' E [2.
`too large for
`the Gramm-Schmidt procedure to effect
`tively approximate the response with a Single degree
`two Polynomial. Hence. we divide this range m t.“
`to improve the approximation of the response function
`6"" t sinmr). Since sinlfir) is increasing in the run;
`,_
`[0. .755]. we divide the original range into the two {BREE}
`5
`[LBLUBI] 2 [5g] and 1L32.UB2]_= [rt—“l-
`We choose the proper range by comparing tile-$112:
`old voltage u”. to the response value at timet - zfi'
`' "
`1
`2
`2
`). This rarefied”
`vlfi) = 1‘ JEJ‘Zexm-g—(p —% .
`ut waveforms-
`can be extended to other (6.5., ramp) 1rIP
`3 Constraint on Moments for Contl’
`Undershoot/Overshoot
`[n this section. we illustrate how our S‘lm
`Old delay model can yield Simple analytic ddressihe
`for interconnect synthesis, Specificalllfi.we a
`Question of finding interconnect and driver
`for optimum delay with comrolled ringing-
`Simple RLC line driven by a gate. With .‘5
`driver impedance and CL being the. 193d map
`the end of the line. The characteristic Im
`the driVEr and
`ffijgé,
`Ideally.
`
`ol oi
`
`being the
`r
`
`Page 17 of22 I
`
`line is given by Zn :
`
`
`
`Page 17 of 22
`
`Page 17 of 22
`
`

`

`1
`m f
`
`mshold
`
`Delay in!)
`
`Length
`
`l
`
`Table 1: Threshold delay estimates at various thresh-
`olds for non—monotone response under HSPICE. Elmore
`and our New models. Source resistance is 10 f2 and load
`capacitance is 2 pF.
`
`4 Experimental Results
`eye models by simulating vari-
`We evaluate the ab
`lines With different source/load
`ous RLC interconnect
`impedances and different
`input
`rise times. We con-
`sider
`typical
`interconnect parameters encountered in
`ts 3. For all cases.
`the interconnect
`MCM interconnec
`resistance.
`inductance and capacitance per length are
`r = 3.0 x 10’49/pmi f = 0.433 pHipm and c = 9.]
`he length of the interconnect
`in 3000 to SDOOOpm. We also vary the
`d the driver resistance from 2 to SpF
`load capacitance an
`‘
`to 708?. respectively. We compute delays at
`thresholds ranging from 10% to 90% from the response
`at the load min the HSPICE simulator {see Tables ]
`-
`4 for results wit
`four of the configurations}. For cases
`is non-monotone the difference be-
`when the response
`tween delays from HSPICE and delays from our model
`is always less than 27% despite this large range of in-
`mation always underesti-
`stances. The Elmore approxi hresholdis are small. and
`mates delays when the voltage L
`_
`can either overestimate or underestimate when the volt-
`age thresholds are large. Overall. Elmore delay differs
`from HSPICE delay by up to 100%, When the response
`is monotone (i.e., with real poles), the minimum differ-
`ence between our new model delay and HSPlCE delay is
`23%.
`
`are adjusted such that Z5 matches Z
`response at the end of the line is critic:
`Iiiic parameters
`and the voltage
`Howm-er,
`if the driver impedance Z is
`rally damped.
`just smaller than the characteristic impedance of the line
`(he volLage response will have a small amount of ringin i
`iliis can be advantageous in that the threshold delay wigll
`.lvcrrase [19].; The problem with ringing is that it can
`cause false swrtching if the voltage response drops back
`below the threshold: hence. the advantages of riri
`in ca
`be exploited only if the iiiaximiam oscillation (ogersghoori
`or iinderslioot) is bounded such that false switchin doe
`[lotIOCCllL _We now develop an analvtical equatiog that:
`achieves this control in terms of coefficients of the trans
`fer function. Additional context for our discussio
`I
`lie found in {10]
`i
`h
`n may
`The voltage response for ringing is given by
`
`”cull” = in [l —
`
`02+‘ifi'32 _
`-—-——‘-
`d
`e
`
`'
`"‘SmliiHm
`
`where
`: [an-1 g
`and Ulfilersho
`, (a)' To find the Peaks of overshoot
`,
`at in the response, we 53;
`the derivative
`twill to zero. yielding fit - mr with ri
`,-
`.
`_
`= 1.3.5,...1'
`zlntgflio‘ots and n = 2: 4, 6.
`for undershoots. The firgi
`.rs out occurs at time T1 = 21/13, and the value of
`the undershoot is
`
`do
`
`-aT1
`
`Vile
`
`‘1 .,
`_
`1+(E)-szn(m‘1+p) : Hie—"TR
`
`t for a
`The constrain
`he Obtained as
`
`'
`Swen Percentage undershoot U", can
`
`For
`‘
`-
`andefiangaglth 3% undershoot. we have on, 2 0.05%
`3
`.
`. We can express a and 6 in terms of
`cv_
`bl
`coeffi
`lents of the transfer function, i.e.,
`Wm-
`Therefom
`
`'C
`
`bi
`
`is
`_)2 __ l.
`
`l “i”(a
`0745? 2:30:35? 511me lfiquatlon reduces to
`is]:
`is case can be obtaiiiedo(seer?i0l)) asdelay estimate for
`
`'
`With 5% u
`
`rid
`
`.
`
`T08
`
`1'66
`
`252
`
`«452 ‘7.b1
`
`213th
`
`Simil my. f0 ’ -
`I fit overshoot“ the relation between the co-
`s b
`._
`’3flltients ‘1
`2
`plate is Ti) 9 I: T 26-9152 and a correSporiding delay esti—
`or fist
`.
`.
`()1. As expected, the delay increases
`»
`ersh
`-
`.
`Tong und
`-
`34‘ increases
`00" requirement. and in general the
`rlel
`1e aho~
`E ”1 the response is su presscd
`if ringin
`'
`-
`[19]."
`ii
`Bishoo‘teigonshalnb between a: and 5 t5 reduce
`”‘3 liiid
`.VriiodEl in éhe Fijponse could be applied with
`”Ie (loin
`tree Symhesiguahon (7} to perform delay-driven
`routing
`
`105
`
`
`
`Page 18 of 22
`
`Page 18 of 22
`
`

`

`RC Trees with Generalized Input Signals”. doll/{Egg
`Design Automation Conference. J UN: 1993
`[6] M.A. Horowitz. “Timing Models for M05 Circuits“
`PhD Thesis. Stanford University. Jan. 1984.
`'
`[7] Th. V. Ilromadka II et at, The Best Apprortmntwn
`Method an Introduction, Lecture Notes in En
`smearing
`27. Springer—Verlag. 1987.
`
`“Signal Degradation
`[B] C. C. Huang and L. L. Wu,
`Through Module Pins in VLSI Packagingfi [BM 1‘ HM
`and Dev. 31(4). July 1937, pp. 439-493.
`‘
`[9] S. Lin and ES. Kuh. “Transient Simulation ofLossy
`Interconnect”. Proc. 29th .4 CM/IEEE Design Automa-
`tion Conf.. June 1992. pp.31—86.
`
`“An Analytical Dela)-
`[l0] AB. Kahng and S. Muddu.
`Model
`for RLC Interconnects”.
`IEEE International
`Symposium on Circurts and Systems. May 1996.v0l.1\’.
`pp.‘237-240.
`
`[11] A. B. Kahng. K. Masuko and S. Muddu. “Analytical
`Delay Models for VLSI Interconnects Under Rampln‘
`put". lEEE/AL-Ull lntl. Conf. on CAD. Nov. 1996.
`
`[12] AB. Kahng. K. Masulro. and S. Muddu. “Delay Models
`for Interconnects Under Non- Monotone and Monotone
`
`Response". UCLA CS Dept. TH- 960010.Nov.1995.
`
`
`
`
`
`
`
`
`
`
`4-
`
`"—136“
`firm-"MI
`Ital—ml
`
`
`" _——I
`
`mam—I
`
`
`
`mum—_I
`urn-ml
`mm-
`some
`”IE-l
`
`m- —_I
`
`firm—“I
`
`urn-ml
`
`Int-m 743 ml
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Table 2: Threshold delay estimates at various thresh—
`olds tor non-monotone response under HSPICE, Elmore
`and our New models. Source resistance is 30 Q and load
`capacitance is 3 pF.
`
`5 Conclusions
`
`We have developed a simple two-pole based analytical
`delay mod