United States Patent (19)
`Lindenmeier et al.
`
`(54 SIGNAL DIVERSITY ARRANGEMENT FOR
`MOBILE RECEPTION
`75 Inventors: Karl-Heinz G. Lindenmeier, Planegg;
`Gerhard Flachenecker, Ottobrunn,
`both of Fed. Rep. of Germany
`73 Assignee: U.S. Philips Corporation, New York,
`N.Y.
`(21) Appl. No.: 127,827
`(22
`Filed:
`Dec. 1, 1987
`(30)
`Foreign Application Priority Data
`Dec. 2, 1986 DE Fed. Rep. of Germany ....... 36.41109
`(51l Int. Cl." ............................................. HO4B 11/16
`(52 U.S. Cl. .................................... 455/133; 455/135;
`455/275; 455/278
`58 Field of Search ................................ 455/132-135,
`455/50, 272,275,276, 278, 296, 303; 37.5/100;
`370/95, 100, 110.1
`References Cited
`U.S. PATENT DOCUMENTS
`4,498,885 2/1985 Namiki ................................ 455/278
`4,512,034 4/1985 Greenstein et al. .....
`... 455/278
`4,578,819 3/1986 Shimizu ...............
`... 455/135
`4,736,455 4/1988 Matsue et al. ...
`... 455/278
`4,742,568 5/1988 Furuya ............
`... 455/135
`4,756,023 7/1988 Kojima ................................ 455/134
`OTHER PUBLICATIONS
`"NTG Fachbrichte Band 72”, p. 241, 3/80.
`Primary Examiner-Robert L. Griffin
`Assistant Examiner-Curtis Kuntz
`
`(56)
`
`11
`45
`
`Patent Number:
`Date of Patent:
`
`4,876,743
`Oct. 24, 1989
`
`Attorney, Agent, or Firm-David R. Treacy
`57
`ABSTRACT
`The invention relates to a signal diversity arrangement
`for a mobile reception, comprising a receiver and a
`diversity processor, which receives the input signals
`and applies a different input signal to the receiver when
`interference occurs. The diversity processor comprises
`an interference detector operating in the analog mode
`and a comparator, to whose first input is applied the
`output signal of the interference detector and to whose
`senond input is applied a suitably set voltage V1. The
`comparator shows on its output the occurence of inter
`ference by way of a binary signal when the threshold
`voltage V at the second input is exceeded. No less than
`one integrator is available having a discharging time
`constant, to whose input is applied a signal derived from
`the interference signal and whose time of integration is
`equal to the switching interval of one of the input sig
`nals and whose output signal is added to either the
`interference signal at the first comparator input such
`that when the interference is increased the total voltage
`at the first input of the comparator is increased also, or
`the output signal is applied to the second comparator
`input such that the threshold voltage is lowered when
`the interference rises. In the case of a series of integra
`tors whose inputs each receive a signal derived from the
`interference signal of the associated input signal, the
`output signals of these integrators are each time applied
`to one of the comparator inputs and the threshold volt
`age V is changed each time in accordance with the
`interference signal during the switching interval.
`12 Claims, 4 Drawing Sheets
`
`RECEIVER
`
`
`
`
`
`
`
`
`
`
`
`SIGNA
`SELECTION
`
`INTERFERENCE
`RECOGNITION
`
`".
`
`DIVERSITY
`PROCESSOR
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 1 of 11
`
`

`

`U.S. Patent Oct. 24, 1989
`
`Sheet 1 of 4
`
`4.876,743
`
`RECEIVER
`
`DVERSY /
`U PEGESSR1
`
`FG.1
`
`
`
`5
`
`INTERFERENCE
`DETECTOR
`
`5
`
`-COMPARATOR
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 2 of 11
`
`

`

`U.S. Patent Oct. 24, 1989
`21
`5
`9
`
`Sheet 2 of 4
`6
`
`4,876,743
`
`STORASE
`St UU
`
`
`
`
`
`INTEGRATOR
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 3 of 11
`
`

`

`U.S. Patent Oct. 24, 1989
`
`Sheet 3 of 4
`
`4.876,743
`
`STORAGE
`SELECTOR
`
`INTEGRATOR
`
`
`
`
`
`
`
`COMPARATOR
`
`FIG.7
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 4 of 11
`
`

`

`U.S. Patent Oct. 24, 1989
`
`Sheet 4 of 4
`
`4,876,743
`
`
`
`STORAGE
`SELECTOR
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 5 of 11
`
`

`

`1.
`
`SIGNAL DIVERSITY ARRANGEMENT FOR
`MOBILE RECEPTION
`
`5
`
`O
`
`20
`
`BACKGROUND OF THE INVENTION
`The invention relates to a signal diversity receiving
`system for mobile reception of frequency modulated
`singals, comprising a receiver and a diversity processor,
`which receives the input signals and applies a different
`one of the input signals to the receiver when interfer
`ence occurs on the signal currently being used.
`Such an arrangementis, for example, known from the
`NTG-Fachberichte Band 72 (VDE Verlag), p. 241,
`picture 5b, as a scanning diversity combiner. In this case
`the diversity combiner selects one signal out of the two
`15
`input signals offered, while that signal exceeds a specific
`predetermined voltage threshold Umin. Falling short of
`this level is considered by the combiner to be interfer
`ence. The interference detector operates in a digital
`mode, and in the case of the combiner shown comprises
`a comparator having a threshold voltage At the output
`of the deletion signal is developed moving the switch
`into the other position.
`Such a system has the disadvantage that when inter
`ference occurs as defined above, the switch is moved
`25
`into the other position each time, regardless of the sig
`nal quality history of the signal applied to the signal
`input. For example, if the voltage at one of the two
`signal inputs has been essentially lower on average than
`the voltage at the other input over along period of time,
`30
`and then for a short period of time at the signal input
`with a larger signal on average the value falls below
`Unin, a switching through to the input with the signal
`which is worse on average will take place, although
`most probably a still worse signal is available there. In
`such a case the system often switches back and forth
`between the signal inputs at a very high switching rate.
`This leads to an additional disturbing element in the
`system, and a consequent degradation of the quality of
`the signal switched through to the receiver. When uti
`40
`lizing diversity aerial selection there will be consequent
`disturbing noise in the clock rate at the switching fre
`quency on reception, which is often considered to be
`switching noise.
`SUMMARY OF THE INVENTION
`Therefore, it is an object of the invention with a sig
`nal diversity arrangement (1) for mobile reception to
`switch through to the receiver a signal input having a
`less disturbed signal on average rather than a signal
`50
`input having a more disturbed signal on average.
`This object is achieved in accordance with the inven
`tion in that the diversity processor (3) comprises an
`interference detector (5) oprating in the analog mode
`and a comparator (6), whose first input (7) receives the
`55
`output signal of the interference detector and to whose
`second input (8) a suitably set voltage (V1) is applied
`and the comparator (6) shows on its output by way of a
`binary signal (10) the occurrence of interference when
`the threshold voltage V at the second input (8) is ex
`ceeded by the interference signal (9). One integrator
`(11) is available having a discharging time constant, to a
`signal (12, 20) derived from the interference signal is
`applied to at least one integrator (11) having a discharg
`ing time constant, whose time of integration is equal to
`65
`the switching interval of one of the input signals (2).
`The integrator output signal is added either to the inter
`ference signal at the first comparator input (7) such that
`
`4,876,743
`2
`when the interference signal is increased the total volt
`age at this first input (7) of the comparator (6) is in
`creased also, or the output signal at the second compar
`ator input (8) is superimposed on the voltage V1, so that
`the threshold voltage V is lowered when the interfer
`ence signal is increased or in the case of a series of
`integrators (11), whose inputs each receive a signal (12,
`20) derived from the interference signal of the associ
`ated input signal (2), the output signals of these integra
`tors (11) are each time applied to one of the two com
`parator inputs (7, 8) and, if necessary, the threshold
`voltage V is changed each time in accordance with the
`interference signal during the switching interval.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a signal diversity ar
`rangement for mobile reception according to the inven
`tion comprising a diversity processor with an interfer
`ence recognition circuit, a signal selecting circuit, a
`signal selector and a subsequent receiver.
`FIG. 2 is a block diagram of an interference recogni
`tion circuit comprising an interference detector operat
`ing in the analog mode, a subsequent integrator with a
`discharging time constant, and a comparator to whose
`signal inverting second input the output signal of the
`integrator is applied.
`FIG. 3 is a similar diagram of an interference recogni
`tion circuit, comprising an interference detector operat
`ing in the analog mode, a subsequent integrator with a
`discharging time constant, and a comparator to whose
`signal noninverting first input the output signal of the
`integrator is positively applied.
`FIG. 4 is a diagram of a set of integrators, which are
`assigned to the relevant input signals and to which the
`interference signal occurring during this switch
`through time is applied through a multiplexer, the out
`put signal of the set being passed on to the comparator
`through the storage selector.
`FIG. 5 is a diagram of an integrator having a reset
`value adjustable to a specific initial value.
`FIG. 6 is a diagram of a series of integrators assigned
`to the relevant input signals, to which has been applied
`through a multiplexer, for example, a time-constant
`voltage value, the output signals of the series being
`applied to the comparator through the storage selector.
`FIG. 7 is a diagram of an interference frequency
`detector, comprising a PLL circuit, a sampleand-hold
`evaluating means, and a monoflop which is triggered by
`the binary switching signal, the output voltage of the
`sample-and-hold section being used to control the dis
`charging time constant in the integrator.
`FIG. 8 is a diagram of a series of integrators having a
`switchable time constant for the charging and discharg
`ing processes switching over being effected, for exam
`ple by means of bridging switches.
`FIG. 9 is a diagram of an integrator having switch
`able time constants, comprising an operational amplifier
`and a controllable switch, which is switched in line with
`the rate of the address output signal.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`FIG. 1 shows a singal diversity arrangement for mo
`bile reception in accordance with the invention, com
`prising a diversity processor (3) having an interference
`recognition circuit (4) according to the invention, a
`signal selecting circuit (14), a signal selector (16) and a
`
`35
`
`45
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 6 of 11
`
`

`

`10
`
`5
`
`4,876,743
`3
`4.
`placed by the arrangement of FIG. 2 having the input
`subsequent receiver (17). NTG-Fachberichte, Volume
`72 (VDE-Verlag), page 241, FIG. 5b discloses in the
`signal (21) and the binary output signal (10), an advanta
`scanning diversity combiner a comparator with a volt
`geous integration is obtained, in that when a signal input
`age threshold inlieu of the interference recognition
`(2) to which the receiver is switched receives a dis
`circuit (4) and the signal selecting circuit (14). In the
`turbed input signal, the threshold voltage (8) is lowered
`more rapidly on account of the integration against time
`above combiner this voltage threshold is a timeinvariant
`with respect to the switching time of this input accord
`value. In FIG. 1 of the present invention the interfer
`ing as the signal quality at the relevant input has de
`ence recognition circuit (4) also has a threshold and
`when this threshold is passed the binary output signal
`graded. Thus, if the interference signal (9) occurs, an
`advanced switching operation is brought about by
`(10) will indicate the presence of interference. This
`binary signal switches the signal selecting circuit (14)
`means of the comparator, and a signal more disturbed
`one step further, so that when the principle is applied in
`on average is switched through to the receiver for a
`the most general sense, a binary code word (15) will be
`shorter period of time if the instantaneous interference
`generated at the output of the signal selecting circuit
`remains the same. The interference audible in the re
`(14), which code word brings the signal selector (16) in
`ceiver is substantially proportional to both the instanta
`a desired position and thus a defined signal (2) is
`neous interference and the switching time of the inter
`switched through to the receiver (17). According to the
`ference signal. When reducing the switching interval in
`inventive idea the interference can have different ori
`accordance with the measure of the invention the audi
`gins. It can consist of, for example, adjacent channel
`ble interference is reduced also. Thus, a signal having a
`better quality on average is switched through for a
`interference, common-channel interference, noise jam
`20
`ming, intermodulation interference or multi-path recep
`longer period of time than a signal of a poorer quality.
`tion interference owing to large differences in delay
`This leads in the case of a plurality of inputs, to a distri
`bution of the average switching times according to the
`time.
`signal qualities available at the separate inputs.
`The invention is based on the fact that in the interfer
`ence recognition circuit (4), whose block diagram is
`FIG. 3 shows an interference recognition circuit (4)
`shown in FIG. 2 by way of example, an interference
`according to the invention, comprising an interference
`detector (5) operating in the analog mode is available,
`detector (5) operating in the analog mode with a subse
`quent integrator (11) having a discharging time con
`indicating the aforedescribed interference by means of
`an anaalog signal on its output (9). To initiate a switch
`stant, and a comparator (6). With this circuit an opera
`ing operation this output signal (9) of the interference
`tion similar to that of the arrangement of FIG. 2 can be
`30
`detector (5) can also be compared to a threshold voltage
`achieved in an advantageously simple manner, in that
`(8). The switching operation is initiated when the ana
`the non-inverting output signal (13) of the integrator
`log voltage (9), applied to a first input (7) of a compara
`(11) is superposed on the interference signal (9) at the
`tor (6), exceeds the threshold voltage V on its second
`output of the interference detector (5) operating in the
`input (8). Subsequently, a binary signal (10) to trigger
`analog mode with the aid of a summing circuit as shown
`35
`the signal selecting circuit (14) is available on the output
`in FIG. 3, and this signal is applied to the first input (7)
`(10) of the comparator (6). In an embodiment of the
`of the comparator (6). The threshold voltage V1 having
`innovative idea the threshold voltage (8) is suitably
`the aforedescribed features is then available in a similar
`arranged such, that this threshold voltage is lowered
`mode at the second input (8) of this comparator. Thus,
`when there is a poor average signal quality. Thus, it is
`the output signal (13) of the integrator is not used for
`achieved that a smaller interference signal (9) already
`the formation of the threshold voltage V at the second
`results in the arrangement being switched through by
`input of the comparator (6), but the value for the aver
`the binary signal (10). This signal quality is averaged by
`age signal quality is additively superposed on the actual
`means of an integrator (11), to whose input is applied a
`interference signal (9). Resetting the integrator can be
`signal (12) corresponding to the interference, which
`effected in a similar way to that of the arrangement in
`45
`integrator is returned to a defined initial value after each
`FIG. 2.
`switching operation.
`FIG. 4 shows a series of integrators (11) which are
`In a particularly simple manner the integrator can be
`assigned to the relevant input signal (2) and which re
`constituted by a capacitor. A discharging time constant
`ceive through a multiplexer (18) the signal (12) occuring
`72 (for example, with a resistor arranged in parallel) is
`during each switching interval and derived from the
`assigned to the integrating capacitor, in order not to
`interference. The output signals of the integrators (11)
`allow the threshold (8) to be lowered too much by the
`are applied as signals (13) to one of the two inputs of the
`signals (12) representing the interference and integrated
`comparator (6) through a storage selector (19), which is
`in time with respect to the past. The resetting of the
`driven in synchronism with the multiplexer (18), so that
`integrator (11) is effected in synchronism with the
`each time the output signal of the integrator is available
`switching through by the binary address output signal
`at the input of the comparator which is assigned to the
`(15). Thus, the output signal (13) represents the average
`corresponding input signal (2). In this arrangement
`value against time of the interference in the signal(21)
`there is no resetting of the integrators (11) in line with
`during the switching interval of a signal. When the
`the rate at which the interference recognition circuit is
`threshold voltage (8) is lowered further, the recognition
`switched through.
`of interference in the signal (21) via the interference
`This arrangement, shown in FIG. 4, is introduced
`signal (9) becomes more sensitive.
`into an advantageous further embodiment of the inven
`In an advantageous manner the signal (13) is superim
`tion in lieu of the integrator (11) either as shown in FIG.
`posed on a partial threshold voltage V1 in a summing
`2 or in FIG. 3. The input signal is the signal (12) derived
`circuit as shown in FIG. 2. This partial threshold volt
`from the interference, the output signal (13) is either
`65
`age V1 generally represents the instantaneous value of
`superposed on the interference signal (9) as shown in
`the signal quality averaged over all input signals (2). If
`FIG. 3 or, as shown in FIG. 2, used to form the thresh
`the interference recognition circuit (4) in FIG. 1 is re
`old voltage V at the second input (8) of the comparator.
`
`50
`
`25
`
`55
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 7 of 11
`
`

`

`15
`
`10
`
`4,876,743
`5
`6
`In these arrangements a single integrator (11) is assigned
`(12) derived from the interference. The sample and hold
`to each input signal (2), which integrator is charged
`circuit, which is clocked by means of a monoflop (45)
`during each switching interval of the relevant signal
`triggered by a binary switching signal (10), is instrumen
`input (2) via the signal (12) derived from the interfer
`tal in producing at the output the signal (39) with which
`ence of the interference detector (5) operating in the
`the time constants of the integrator are controlled in the
`analog mode. When switching the relevant input signal
`manner described in the Claim 3.
`(2) through, the integrator is switched on with the aid of
`If the discharging time constant (T2) of the integra
`a multiplexer (18) controlled in synchronism with ad
`tors (11) is too large, owing to the effect of the storage,
`dress output signal (15). When averaging by means of a
`the signal quality qhich was previously available at a
`capacitor and a resistor the above embodiments can be
`specific input is valued too strongly compared to the
`used. The separate output signals of the integrators (11)
`actual signal quality. If the charging time constant is too
`are alternately switched through to the common output
`large, the storages will start operating too slowly.
`by means of a storage selector (19) controlled in syn
`Therefore,in a particularly advantageous embodiment
`chronism with the multiplexer (18). In contradistinction
`of the invention each integrator (11), as shown in FIG.
`to the interference recognition circuit with only a single
`8, receives a suitably chosen charging time constant T1
`integrator, the interference recognition circuit shown in
`and a discharging time constant T2 which can be ad
`FIG. 4 operates with a series of integrators (11), which
`justed separately. This is effected in a manner known
`are not reset when a switching through takes place and
`per se by means of two different resistors and bridging
`whose charging condition changes into a discharging
`switches, as is shown, for example, in a simple embodi
`condition during the turn-off time according to a suit
`ment in FIG. 8. In accordance with the invention this
`20
`ably chosen discharging time constant (T2). Thus, a
`switch is switched at the rate of the address output
`separate evaluation is possible of the qualities of the
`signal (15), so that in the integrator the charging time
`signals previously available at the separate input signal
`constant T1 appears during the switching interval of the
`(2). Therefore, this arrangement has the advantage that
`relevant input and the discharging time constant T2
`according to their average signal quality the signal in
`during the remaining time periods. This arrangement in
`25
`puts are switched through to the receiver for different
`FIG. 8 has the advantage that in view of their average
`time intervals approximately in the order of a list of
`signal quality the signal inputs are switched through to
`priorities.
`the receiver for different periods of time according to
`In an advantageous further embodiment of the inven
`the range of a list of priorities also in case the reception
`tion according to an arrangement as shown in FIG. 2,
`is difficult. By means of a switch, which in a manner
`30
`integrators (11) are used having a reset value adjustable
`known per se can also be designed as a semiconductor
`to a specific initial value as shown in FIG. 5. By suitably
`switch, an operational amplifier, a charging capacitor
`allowing for this initial value the mode of operation of
`and three resistors, the circuit for such an integrator is
`the integrators can be ideally adapted to a receive con
`realized in a particularly simple manner as shown, for
`dition.
`example, in FIG. 9. This circuit can be implemented for
`35
`In an extremely simple embodiment of the invention
`each of the integrators shown in Figure 4, as well as for
`the averaging of the interference on the respective input
`the respective integrators shown in the FIGS. 2 and 3.
`signal (2) is effected with the aid of the switching time
`The arrangement of T1 and T2 is effected each time in
`of a signal input. An arrangement of this type is shown
`accordance with the invention in such a manner as
`in FIG. 6. For this purpose both the multiplexer (18)
`claimed in the claims.
`and the storage selector (19) are switched through in
`What is claimed is:
`line with the switch-through rate of the signal selector
`1. A signal diversity receiving system comprising a
`(16). This is effected with the aid of signal (15), which
`receiver and a diversity processor,
`is identical with the signal used to switch the signal
`said processor comprising means for applying a se
`selector (16) through. To receive a value for the aver
`lected one of a plurality of input signals to said
`45
`age switching interval of each input signal (2) sepa
`receiver, and means for applying a different one of
`rately, a time-constant voltage (20) is applied to the
`said input signals to said receiver after a switching
`input of the multiplexer (18). Thus, the output signal of
`interval, in case of interference affecting said se
`each integrator (11) corresponds to the charging and
`lected one,
`discharging time constants of the average switching
`characterized in that said means for applying a differ
`interval of the respective signal inputs. As regards the
`ent one comprises an interference detector operat
`choice of the time constants T1 and T2, the same char
`ing in an analog mode, and a comparator having
`acteristic features are found as those described for the
`first and second inputs, said interference detector
`arrangement shown in FIG. 4. In this manner it is also
`having an output connected to said first input,
`achieved that in view of their average signal quality the
`further comprising means for applying a set value to
`signal inputs are switched through to the receiver for
`said second input, said comparator having a binary
`different periods of time according to the range of a list
`signal output indicative of interference when said
`of priorities.
`output of said interference detector exceeds said set
`FIG. 7 shows an interference frequency detector,
`value,
`composed of a PLL circuit (43), a sample and hold
`at least one integrator having a discharging time con
`60
`circuit (48) and a monoflop (45), which is triggered by
`stant,
`the binary switching signal (10). The output voltage of
`means for deriving a signal from said interference
`the sample and hold circuit is used to control the dis
`detector output and applying that signal to said at
`charging time constant in the integrator. This arrange
`least one integrator, said at least one integrator
`ment is in a position to indicate the average frequency at
`having a time of integration equal to said switching
`65
`which interference occurs. This is effected by compar
`interval, and
`ing the frequency of the subsequent VCO (23) to the
`means for adding said integrator output signal to one
`repetition frequency of the interference of the signal
`of said comparator inputs for varying a relationship
`
`50
`
`55
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 8 of 11
`
`

`

`4,876,743
`7
`8
`between a magnitude of the interference detector
`7. A system as claimed in any one of claims 1-6,
`comprising means for providing a proportional output
`output and said set value when the interference
`signal increases.
`signal which is proportional to the average interference
`2. A system as claimed in claim 1, for receiving one of
`frequency and is applied to said at least one integrator,
`a given number of said input signals, said means for 5
`and means for reducing respective time constants of said
`applying a different one comprising said given number
`at least one integrator when said interference frequency
`of said integrators,
`increases.
`-
`a multiplexer for applying a respective interference
`8. A system as claimed in claim 7, characterized in
`detector output signal corresponding to a respec
`that said means comprises a phase locked loop circuit
`tive input signal to a respective integrator,
`having a mixer with a low pass filter, providing a first
`means for applying a time constant signal to said
`separate output, a voltage controlled oscillator provid
`multiplexer during a respective switching interval
`ing a second separate output, a sample and hold circuit
`of the respective input signal,
`with a low pass filter receiving an output of said mixer,
`a storage selector for receiving and storing the re
`and means for driving a control input of said sample and
`spective integrator outputs, for applying the inte- 15
`hold circuit through a monoflop, and means for driving
`grator output corresponding to a respective input
`said monoflop by said binary signal.
`signal during a switching interval in which the
`9. A system as claimed in claim 4, characterized in
`multiplexer is applying the corresponding input
`that said integrator output signal is applied to said re
`signal to the respective integrator, and
`ceiver, and said receiver comprises adjustable means for
`means for controlling said multiplexer and said stor
`reducing said signal responsive to increase in the inter
`20
`age selector by a common digital address signal.
`ference of the selected input signal as a function of said
`integrator output signal.
`3. A system as claimed in claim 1, characterized in
`that said interference detector output signal is applied to
`10. A system as claimed in claim 1, characterized in
`said at least one integrator having a discharging time
`that said integrator output signal is applied to said re
`ceiver, and said receiver comprises adjustable means for
`COnstant.
`25
`4. A system as claimed in claim 3, characterized in
`reducing said signal responsive to increase in the inter
`that said at least one integrator has a charging time
`ference of the selected input signal as a function of said
`integrator output signal.
`constant T1 higher than an average time period be
`tween successive interference signals during operation.
`11. A system as claimed in claim 1, characterized in
`that said processor comprises a signal selecting circuit
`5. A system as claimed in claim 4, characterized in
`30
`that said processor comprises a signal selecting circuit
`having a digital address output signal, and a signal selec
`having a digital address output signal, and a signal selec
`tor receiving said digital address output signal, said
`tor receiving said digital address output signal, said
`means for applying a different one connecting the re
`means for applying a different one connecting the re
`spective input signal corresponding to the digital ad
`spective input signal corresponding to the digital ad-35
`dress output signal to the receiver,
`dress output signal to the receiver,
`said at least one integrator comprising a respective
`said at least one integrator comprising a respective
`integrator for each of said plurality of input signals,
`integrator for each of said plurality of input signals,
`each of said integrators having a switched dis
`each of said integrators having a switched dis
`charging time constant,
`charging time constant,
`a multiplexer receiving said input signals and an inter
`40
`a multiplexer receiving said input signals and an inter
`ference detector output signal, for applying a re
`ference detector output signal, for applying a re
`spective input signal to the respective associated
`spective input signal to the respective associated
`integrator during the multiplexer switching inter
`integrator during the multiplexer switching inter
`val of the respective input signal, and
`val of the respective input signal, and
`a storage selector for applying the output signal of
`45
`a storage selector for applying the output signal of
`each respective integrator to the comparator sec
`each respective integrator to the comparator sec
`ond input during said switching interval.
`ond input during said switching interval.
`12. A system as claimed in claim 1, characterized in
`that said processor comprises one only integrator hav
`6. A system as claimed in claim 4, characterized in
`that said processor comprises one only integrator hav
`ing a discharging time constant, and means for setting
`50
`ing a discharging time constant, and means for setting
`said integrator to a predetermined initial value after
`said integrator to a predetermined initial value after
`each switching operation.
`each switching operation.
`
`O
`
`55
`
`65
`
`six
`
`k
`
`is
`
`is
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 9 of 11
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`4,876, 743
`PATENT NO. :
`October 24, 1989
`DATED
`Lindenmeier et al.
`INVENTOR(S) :
`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby
`Corrected as shown below:
`
`
`
`
`
`In the title page, under " (75) Inventors : " change "both" to
`--Ernst Manner, Ottobrun, all--.
`
`Signed and Sealed this
`Fifteenth Day of January, 1991
`
`Attest:
`
`Attesting Officer
`
`Commissioner of Patents and Trademarks
`
`HARRY F. MANBECK, JR.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 10 of 11
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`4, 876, 743
`PATENT NO. :
`October 24, 1989
`DATED
`Lindenmeier et all
`INVENTOR(S) :
`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`In the title page, under " (75) Inventors: " change "both." tO
`Ernst Manner, Ottobrun, all--.
`
`Signed and Sealed this
`Fifteenth Day of January, 1991
`
`Attest:
`
`Attesting Officer
`
`Commissioner of Patents and Trademarks
`
`HARRY F. MANBECK, JR.
`
`
`
`ERICSSON v. UNILOC
`Ex. 1041 / Page 11 of 11
`
`