IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`SAMSUNG DISPLAY CO., LTD.,
`Petitioner,
`
`v.
`
`SOLAS OLED, LTD.,
`Patent Owner.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Case No. IPR2020-00320
`U.S. Patent No. 7,446,338
`
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,446,338
`UNDER 35 U.S.C. §§ 311–319 AND 37 C.F.R. § 42.100 et seq.
`
`
`
`

`

`
`
`LIST OF EXHIBITS
`
`
`Description
`U.S. Patent No. 7,446,338 (the “’338 patent”)
`File History for U.S. Patent No. 7,446,338
`U.S. Patent Application Pub. No. 2002/0158835 (“Kobayashi”)
`U.S. Patent Application Pub. No. 2004/0113873 (“Shirasaki”)
`International Publication No. WO 03/079441 (“Childs”)
`European Patent Application No. EP 1331666 (“Yamazaki”)
`U.S. Patent Application Pub. No. 2004/0165003 (“Shirasaki II”)
`Japanese Patent Publication No. 2004-258172
`U.S. Patent Application Pub. No. 2003/0151637 (“Nakamura”)
`International Publication No. WO 03/079442 (“Hector”)
`International Publication No. WO 03/079449 (“Young”)
`Tsujimura, Takatoshi. OLED Display Fundamentals and
`Applications: Fundamentals and Applications, John Wiley &
`Sons, Incorporated, 2012. (“Tsujimura”)
`Crawford, Gregory P. Flexible flat panel display technology. Vol.
`3. West Sussex: Wiley, 2005. (“Crawford”)
`U.S. Patent Application Pub. No. 2003/0127657 (“Park”)
`U.S. Patent No. 7,498,733 (“Shimoda”)
`U.S. Patent Application Pub. No. 2002/0000576 (“Inukai”)
`U.S. Patent Application Pub. No. 2002/0009538 (“Arai”)
`Declaration of Dr. Adam Fontecchio
`Curriculum Vitae of Adam Fontecchio
`
`
`Exhibit
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`1012
`
`1013
`
`1014
`1015
`1016
`1017
`1018
`1019
`
`- 1 -
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`

`

`Table of Contents
`
`
`
`B.
`
`I.
`Introduction ...................................................................................................... 4
`II.
`Standing, Mandatory Notices, and Fee Authorization .................................... 9
`III. Summary of Challenge .................................................................................. 10
`IV. Overview of the ’338 Patent .......................................................................... 12
`A.
`“Interconnections Which Are Formed to Project from a Surface
`of the Transistor Array Substrate” ...................................................... 14
`“Driving Transistor,” “Switch Transistor,” and “Holding
`Transistor” ........................................................................................... 18
`C.
`Prosecution History ............................................................................. 19
`V.
`Level of Ordinary Skill .................................................................................. 21
`VI. Claim Construction ........................................................................................ 21
`A.
`“transistor array substrate” (claim 1) .................................................. 21
`B.
`“a plurality of interconnections which are formed to project
`from a surface of the transistor array substrate” (claim 1) .................. 23
`“the pixel electrodes being arrayed along the interconnections
`between the interconnections on the surface of the transistor
`array substrate” (claim 1) .................................................................... 25
`VII. Overview of the Prior Art .............................................................................. 26
`A. Kobayashi (Ex. 1003) .......................................................................... 29
`B.
`Shirasaki (Ex. 1004) ............................................................................ 32
`C.
`Childs (Ex. 1005) ................................................................................ 34
`VIII. Application of Prior Art to the Challenged Claims ....................................... 37
`A. Ground I: Claims 1–2, 5–6, and 9–11 Are Unpatentable Under
`35 U.S.C. § 103 Over the Combination of Kobayashi and
`Shirasaki. ............................................................................................. 38
`
`C.
`
`- 2 -
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`

`

`
`
`B.
`
`1.
`Claim 1 ...................................................................................... 39
`2.
`Claim 2 ...................................................................................... 58
`3.
`Claim 5 ...................................................................................... 58
`4.
`Claim 6 ...................................................................................... 59
`5.
`Claim 9 ...................................................................................... 60
`6.
`Claim 10 .................................................................................... 61
`7.
`Claim 11 .................................................................................... 62
`Ground II: Claims 1–3 and 5–13 Are Unpatentable Under 35
`U.S.C. § 103 Over the Combination of Childs and Shirasaki. ............ 63
`1.
`Claim 1 ...................................................................................... 64
`2.
`Claim 2 ...................................................................................... 82
`3.
`Claim 3 ...................................................................................... 84
`4.
`Claim 5 ...................................................................................... 86
`5.
`Claim 6 ...................................................................................... 87
`6.
`Claim 7 ...................................................................................... 87
`7.
`Claim 8 ...................................................................................... 88
`8.
`Claim 9 ...................................................................................... 88
`9.
`Claim 10 .................................................................................... 88
`10. Claim 11 .................................................................................... 90
`11. Claim 12 .................................................................................... 91
`12. Claim 13 .................................................................................... 92
`IX. Conclusion ..................................................................................................... 93
`
`- 3 -
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`

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`
`
`I.
`
`INTRODUCTION
`Samsung Display Co., Ltd. (“Petitioner”) petitions for inter partes review
`
`seeking cancellation of claims 1–3 and 5–13 of U.S. Patent No. 7,446,338 (Ex. 1001,
`
`“’338 patent”), assigned to Solas OLED, Ltd. (“Patent Owner”).
`
`The ’338 patent relates to active-matrix organic light-emitting diode
`
`(AMOLED) display panels. Ex. 1001, 1:51–65, 4:53–56, 5:51–53. The patent is
`
`directed to AMOLED displays having two purportedly distinctive features: (1)
`
`conductive “interconnections” that project from the surface of the substrate on which
`
`the OLED elements are formed, id., 2:42–44, 3:63–67; and (2) a specific circuit to
`
`drive each pixel in the OLED device made up of three thin-film transistors (“TFTs”),
`
`id., 6:45–7:18.
`
`Regarding the first feature, the ’338 patent describes and claims three types of
`
`projecting “interconnections” (“feed, “select,” and “common”):
`
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`
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`The ’338 patent explains that each type of interconnection is a low-resistance
`
`conductive element that “projects” upward in relation to the substrate below
`
`containing the TFTs (and on which the OLED elements are formed). Id., 2:42–44.
`
`Each type of interconnection is electrically coupled to (and lowers the resistance of)
`
`a separate conductive component in the OLED structure. For example, the “feed”
`
`interconnection is electrically coupled to the voltage supply lines that bring power
`
`to the OLED elements, id., 5:48–50, 14:20–29, and the “common” interconnection
`
`is electrically coupled to the transparent cathode electrode in each of the OLED
`
`elements, id., 7:16–18, 17:59–18:7.
`
`However, these types of projecting interconnections were all known in the
`
`prior art. Accordingly, during prosecution of the ’338 patent, original independent
`
`- 5 -
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`

`
`
`claim 1 was rejected by the Examiner over the prior art. Ex. 1002, 446 (October 23,
`
`2007 Non-Final Rejection) (citing “auxiliary electrode[s] 621” and “721” of
`
`European Patent Application No. EP 1331666 to Yamazaki et al. (“Yamazaki”) (Ex.
`
`1006) for the claimed “plurality of interconnections.”).
`
`To gain allowance of the ’338 patent, the applicants added to independent
`
`claim 1 another feature—the specific three-transistor circuit structure of each pixel:
`
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`
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`But while the Examiner believed this second feature to be novel at the time, he was
`
`not made aware that the prior art disclosed this specific structure and specifically
`
`encouraged use of it over two-transistor structures. For instance, the Examiner was
`
`not informed of prior art U.S. Patent Application Pub. No. 2004/0113873 to
`
`Shirasaki et al. (“Shirasaki”), which disclosed this three-transistor pixel circuit
`
`structure more than a year before the U.S. filing date of the ’338 patent. This
`
`reference was not identified during prosecution, even though it had the same lead
`
`inventor as the ’338 patent.1
`
`Shirasaki taught the three-transistor pixel circuit structure claimed in the ’338
`
`patent, with circuit diagrams depicting the same structure as found in the ’338 patent.
`
`Compare Ex. 1004, Figs. 1, 5A–B, 9A–B, with Ex. 1001, Fig. 2. Moreover,
`
`Shirasaki explained why its three-transistor pixel circuit structure was an
`
`improvement for OLED displays and should be used instead of the two-transistor
`
`pixel circuit structure more commonly used in OLED displays at the time. See Ex.
`
`1004, ¶¶ [0002]–[0025].
`
`
`1 For clarity, because this prior art reference and the challenged patent share the same
`
`lead inventor, Tomoyuki Shirasaki, the Petition refers to this reference as
`
`“Shirasaki,” and to the challenged patent as “the ’338 patent.”
`
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`
`
`Thus, both purportedly distinctive features of the ’338 patent were taught in
`
`the prior art as desirable features to improve the performance of OLED displays.
`
`Further, as noted above, Shirasaki described why it would have been beneficial to
`
`use its three-transistor pixel circuit (the second feature) to replace the conventional
`
`pixel circuits found in OLED prior art that included the claimed “interconnections”
`
`(the first feature). Accordingly, claims 1–3 and 5–13 would have been obvious to a
`
`person of ordinary skill at the time of the alleged invention based on the prior art.
`
`As explained in Ground I below, claims 1–2, 5–6, and 9–11 are unpatentable
`
`over U.S. Patent Application Pub. No. 2002/0158835 to Kobayashi et al.
`
`(“Kobayashi”) in view of Shirasaki. Kobayashi teaches the claimed “common” type
`
`of projecting interconnections, which are electrically connected to and lower the
`
`resistance of the pixel cathode. The combination of Kobayashi and Shirasaki would
`
`have been no more than simple substitution of one known element (Shirasaki’s three-
`
`transistor pixel circuit) for another (Kobayashi’s two-transistor pixel circuit), a
`
`substitution motivated by the reasons expressly described by Shirasaki, Ex. 1004, ¶¶
`
`[0002]–[0025].
`
`As explained in Ground II below, claims 1–3 and 5–13 of the ’338 patent are
`
`unpatentable as obvious over the combination of International Publication No. WO
`
`03/079441 to Childs et al. (“Childs”) and Shirasaki. Childs discloses the other two
`
`types of projecting interconnections claimed by the ’338 patent (“feed”
`
`- 8 -
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`

`
`
`interconnections electrically connected to a supply line and “select” interconnections
`
`electrically connected to a scan line). Similar to the Kobayashi–Shirasaki
`
`combination, the combination of Childs and Shirasaki would have been no more
`
`than the simple substitution of Shirasaki’s three-transistor pixel circuit for Childs’
`
`two-transistor pixel circuit, a substitution which again was motivated for the reasons
`
`described in Shirasaki, Ex. 1004, ¶¶ [0002]–[0025].
`
`II.
`
`STANDING, MANDATORY NOTICES, AND FEE
`AUTHORIZATION
`Grounds for Standing: Pursuant to 37 C.F.R. § 42.104(a), Petitioner certifies
`
`that the ’338 patent is available for IPR and that Petitioner is not barred or estopped
`
`from requesting an IPR challenging the ’338 patent on the grounds identified in this
`
`petition.
`
`Real Party-in-Interest: Petitioner identifies Samsung Display Co., Ltd.,
`
`Samsung Electronics Co., Ltd., and Samsung Electronics America, Inc. as real
`
`parties in interest.
`
`Related Matters: Patent Owner has asserted the ’338 patent in litigation
`
`against the real parties-in-interest in Solas OLED Ltd. v. Samsung Display Co., Ltd.,
`
`et al., Case No. 2:19-cv-00152-JRG (E.D. Tex.). Patent Owner has also asserted the
`
`’338 patent in litigation against Apple Inc. in Solas OLED Ltd. v. Apple Inc., Case
`
`No. 6:19-cv-00527 (W.D. Tex.), and against Google Inc. in Solas OLED Ltd. v.
`
`Google Inc., Case No. 6:10-cv-00515 (W.D. Tex.).
`
`- 9 -
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`
`
`Lead and Back-Up Counsel: Petitioner designates David A. Garr (Reg. No.
`
`74,932, dgarr@cov.com) as lead counsel and Grant D. Johnson (Reg. No. 69,915,
`
`gjohnson@cov.com) as back-up counsel, both of Covington & Burling LLP, One
`
`CityCenter, 850 Tenth Street, NW, Washington, DC 20001 (postal and hand
`
`delivery), telephone: 202-662-6000, facsimile: 202-662-6291.
`
`Petitioner also designates Peter P. Chen (Reg. No. 39,631) as back-up counsel,
`
`of Covington & Burling LLP, 3000 El Camino Real, 5 Palo Alto Square, 10th Floor,
`
`Palo Alto, CA 94306 (postal and hand delivery), telephone: 650-632-4700, facsimile:
`
`650-632-4800.
`
`Service Information: Service information is provided in the designation of
`
`counsel above. Petitioner consents to service of all documents via electronic mail at
`
`the email addresses above and at Samsung-Solas@cov.com.
`
`Fee Authorization: The Office is authorized to charge $30,500 ($15,500
`
`request fee and $15,000 post-institution fee) for the fees set forth in 37 C.F.R.
`
`§ 42.15(a) (as well as any additional fees that might be due) to Deposit Account No.
`
`60-3160.
`
`III. SUMMARY OF CHALLENGE
`Petitioner requests IPR of claims 1–3 and 5–13 of the ’338 patent under 35
`
`U.S.C. § 103 based on the following prior art combinations:
`
`- 10 -
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`
`
`• Ground I: Claims 1–2, 5–6, and 9–11 are obvious over the combination
`of Kobayashi and Shirasaki.
`
`• Ground II: Claims 1–3 and 5–13 are obvious over the combination of
`Childs and Shirasaki.
`
`The ’338 patent has a U.S. filing date of September 26, 2005, and claims
`
`priority to a Japanese application filed on September 29, 2004. Each of the asserted
`
`references is available as prior art under 35 U.S.C. § 102 (pre-AIA)2, as shown in
`
`the following table.
`
`Reference
`Exhibit
`Ex. 1003 U.S. Patent Application
`Pub. No. 2002/0158835
`(“Kobayashi”)
`
`Ex. 1004 U.S. Patent Application
`Pub. No. 2004/0113873
`(“Shirasaki”)
`Ex. 1005 International Publication
`No. WO 03/079441
`(“Childs”)
`
`Date(s)
`October 31, 2002
`(published);
`April 19, 2002 (filed)
`June 17, 2004 (published);
`September 16, 2003 (filed)
`
`Availability
`as Prior Art
`§§ 102 (a),
`(b), and (e)
`
`§ 102 (b)3
`
`Sept. 25, 2003 (published);
`Feb. 21, 2003 (filed)
`
`§§ 102 (a),
`(b), and (e)
`
`
`
`
`2 Because the application for the ’338 patent was filed prior to March 16, 2013, the
`
`pre-AIA conditions for patentability apply.
`
`3 Foreign priority is not applicable for Section 102(b). See generally MPEP
`
`§ 2133.02.
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`
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`IV. OVERVIEW OF THE ’338 PATENT
`The ’338 patent (Ex. 1001) states that it “relates to a display panel using a
`
`light-emitting element,” Ex. 1001, 1:14–15—specifically,
`
`to a “organic
`
`electroluminescent display panel of [the] active matrix driving type” (i.e. an
`
`“AMOLED”), id., 1:51–65, 3:53–56, 5:51–53; Ex. 1018, ¶ [0054]. The challenged
`
`claims are directed to an AMOLED structure with two key features: (a) conductive
`
`“interconnections” that project from the surface of a substrate on which the OLED
`
`elements are formed, id., 3:63–67; and (b) a specific circuit design for each pixel in
`
`the OLED display panel made up of three TFTs, id., 6:45–7:18.
`
`In particular, challenged independent claim 1 recites:
`
`1. A display panel comprising:
`
`[a] a transistor array substrate which includes a plurality of pixels and
`comprises a plurality of transistors for each pixel, each of the transistors
`including a gate, a gate insulating film, a source, and a drain;
`
`[b] a plurality of interconnections which are formed to project from a
`surface of the transistor array substrate, and which are arrayed in
`parallel to each other;
`
`[c] a plurality of pixel electrodes for the plurality of pixels, respectively,
`the pixel electrodes being arrayed along the interconnections between
`the interconnections on the surface of the transistor array substrate;
`
`[d] a plurality of light emitting layers formed on the pixel electrodes,
`respectively and
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`
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`[e] a counter electrode which is stacked on the light-emitting layers,
`
`[f] wherein said plurality of transistors for each pixel include [1] a
`driving transistor, one of the source and the drain of which is connected
`to the pixel electrode, [2] a switch transistor which makes a write
`current flow between the drain and the source of the driving transistor,
`and [3] a holding transistor which holds a voltage between the gate and
`source of the driving transistor in a light emission period.
`
`The ’338 patent concedes, in the “Description of the Related Art,” Ex. 1001,
`
`1:16–2:30, that many of these claim elements were known in the art and commonly
`
`used in “conventional organic electroluminescent display panel[s] of [the] active
`
`matrix driving type,” id., 1:21–26, 1:51–52, noting that such conventional
`
`AMOLED display panels contained a “transistor array substrate” (element [a]), id.,
`
`2:17–21; “an organic electroluminescent element . . . for each pixel” (elements [c]–
`
`[e]), id., 1:24–31; “interconnections such as a power supply line,” (element [b]), id.,
`
`1:51–56; and “driving” and “switching transistors” (elements [f][1] and [f][2]), id.,
`
`1:21–31; Ex. 1018, ¶ [0055].
`
`The only purportedly novel elements of challenged independent claim 1 are
`
`the ones underlined above: that is, the claimed “interconnections which are formed
`
`to project from a surface of the transistor array substrate” (element [b]); and a three-
`
`transistor circuit “for each pixel” that includes a “holding transistor” in addition to
`
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`

`
`
`the conventional “driving and “switch transistor[s]” (element [f][3]). These features
`
`are discussed in the following two subsections.
`
`A.
`
`“Interconnections Which Are Formed to Project from a Surface
`of the Transistor Array Substrate”
`The ’338 patent explains that in conventional AMOLED displays, electrical
`
`“interconnections such as a power supply line to supply a current to an organic EL
`
`element are patterned simultaneously in the thin-film transistor patterning step by
`
`using the [same] material as a thin-film transistor.” Ex. 1001, 1:51–65. Because the
`
`electrical interconnections are formed in the same layer as the TFT, “the thickness
`
`of the interconnection equals that of the thin-film transistor,” id., which “is thin
`
`literally,” id., 2:2–3; Ex. 1018, ¶ [0056].
`
`The ’338 patent explains that these thin interconnections cause resistance
`
`problems: when “a current is supplied from the interconnection to a plurality of light-
`
`emitting elements, a voltage drop occurs, or the current flow through the
`
`interconnection delays due to the electrical resistance of the interconnection.” Ex.
`
`1001, 2:3–7. The ’338 patent explains that other thin elements in conventional
`
`OLEDs similarly suffer from issues caused by high resistance—specifically, the
`
`cathode electrodes of the “organic EL element” itself, which are “[c]onventionally . . .
`
`formed as a transparent electrode of, e.g., a metal oxide having a high resistance
`
`value,” such as “ITO [indium tin oxide].” Id., 13:28–14:2. The “only” way to
`
`“sufficiently reduce the sheet resistance” of these transparent cathodes is “by
`
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`

`
`
`increasing the[ir] thickness,” id, 14:2–3—but “[w]hen the material is thick, the
`
`transparency of the organic EL element decreases inevitably . . . and the display
`
`characteristic becomes poor,” id., 14:4–7; Ex. 1018, ¶ [0057].
`
`To solve the problems caused by the high resistance of these components,
`
`the ’338 patent proposes the use of three types of additional “interconnections,” each
`
`of which has a “low resistance” and is “electrically connected” to higher-resistance
`
`components in the OLED structure (decreasing their resistance). Ex. 1001, 21:63–
`
`22:61. The “common interconnection” is electrically connected to the higher-
`
`resistance cathode electrode of the OLED elements, bringing down the resistance of
`
`that cathode and making its voltage “uniform[]” across the electrode. Id., 22:2–10.
`
`Two other types of interconnections, “select” and “feed,” are “electrically connected”
`
`to the “thin scan lines” and “thin supply lines” of the OLED display, respectively,
`
`bringing down the resistance of those thin lines. Id., 22:20–61. The ’338 patent
`
`explains that “[w]hen the resistance of these interconnections decreases, the signal
`
`delay and voltage drop can be suppressed.” Id., 3:63–67; Ex. 1018, ¶ [0058].
`
`The ’338 patent’s “plurality of interconnections” are illustrated in annotated
`
`Figure 1, showing “a schematic plan view . . . of a display panel 1 which is operated
`
`by the active matrix driving method.” Ex. 1001, 4:53–56. The display panel
`
`includes “a plurality of select
`
`interconnections 89, a plurality of feed
`
`interconnections 90, and a plurality of common interconnections 91,” id., 5:23–27,
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`- 15 -
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`

`
`
`arranged between “sub-pixel[s]” Pr, Pg, and Pb,
`
`id., where “the select
`
`interconnection 89 overlaps” and is “electrically connected to the scan line [X],”
`
`and “[t]he feed interconnection 90 overlaps” and is “electrically connected to the
`
`supply line [Z],” id., 5:46–50; Ex. 1018, ¶¶ [0059]–[0060]:
`
`
`
`Figure 6 illustrates a cross-section of “the layer structure of display panel 1.”
`
`Ex. 1001, 8:18–20. As this figure shows, the projecting interconnections are formed
`
`on top of a layered “transistor array substrate 50” (shown in orange). Id., 10:42–47
`
`(depicting “insulating substrate 2,” “gate insulating film 31,” “protective insulating
`
`film 31,” and “planarization film 3” forming a “layered structure” that contains
`
`- 16 -
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`

`

`“switch transistors 21” and “driving transistors 23” and “is called a transistor array
`
`substrate 50”); Ex. 1018, ¶¶ [0061]–[0062]:
`
`
`
`
`
`As illustrated in annotated Figure 6 above, “the select interconnection 89 and
`
`feed interconnection 90 project upward from the upper surface of the planarization
`
`film,” Ex. 1001, 11:36–41, as does “common interconnection 91,” which is “formed
`
`on the insulating line 61,” id., 10:48–58. Each of the “organic EL element[s] 20” is
`
`“electrically connected to the . . . source 23s of the driving transistor 23” through
`
`“contact hole 88,” id., 12:6–15, and the “counter electrode 20c functioning as the
`
`cathode of the organic EL element 20” is “electrically connected to the common
`
`interconnections 91,” id., 13:28–37; Ex. 1018, ¶ [0063].
`
`- 17 -
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`

`
`
`B.
`
`“Driving Transistor,” “Switch Transistor,” and “Holding
`Transistor”
`The “layered structure” of “transistor array substrate 50” includes within it
`
`three transistors for each sub-pixel of the display panel 1: “switch transistor 21,”
`
`“holding transistor 22,” and “driving transistor 23.” Ex. 1001, 10:25–47. The
`
`“circuit arrangement” of these three transistors (along with interconnections 89–91
`
`and organic EL element 20) is depicted in annotated Figure 2, id., 6:45–7:18; Ex.
`
`1018, ¶ [0064]:
`
`
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`- 18 -
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`
`
`The ’338 patent explains that “switch transistor 21 functions to turn on
`
`(selection period) and off (light emission period) [] the current between the signal
`
`line Yj and the source 23s of the driving transistor 23,” Ex. 1001, 17:26–37, as
`
`illustrated by arrows “A” in Figure 2, above, id., 16:30–41. If the switching
`
`transistor is on, “no driving current flows to the organic EL element 20, and no light
`
`emission occurs.” Id., 17:24–25. The “holding transistor 22 functions to . . . hold
`
`the voltage between the gate 23g and the source 23s of the [driving] transistor 23 in
`
`the light emission period.” Id., 17:29–37. Finally, the “driving transistor 23
`
`functions to drive the organic EL element by supplying a current . . . to the organic
`
`EL element 20,” causing “the organic EL element [to] emit[] light.” Id. (with that
`
`“driving current” illustrated by arrow “B” in Figure 2, above, id., 17:10–15); Ex.
`
`1018, ¶¶ [0065]–[0066].
`
`C.
`Prosecution History
`As originally filed, claim 1 of the ’338 patent’s application contained only
`
`elements [a]–[e] listed above, and did not require the three-transistor pixel circuit
`
`(element [f]), i.e., a “driving transistor,” “holding transistor,” and “switch transistor.”
`
`Ex. 1002, 817 (September 26, 2005 originally filed claims). The Examiner rejected
`
`this original claim as anticipated by Yamazaki, noting that Yamazaki disclosed every
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`limitation of the claim including the “plurality of interconnections which are formed
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`to project to a surface of the transistor array substrate.” Id., 446 (October 23, 2007
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`Non-Final Rejection) (citing “auxiliary electrode 621” and “auxiliary electrode 721”
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`of Yamazaki as teaching the claimed “plurality of interconnections.”). The
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`Examiner stated, however, that originally filed dependent claim 2 (requiring that the
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`“plurality of transistors includes a driving transistor . . . a switch transistor . . . and a
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`holding transistor”) would “be allowable if rewritten in independent form.” Id., 448,
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`817.
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`In response to this initial Office Action, the applicants amended claim 1 “to
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`incorporate the subject matter of claim 2 [i.e. the three-transistor pixel circuit],” id.,
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`436 (February 25, 2008 Remarks), and the Examiner issued a Notice of Allowance
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`for all pending claims, id., 333 (May 30, 2008 Notice of Allowance).
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`The applicants never identified Shirasaki during prosecution. Two months
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`after the issuance of the Notice of Allowance and the close of prosecution, the
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`applicants submitted an Information Disclosure Statement identifying another
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`application that listed Tomoyuki Shirasaki as the lead inventor—U.S. Patent
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`Publication No. 2004/0165003 (“Shirasaki II”) (Ex. 1007)—as well as its Japanese
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`counterpart (JP 2004-258172) (Ex. 1008). Id., 32–36 (August 5, 2008 IDS).
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`Because prosecution had closed, the applicants provided a statement under 37
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`C.F.R. § 1.97(e) representing that Shirasaki II was not “known to any individual
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`designated in 37 C.F.R. 1.56(c) more than three months prior to the filing of this
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`Information Disclosure Statement,” id., even though Shirasaki II had been published
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`nearly four years earlier and Tomoyuki Shirasaki was also the lead named inventor
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`of the ’338 patent. The applicants also did not indicate in the IDS that Shirasaki II
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`disclosed the same three-transistor pixel circuit as the ’338 patent. Compare Ex.
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`1001, Fig. 2, with Ex. 1007, Fig. 1, Fig. 3.
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`After the applicants paid the issue fee on August 29, 2008, Ex. 1002, 31, the
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`Examiner initialed the IDS on September 19, 2008, id., 30, and the ’338 patent issued
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`on November 4, 2008.
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`V. LEVEL OF ORDINARY SKILL
`A person of ordinary skill in the art (“POSA”) of the ’338 patent at the time
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`of the alleged invention would have had a relevant technical degree in electrical
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`engineering, computer engineering, physics, or the like, and 2–3 years of experience
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`in active matrix display design and/or manufacturing. Ex. 1018, ¶¶ [0073]–[0074].
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`VI. CLAIM CONSTRUCTION
`In IPR proceedings, claims are now construed “in accordance with their
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`ordinary and customary meaning.” 37 C.F.R. § 42.100(b); see Phillips v. AWH
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`Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005). Petitioner discusses the meaning of
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`certain claim limitations below.
`
`A.
`“transistor array substrate” (claim 1)
`The ’338 patent describes the “transistor array substrate” as the layered
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`structure on which the pixel electrodes are formed. The “transistor array substrate
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`50” is depicted in orange in annotated Figure 6 of the ’338 patent below:
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`As Figure 6 demonstrates, the “transistor array substrate” includes all of the layers
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`beneath the pixel electrodes, including the insulating substrate (element 2 in Figure
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`6), the gate insulating film (element 31 in Figure 6) and any additional planarization
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`or other insulating layers above the transistor array and below the pixel electrodes
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`(in Figure 6, protective insulating film 32 and planarization film 33). Ex. 1018, ¶¶
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`[0079]–[0081] (citing Ex. 1015, 8:38–58).
`
`The ’338 patent’s specification describes the “transistor array substrate” as
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`including all of the layers beneath the pixel electrodes, from the bottommost
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`“insulating substrate” through the topmost insulating layer on whose surface the
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`pixel electrodes are formed (in Figure 6, the planarization film 33), Ex. 1018, ¶
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`[0077]:
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`The plurality of sub-pixel electrodes 20a are arrayed in a matrix on the
`upper surface of the planarization film 33, i.e., on the surface of the
`transistor array substrate 50. The sub-pixel electrodes 20a are
`formed . . . by patterning a transparent conductive film formed on the
`entire surface of the planarization film 33.
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`Ex. 1001, 11:50–55 (emphasis added); see also id., 10:48–51. Edwards Lifesciences
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`LLC v. Cook Inc., 582 F.3d 1322, 1334 (Fed. Cir. 2009) (“the specification’s use of
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`‘i.e.’ signals an intent to define the word to which it refers”) (emphasis added).
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`Accordingly, this term should be interpreted as covering a layered structure
`
`including a bottom insulating substrate through a topmost insulating layer on whose
`
`surface the pixel electrodes are formed. Ex. 1018, ¶ [0082].
`
`B.
`
`“a plurality of interconnections which are formed to project from
`a surface of the transistor array substrate” (claim 1)
`Claim 1 refers to “a plurality of interconnections which are formed to project
`
`from a surface of the transistor array substrate.” As noted above, the ’338 patent
`
`defines the “surface of the transistor array substrate” as the upper surface of the
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`topmost layer of the transistor array substrate, on which pixel electrodes are formed.
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`Ex. 1001, 11:50–52, 10:48–51; Ex. 1018, ¶ [0083].
`
`As to the meaning of “project from” a surface of the transistor array substrate,
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`the ’338 patent provides several examples. The specification describes how
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`“common interconnection 91 is . . . formed to . . . project upward from the surface
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`of the planarization film 33,” Ex. 1001, 10:54–58, and “the select interconnection
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`89 and feed interconnection 90 project upward from the upper surface of the
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`planarization film 33,” id., 11:36–41, as depicted in annotated Figure 6, Ex. 1018, ¶
`
`[0083]:
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`
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`
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`The ’338 patent goes on to explain that each of “select interconnection 89,
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`feed interconnection 90, and common interconnection 91 . . . are formed . . . to
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`project respect to the surface of the transistor array substrate 50.” Ex. 1001, 12:62–
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`67; Ex. 1018, ¶ [0084].
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`Accordingly, this term should be interpreted to encompass a plurality of
`
`interconnections which are formed to extend above the upper surface of the topmost
`
`layer of the transistor array substrate (as in Figure 6, above). Id.
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`C.
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`“the pixel electrodes being arrayed along the interconnections
`between the interconnections on the surface of the transistor
`array substrate” (claim 1)
`As previously discussed, the “surface of the transistor array substrate” refers
`
`to the upper surface of the topmost insulating layer on which the pixel electrodes are
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`formed. Ex. 1001, 11:50–52, 10:48–51. Petitioner submits that the proper
`
`interpretation of the claim limitation above is that the pixel electrodes: (1) are
`
`arrayed along the interconnections between the interconnections; and (2) are arrayed
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`on the surface of the transistor array substrate. Ex. 1018, ¶ [0085].
`
`This interpretation is supported by both the disclosure and cl