USOO7498733B2
`
`(12) United States Patent
`Shimoda et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,498,733 B2
`Mar. 3, 2009
`
`(54) DISPLAY PANEL
`75
`(75) Inventors: Satoru Shimoda, Fussa (JP); Manabu
`Takei, Sagamihara (JP); Tomoyuki
`Shirasaki, Higashiyamato (JP); Jun
`Ogura, Fussa (JP)
`
`1/2004 Nishi et al. ................. 174/250
`2004/0003939 A1
`8, 2004 Sato et al.
`2004O160170 A1
`8/2004 Shirasaki
`2004/O165003 A1
`2004/02566.17 A1 12/2004 Yamada et al.
`2005.0062409 A1
`3/2005 Yamazaki et al. ........... 313,504
`
`(73) Assignee: Casio Computer Co., Ltd., Tokyo (JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 441 days.
`
`(21) Appl. No.: 11/235,605
`
`(22) Filed:
`
`Sep. 26, 2005
`
`(65)
`
`Prior Publication Data
`US 2006/0066219 A1
`Mar. 30, 2006
`
`Foreign Application Priority Data
`(30)
`Sep. 29, 2004
`(JP)
`............................. 2004-283963
`(51) Int. Cl.
`(2006.01)
`HOL L/62
`(52) U.S. Cl. ........................... 313/500; 345/44; 345/45;
`313/505; 315/169.3
`(58) Field of Classification Search ....................... None
`See application file for complete search history.
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`5,684,365 A 1 1/1997 Tang et al.
`6.297,589 B1
`10/2001 Miyaguchi et al.
`6,717,357 B2
`42004 Okuyama et al.
`6,839,057 B2
`1/2005 Iguchi
`7,358,529 B2
`4/2008 Childs et al.
`7,402,948 B2
`7/2008 Yamazaki et al.
`2003/0047730 A1
`3f2003 Konuma ...................... 257/42
`2003/0137325 A1
`7/2003 Yamazaki et al.
`2003/0146693 A1* 8, 2003 Ishihara et al. .............. 313,504
`2003/O151355 A1
`8, 2003 Hosokawa
`2003,0168992 A1
`9/2003 Noguchi et al.
`2003/0193056 Al 10/2003 Takayama et al.
`
`94
`
`
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`CN
`
`1434.668 A
`
`8, 2003
`
`(Continued)
`OTHER PUBLICATIONS
`
`Related U.S. Appl. No. 1 1/235,579, filed: Sep. 26, 2005: Inventors:
`Tomoyuki Shirasaki et al. Title: Display Panel.
`(Continued)
`Primary Examiner Aaron Williams
`(74) Attorney, Agent, or Firm Frishauf, Holtz, Goodman &
`Chick, PC
`s
`
`(57)
`
`ABSTRACT
`
`A display panel includes a transistor array Substrate which
`has a plurality of transistors including at least a driving tran
`sistor, and a plurality of pixel electrodes electrically con
`nected to the driving transistor of the plurality of transistors.
`A plurali
`flight
`itting 1
`ided on the pixel
`plurality of light-emitting ayers are provided on the pixe
`electrodes. A counter electrode is provided on the light-emit
`ting layers. Each of a plurality of interconnections is arranged
`between the pixel electrodes adjacent to each other and elec
`trically connected to the counter electrode.
`
`21 Claims, 21 Drawing Sheets
`
`-23g
`
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`US 7,498.733 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`2005/0073264 A1* 4/2005 Matsumoto .............. 315/169.3
`2005, OO88086 A1* 4, 2005 Park et al. ...
`... 313,506
`2005/0258741 A1* 11/2005 Kim et al. ................... 313,503
`2006/0066535 A1
`3, 2006 Shirasaki et al.
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`CN
`EP
`EP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`KR
`KR
`
`A
`A2
`A1
`
`1437.177
`1331 666
`1349 208
`8-330600
`2001-1950O8
`2002-352963
`2003-076327
`2003-186420
`2003-288994
`2003-317971
`2004-258172
`2006-004731
`2002-OOOO875
`10-2004-0051611
`
`8, 2003
`T 2003
`10, 2003
`12/1996
`T 2001
`12/2002
`3, 2003
`T 2003
`10, 2003
`11, 2003
`9, 2004
`1, 2006
`1, 2002
`6, 2004
`
`591574. A
`TW
`521336 A
`TW
`584.824. A
`TW
`594.628 A
`TW
`WOO3,O79441 A1
`WO
`WO WO 2004/019314 A1
`
`5, 2002
`2, 2003
`4/2004
`6, 2004
`9, 2003
`3, 2004
`
`OTHER PUBLICATIONS
`Japanese Office Action (and English translation thereof) dated Apr.
`30, 2008 issued in a counterpart Japanese Application in related U.S.
`Appl. No. 1 1/235,579.
`Chinese Office Action (and English translation thereof) dated Jun. 6.
`2008, issued in a counterpart Chinese Application.
`Chinese Office Action (and English translation thereof) dated Jun. 6.
`2008, issued in related U.S. Appl. No. 1 1/235,579 in counterpart
`Chinese Application No. 2005800 157971.
`Japanese Office Action (and English translation thereof) dated Jun.
`10, 2008, issued in a counterpart Japanese Application.
`Japanese Office Action (and English translation thereof) dated Sep. 9,
`2008, issued in a counterpart Japanese Application.
`* cited by examiner
`
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`U.S. Patent
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`Mar. 3, 2009
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`US 7,498,733 B2
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`U.S. Patent
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`Mar. 3, 2009
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`US 7,498,733 B2
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`U.S. Patent
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`Mar. 3, 2009
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`U.S. Patent
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`Mar. 3, 2009
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`
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`US 7,498,733 B2
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`Sheet 4 of 21
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`No.t:
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`

`U.S. Patent
`
`Mar. 3, 2009
`
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`US 7,498,733 B2
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`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 6 of 21
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`US 7,498,733 B2
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`

`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 7 of 21
`
`US 7,498,733 B2
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`SAMSUNG EX. 1015 - 9/35
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`

`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 8 of 21
`
`US 7,498,733 B2
`
`SELECTION PERIOD
`OF SUB-PIXELS
`Pi, 1 TO Pin
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME
`
`
`
`LIGHT EMISSION
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`
`VOLTAGE LEVEL
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`
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`P1, 1 TOP1,n
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`PIXELSF. To Pi.1,
`
`LIGHT EMISSION
`
`FIG.8
`
`SAMSUNG EX. 1015 - 10/35
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`

`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 9 of 21
`
`US 7,498,733 B2
`
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`SAMSUNG EX. 1015 - 11/35
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`

`

`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 10 of 21
`
`US 7,498,733 B2
`
`SELECTION PERIOD
`OF SUB-PXELS
`LIGHTEMISSION
`Pi, 1 TOP, n
`PERIOD OF
`PRECEDING FRAME
`LIGHT EMISSION PERIOD
`OF SUB-PXELS
`OF GIVEN FRAME OF
`Pi, TO Pin
`SUB-PIXELSP, 1 TOP,
`
`VOLTAGE LEVEL
`OF SCAN LINE X
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`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
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`s
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`: LIGHT EMISSION
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`PERIOD OF
`:
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`QF SUBPXELS
`Pi.1, 1 TOP1, n
`: ----
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`FIG.O
`
`SAMSUNG EX. 1015 - 12/35
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`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 11 of 21
`
`US 7,498,733 B2
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`FIG.11
`
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`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 12 of 21
`
`US 7,498,733 B2
`
`32-NCH PANEL
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`U.S. Patent
`
`Mar. 3, 2009
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`Sheet 13 of 21
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`US 7,498,733 B2
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`
`SAMSUNG EX. 1015 - 15/35
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`U.S. Patent
`
`Mar. 3, 2009
`
`Sheet 14 of 21
`
`US 7,498,733 B2
`
`40-NCH PANEL
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`FIG.14
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`U.S. Patent
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`Mar. 3, 2009
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`Sheet 15 of 21
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`US 7,498,733 B2
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`1.0x107
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`SAMSUNG EX. 1015 - 17/35
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`U.S. Patent
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`Mar. 3, 2009
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`Sheet 16 of 21
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`US 7,498,733 B2
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`SAMSUNG EX. 1015 - 18/35
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`U.S. Patent
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`Mar. 3, 2009
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`Sheet 17 of 21
`
`US 7,498,733 B2
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`SAMSUNG EX. 1015 - 19/35
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`U.S. Patent
`
`Mar. 3, 2009
`
`US 7,498,733 B2
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`Sheet 18 of 21
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`U.S. Patent
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`Mar. 3, 2009
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`Sheet 19 0f 21
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`US 7,498,733 B2
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`U.S. Patent
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`Mar. 3, 2009
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`Sheet 20 of 21
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`US 7,498,733 B2
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`SAMSUNG EX. 1015 - 22/35
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`U.S. Patent
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`Mar. 3, 2009
`
`Sheet 21 of 21
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`US 7,498,733 B2
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`US 7,498,733 B2
`
`1.
`DISPLAY PANEL
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`2
`resistance of the counter electrode is high, the Voltage of the
`counter electrode cannot become uniform in a plane. Hence,
`the Voltage level difference becomes conspicuous in a plane.
`More specifically, since the counter electrode is formed on the
`entire Surface as a common electrode, the light emission
`intensity varies between the organic electroluminescent ele
`ments even if a voltage of predetermined level is applied to all
`Sub-pixel electrodes. For this reason, the light emission inten
`sity is not uniform in a plane.
`
`BRIEF SUMMARY OF THE INVENTION
`
`The present invention has been made to solve the above
`described problem, and has as its object to make it possible to
`uniform the Voltage of the counter electrode as much as
`possible in a plane even when the counter electrode is thin.
`A display panel according to a first aspect of the present
`invention comprises:
`a transistor array Substrate which has a plurality of transis
`tors including at least driving transistors;
`a plurality of pixel electrodes which are electrically con
`nected to said plurality of driving transistors of said plurality
`of transistors;
`a plurality of light-emitting layers each of which is pro
`vided on each of the pixel electrodes:
`a counter electrode which is provided on the light-emitting
`layers; and
`a plurality of interconnections each of which is arranged
`between the pixel electrodes adjacent to each other and elec
`trically connected to the counter electrode.
`A display panel according to a second aspect of the present
`invention comprises:
`a transistor array Substrate which has a plurality of transis
`tors including driving transistors;
`a plurality of pixel electrodes which are electrically con
`nected to the driving transistors of said plurality of transistors;
`a plurality of light-emitting layer each of which is provided
`on each of the pixel electrodes:
`a counter electrode which is provided on the light-emitting
`layer; and
`a plurality of interconnections which is formed from a
`conductive layer different from a conductive layer serving as
`the pixel electrode, a layer serving as sources and drains of
`said plurality of transistors, and a layer serving as gates,
`arranged between the pixel electrodes adjacent to each other,
`and connected to the counter electrode.
`A display panel according to a third aspect of the present
`invention comprises:
`a plurality of pixel electrodes;
`a plurality of light-emitting layers which are provided on
`said plurality of pixel electrodes:
`a counter electrode which is provided on each of said
`plurality of light-emitting layers;
`a plurality of driving transistors which are electrically con
`nected to said plurality of pixel electrodes, respectively;
`a plurality of Switch transistors each of which Supplies a
`write current to a drain-to-source path of corresponding one
`of said plurality of driving transistors;
`a plurality of holding transistors each of which holds a gate
`Voltage of corresponding one of said plurality of driving
`transistors;
`a plurality of common interconnection each of which is
`arranged between adjacent two of said plurality of pixel elec
`trodes and electrically connected to the counter electrode; and
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is based upon and claims the benefit of
`priority from prior Japanese Patent Application No. 2004
`283963, filed Sep. 29, 2004, the entire contents of which are
`incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
`The present invention relates to a display panel using a
`light-emitting element as a Sub-pixel.
`2. Description of the Related Art
`As described in Jpn. Pat. Applin. KOKAI Publication No.
`8-330600, an organic electroluminescent element serving as a
`light-emitting element has a layered structure in which an
`anode, electroluminescent layer (to be referred to as an EL
`layer hereinafter), and cathode are stacked on a Substrate in
`this order. When a voltage is applied between the anode and
`cathode, holes and electrons are injected in the EL layer so
`electroluminescence occurs in the EL layer. An electrolumi
`nescent element whose Substrate and Substrate-side elec
`trodes are designed to be optically transparent so that light
`from the EL layer exits from the substrate with the EL layer is
`called a bottom emission type. On the other hand, an elec
`troluminescent element designed to output light from the EL
`layer from the opposite side of the substrate with the EL layer
`is called a top emission type.
`In a display panel of active matrix driving type, one or a
`plurality of thin-film transistors are provided per 1-dot sub
`pixel. The thin-film transistors cause an organic electrolumi
`nescent element to emit light. In a display panel described in,
`e.g., Jpn. Pat. Appln. KOKAI Publication No. 8-330600, two
`thin-film transistors are provided for each Sub-pixel. In manu
`facturing the display panel of active matrix driving type, a
`transistor array Substrate is prepared by patterning thin-film
`transistors for each Sub-pixel. After that, an organic electrolu
`minescent element is patterned on the Surface of the transistor
`array Substrate in correspondence with each Sub-pixel. The
`organic electroluminescent elements are patterned after the
`thin-film transistors because the temperature in patterning the
`thin-film transistors is higher than the heatproof temperature
`of the organic electroluminescent elements.
`The thin-film transistors are patterned for each sub-pixel.
`Hence, the plurality of organic electroluminescent elements
`are patterned in a matrix Such that the lower electrode (e.g.,
`the anode) to be connected to the thin-film transistors is
`formed independently for each sub-pixel. On the other hand,
`the counter electrode (e.g., the cathode) is formed on the
`entire Surface as a common electrode shared by all organic
`electroluminescent elements.
`In the above-described apparatus, the EL layers may be
`damaged by thermal/chemical factors during formation of the
`counter electrode. To Suppress damage to the EL layers, the
`formation time of the counter electrode is shortened as much
`as possible. However, when the formation time of the counter
`electrode is short, the counter electrode becomes thin. When
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`organic electroluminescent elements have the top emission
`structure, the counter electrode is preferably made as thin as
`possible such that attenuation of light emitted from the EL
`layers during passing through the counter electrode is mini
`mized as much as possible.
`However, when the counter electrode is made thin, the
`sheet resistance of the counter electrode increases. When the
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`a plurality of signal lines each of which is electrically
`connected to the Switch transistor while being arranged with
`out overlapping the common interconnection.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
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`can be made thinner, in a top emission structure, light emitted
`from the organic EL layer hardly attenuates while passing
`through the counter electrode.
`The common interconnections formed under the counter
`electrode are patterned independently of the gates, Sources,
`and drains of transistors. For this reason, the common inter
`connections can be thick and have a low resistance. Hence,
`the voltage of the counter electrode can be uniformed in a
`plane.
`The best mode for carrying out the present invention will be
`described below with reference to the accompanying draw
`ing. Various kinds of limitations which are technically pref
`erable in carrying out the present invention are added to the
`embodiments to be described below. However, the spirit and
`scope of the present invention are not limited to the following
`embodiments and illustrated examples. In the following
`description, the term “electroluminescence will be abbrevi
`ated as EL.
`Planar Layout of Display Panel
`FIG. 1 is a schematic plan view showing a pixel 3 of a color
`display panel 1 which is operated by the active matrix driving
`method. In the display panel 1, a 1-dot red sub-pixel Pr, 1-dot
`green sub-pixel Pg, 1-dot blue sub-pixel Pb are arrayed adja
`cent in the horizontal direction in correspondence with one
`pixel 3. In the display panel 1, the pixels 3 are arrayed in a
`matrix. The sub-pixels Pr, Pg, and Pb are arrayed in the
`vertical direction (column direction) such that sub-pixels of
`one column are of the same color. The red sub-pixel Pr, green
`sub-pixel Pg, and blue sub-pixel Pb are repeatedly arranged in
`the horizontal direction (row direction) in this order. The
`sub-pixels Pr, Pg, and Pb arearrayed in a matrix all over. More
`specifically, the sub-pixels Pr, Pg, and Pb corresponding to m
`(m is a natural number, m22) dots are arrayed in the vertical
`direction all over while the sub-pixels Pr, Pg, and Pb corre
`sponding to n (n is an integer multiple of 3) dots are arrayed
`in the horizontal direction. In the following description, an
`arbitrary one of the red sub-pixel Pr, green sub-pixel Pg, and
`blue sub-pixel Pb is represented by a sub-pixel P. The descrip
`tion of the sub-pixel Papplies to all the red sub-pixel Pr, green
`sub-pixel Pg, and blue sub-pixel Pb. The first subscript added
`to the sub-pixel Prepresents the sequence from the top of the
`display panel 1, and the second Subscript represents the
`sequence from the left of the display panel 1. More specifi
`cally, let i bean arbitrary natural number of 1 to m, and be an
`arbitrary natural number of 1 to n. A sub-pixel P. is located
`on the ith row from the top and the jth column from the left.
`A signal line Yr runs along a column of the red Sub-pixels
`Pr in the vertical direction. A signal line Yg runs along a
`column of the green sub-pixels Pg in the vertical direction. A
`signal line Yb runs along a column of the blue sub-pixels Pb
`in the vertical direction. The signal line Yr Supplies a signal to
`all the red sub-pixels Pr of one column of pixels 3 in the
`Vertical direction. The signal line Yg Supplies a signal to all
`the green sub-pixels Pg of one column of pixels 3 in the
`Vertical direction. The signal line Yb Supplies a signal to all
`the blue sub-pixels Pb of one column of pixels 3 in the vertical
`direction. In the following description, the description of a
`signal line Y applies to all the signal lines Yr, Yg, and Yb. The
`Subscript added to the signal line Y represents the sequence
`from the left of the display panel 1. More specifically, a signal
`line Y, is the jth column from the left.
`A common interconnection 91 runs along each of the col
`umns of the red sub-pixels Pr, the columns of the green
`sub-pixels Pg, and the columns of the blue sub-pixels Pb in
`the Vertical direction. That is, one common interconnection
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`FIG. 1 is a plan view showing a pixel of a display panel 1;
`FIG. 2 is an equivalent circuit diagram of a sub-pixel P of
`the display panel 1;
`FIG. 3 is a plan view showing the electrodes of the sub
`pixel P:
`FIG. 4 is a sectional view taken along a line IV-IV in FIG.
`3:
`FIG. 5 is a sectional view taken along a line V-V in FIG.3:
`FIG. 6 is a sectional view taken along a line VI-VI in FIG.
`3:
`FIG. 7 is a schematic plan view showing the interconnec
`tion structure of the display panel;
`FIG. 8 is a timing chart for explaining a driving method of
`the display panel 1 shown in FIG. 7:
`FIG. 9 is a schematic plan view showing the interconnec
`tion structure of another display panel;
`FIG. 10 is a timing chart for explaining a driving method of
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`the display panel 1 shown in FIG. 9;
`FIG. 11 is a graph showing the current vs. Voltage charac
`teristic of a driving transistor 23 and organic EL element 20 of
`each sub-pixel;
`FIG. 12 is a graph showing the correlation between the
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`maximum Voltage drop and an interconnection resistivity
`p/sectional area S of a feed interconnection 90 and common
`interconnection 91 of a 32-inch display panel 1;
`FIG. 13 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec
`tion 90 and common interconnection 91 of the 32-inch dis
`play panel 1;
`FIG. 14 is a graph showing the correlation between the
`maximum Voltage drop and the interconnection resistivity
`p/sectional area S of the feed interconnection 90 and common
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`interconnection 91 of a 40-inch display panel 1;
`FIG. 15 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec
`tion 90 and common interconnection 91 of the 40-inch dis
`play panel 1;
`FIG. 16 is a schematic plan view of the pixel 3 including a
`red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb
`continuously arrayed in the horizontal direction of the display
`panel 1;
`FIG. 17 is a plan view showing the electrodes of the sub
`pixel P shown in FIG. 16;
`FIG. 18 is a sectional view taken along a line XVIII-XVIII
`in FIG. 17:
`FIG. 19 is a sectional view taken along a line XIX-XIX in
`FIG. 17:
`FIG. 20 is a schematic plan view showing the interconnec
`tion structure of a display panel of a modification; and
`FIG. 21 is a schematic plan view showing the interconnec
`tion structure of another display panel of the modification.
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`DETAILED DESCRIPTION OF THE INVENTION
`
`According to the present invention, the counter electrode
`and common interconnections are connected. For this reason,
`even when the counter electrode itself is made thin and has a
`high resistance, the Voltage of the counter electrode can be
`uniformed in a plane. In addition, since the counter electrode
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`91 runs in the vertical direction in correspondence with one
`column of the sub-pixels P in the vertical direction.
`One scan line X, one Supply line Z, and one feed intercon
`nection 90 run in the horizontal direction in correspondence
`with one row of the pixels 3 in the horizontal direction. When
`viewed from the upper side, the feed interconnection 90 over
`laps the supply line Z. The subscript added to the scan lineX
`represents the sequence from the top of the display panel 1.
`The subscript added to the supply line Z represents the
`sequence from the top of the display panel 1. More specifi
`cally, a scan line X, is the ith row from the top, and a Supply
`line Z, is the ith row from the top.
`The color of each the sub-pixels Pr, Pg, and Pb is deter
`mined by the color of light emitted from an organic EL
`element 20 (for example, FIG. 2) (to be described later).
`When the entire display panel 1 is viewed from the upper side,
`a plurality of sub-pixel electrodes 20a which are anodes of the
`EL elements 20 are arrayed in a matrix. The 1-dot sub-pixel P
`is determined by one sub-pixel electrode 20a. In the entire
`display panel 1, the columns of the sub-pixel electrodes 20a
`are arrayed along one side of signal lines Y to Y, as shown
`in FIG. 7 or 9. The total number of columns of sub-pixel
`electrodes 20a in the vertical direction is n. Each sub-pixel
`electrode 20a is surrounded by the common interconnections
`91 on both sides in the horizontal direction. For this reason,
`the number of common interconnections 91 is (n+1). As will
`be described later in detail, the common interconnection 91 of
`the kth column (2sksn+1) covers transistors 22 and 23 of
`the sub-pixels P of the (k-1) th column when viewed from the
`upper side.
`Circuit Arrangement of Sub-Pixel
`The circuit arrangement of the sub-pixels Pr, Pg, and Pb
`will be described next with reference to FIG. 2. FIG. 2 is an
`equivalent circuit diagram of the sub-pixel P. of the ith row
`and jth column.
`All the sub-pixels Pr, Pg, and Pb have the same arrange
`ment. The organic EL element 20, first to three N-channel
`amorphous silicon thin-film transistors (to be simply referred
`to as transistors hereinafter) 21, 22, and 23, and a capacitor 24
`are provided for the 1-dot sub-pixel P. The first transistor 21
`will be referred to as the switch transistor 21, the second
`transistor 22 will be referred to as the holding transistor 22,
`and the third transistor 23 will be referred to as the driving
`transistor 23 hereinafter.
`In the switch transistor 21, a source 21s is electrically
`connected to the signal line Y. A drain 21d is electrically
`connected to the sub-pixel electrode 20a of the organic EL
`element 20, a source 23s of the driving transistor 23, and an
`upper electrode 24B of the capacitor 24. A gate 21g is elec
`trically connected to a gate 22g of the holding transistor 22
`and the scan line X.
`In the holding transistor 22, a source 22s is electrically
`connected to a gate 23g of the driving transistor 23 and a
`lower electrode 24A of the capacitor 24. A drain 22d is elec
`trically connected to a drain 23d of the driving transistor 23
`and the Supply line Z. The gate 22g is electrically connected
`to the gate 21g of the switch transistor 21 and the scan line X.
`In the driving transistor 23, the source 23s is electrically
`connected to the sub-pixel electrode 20a of the organic EL
`element 20, the drain 21d of the Switch transistor 21, and the
`upper electrode 24B of the capacitor 24. The drain 23d is
`electrically connected to the drain 22d of the holding transis
`tor 22 and the supply line Z. The gate 23g is electrically
`connected to the source 22s of the holding transistor 22 and
`the lower electrode 24A of the capacitor 24.
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`A counter electrode 20c (one continuous common counter
`electrode or a plurality of divided counter electrodes) serving
`as the cathode of the organic EL element 20 is electrically
`connected to the common interconnection 91. The counter
`electrode 20c is a common electrode shared by all the sub
`pixels Pr, Pg, and Pb. This will be described later in detail.
`In all the red sub-pixels Pr arrayed in a column in the
`vertical direction, the sources 21s of the switch transistors 21
`are electrically connected to the common signal line Yr. In all
`the green Sub-pixels Pg arrayed in a column in the vertical
`direction, the sources 21s of the Switch transistors 21 are
`electrically connected to the common signal line Yg. In all the
`blue sub-pixels Pb arrayed in a column in the vertical direc
`tion, the sources 21s of the switch transistors 21 are electri
`cally connected to the common signal line Yb.
`In all the sub-pixels Pr, Pg, and Pb arrayed in one row in the
`horizontal direction, the gates 21g of the switch transistors 21
`are electrically connected to the common scan line X. The
`gates 22g of the holding transistors 22 are electrically con
`nected to the common scan line X.
`The planar layout of the sub-pixel P will be described with
`reference to FIG. 3. FIG. 3 is a plan view mainly showing the
`electrodes of the sub-pixel P. For the illustrative convenience,
`FIG. 3 does not illustrate the sub-pixel electrode 20a and
`counter electrode 20c of the organic EL element 20.
`As shown in FIG. 3, when viewed from the upper side, the
`Switch transistor 21 is arranged along the signal line Y. The
`holding transistor 22 is arranged along the scan line X. The
`driving transistor 23 is arranged along the adjacent signal line
`Y.
`When a focus is placed on only the switch transistors 21 of
`all the sub-pixels Pr, Pg, and Pb in the entire display panel 1
`viewed from the upper side, the plurality of switch transistors
`21 are arrayed in a matrix. When a focus is placed on only the
`holding transistors 22 of all the sub-pixels Pr, Pg, and Pb, the
`plurality of holding transistors 22 are arrayed in a matrix.
`Whena focus is placed on only the driving transistors 23 of all
`the sub-pixels Pr, Pg, and Pb, the plurality of driving transis
`tors 23 are arrayed in a matrix.
`In the columns of the red sub-pixels Pr, the columns of the
`green Sub-pixels Pg, and the columns of the blue Sub-pixels
`Pb in the vertical direction, the plurality of holding transistors
`22 arrayed in the vertical direction are covered with the com
`mon interconnections 91. In the columns of the red sub-pixels
`Pr, the columns of the green sub-pixels Pg, and the columns of
`the blue sub-pixels Pb in the vertical direction, the plurality of
`driving transistors 23 arrayed in the vertical direction are
`covered with the common interconnections 91. Each holding
`transistor 22 may be covered with the common interconnec
`tion 91 entirely or partially by making the common intercon
`nection 91 narrower.
`Layer Structure of Display Panel
`The layer structure of the display panel 1 will be described
`with reference to FIGS. 4 to 6. FIG. 4 is a sectional view taken
`along a line IV-IV in FIG. 3. FIG. 5 is a sectional view taken
`along a line V-V in FIG. 3. FIG. 6 is a sectional view taken
`along a line VI-VI in FIG. 3. FIG.3 shows the 1-dot sub-pixel
`P. FIGS. 4 to 6 show the sub-pixels P of