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`[19]
`5,847,577
`[11] Patent Number:
`United States Patent
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`
`
`[45] Date of Patent:
`*Dec. 8, 1998
`Trimberger
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`US005847577A
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`
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`[54] DRAM MEMORY CELL FOR
`
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`PROGRAMMABLE LOGIC DEVICES
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`[75]
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`Inventor: Stephen M. Trimberger, San Jose,
`Calif.
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`[73] Assignee: XilinX, Inc., San Jose, Calif.
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`[ * ] Notice:
`The term of this patent shall not extend
`
`
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`
`
`beyond the expiration date of Pat. No.
`5,581,198.
`
`
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`
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`[21] Appl. No.: 758,286
`[22]
`Filed:
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`[63]
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`NOV. 1, 1996
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`Related US. Application Data
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`Continuation—in—part of Ser. No. 394,092, Feb. 24, 1995, Pat.
`No. 5,581,198.
`
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`
`[51]
`Int. Cl.6 ............................ H03K 19/177; G11C 7/00
`[52] US. Cl.
`.............................. 326/38; 326/41; 365/228;
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`711/106
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`[58] Field Of Search ........................ 326/38—40; 365/222,
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`365/228, 230.03, 230.05, 149; 711/100,
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`106, 161—162
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`[56]
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`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`8/1993 Freeman .
`Re. 34,363
`
`
`
`
`...................... 340/1725
`2/1975 Yamada et al.
`3,866,182
`
`
`
`
`
`
`
`365/228
`4,366,560 12/1982 McDermott et al
`
`
`
`
`
`1/1987 Hartung .................................. 364/200
`4,638,425
`
`
`
`
`
`4,642,487
`2/1987 Carter.
`
`
`
`7/1987 Sakurai et al.
`.......................... 365/222
`4,682,306
`
`
`
`
`
`
`11/1987 Carter .................. 365/94
`4,706,216
`
`
`
`
`
`
`6/1988 Hsieh ................
`365/203
`4,750,155
`
`
`
`
`
`6/1990 Matsumura et al.
`365/187
`4,935,896
`
`
`
`
`
`
`5,051,887
`9/1991 Berger et al.
`........................... 364/200
`
`
`
`
`
`
`.
`2/1993 El Gamal et al.
`5,187,393
`
`
`
`
`
`5,270,967 12/1993 Moazzami et al.
`................ 365/230.06
`
`
`
`
`
`
`2/1994 Hollerbauer
`............................ 395/425
`5,283,885
`
`
`
`
`
`12/1994 Wahlstrom ................................ 326/38
`5,375,086
`
`
`
`
`
`5,450,608
`9/1995 Steele ............
`395/800
`
`
`
`
`
`
`5,581,198 12/1996 Trimberger
`...... 326/39
`
`
`
`
`
`
`1/1997 Freeman .................................. 365/222
`5,594,698
`
`
`
`
`
`
`309
`
`
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`
`R. Sedgewick, “Algorithms”, pp. 283—284, Addison—Wes-
`
`
`ley, 1983.
`
`
`
`
`
`R. Sedgewick, “Algorithms”, pp. 295—303, Addison—Wes-
`
`
`ley, 1983.
`
`
`
`
`
`
`
`J .F. Wakerly, “Digital Design Principles and Practices” pp.
`34—44, Prentice Hall, 1990.
`
`
`
`
`
`
`
`
`
`
`
`
`Bradley Felton and Neil Hastie, “2.6 Configuration Data
`
`
`
`
`
`
`Verification and the Integrity Checking of SRAM—based
`
`
`
`
`
`
`FPGAs” GEC Plessey Semiconductors, FPGAs, W.R.
`
`
`
`
`
`
`
`Moore & W. Luk (eds.), 1991, Abingdon EE&C Books, 15
`
`
`
`
`
`
`
`Harcourt Way, Abingdon, 0X14 INV, UK, pp. 54—60.
`
`
`
`
`
`
`
`J .F. Wakerly, “Digital Design, Principles and Practices”, pp.
`255—257, Prentice Hall, 1989.
`
`
`
`
`“Semiconductor Memories”, B. Prince, 2nd Edition, pp.
`
`
`
`
`
`31—39 and pp. 654—655, 1991.
`
`
`
`
`
`
`
`
`
`
`
`
`Primary Examiner—Jon Santamauro
`
`
`
`
`
`
`
`
`
`
`Attorney, Agent, or Firm—Anthony C. Murabito; Wagner
`Murabito & Hao; Jeanette S. Harms
`
`
`
`
`
`
`ABSTRACT
`[57]
`
`
`
`
`
`
`
`
`
`Aplurality of DRAM cells are used to store the state of the
`
`
`
`
`
`
`programmable points in a programmable logical device
`
`
`
`
`
`
`
`(e.g., a field programmable gate array or FPGA). An indi-
`
`
`
`
`
`
`
`
`vidual DRAM cell is used in conjunction With each pro-
`
`
`
`
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`
`
`grammable interconnect point (PIP) Within the FPGA to
`
`
`
`
`
`
`
`
`
`hold a logical state indicating the connectivity state of the
`
`
`
`
`
`
`
`
`
`PIP. During a refresh cycle, each DRAM memory cell is
`loaded With its current logical state in order to maintain this
`
`
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`
`state Within the PIP. An information store contains duplicate
`
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`data for each DRAM cell and this duplicate data is supplied
`
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`and read during the refresh cycle in order to provide each
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`
`DRAM cell With its proper logical state. In this manner, the
`
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`
`
`
`refresh cycle does not alter the logic configuration of its
`associated FPGA DRAM cell. The information store can be
`
`
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`a plurality of DRAM cells or the information store can be of
`
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`non-volatile memory,
`for instance,
`read only memory
`
`
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`
`
`(ROM), programmable ROM (PROM), erasable PROM
`
`
`
`
`
`(EPROM), electrically erasable PROM (EEPROM), or of
`
`
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`non-volatile magnetic storage.
`
`
`
`
`23 Claims, 5 Drawing Sheets
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`DATA
`
`
`REGISTER
`
`307
`
`/ 300
`
`
`ERROR
`
`DETECTION
`
`AND CORRECTION
`
`
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`
`
`4 4 4
`] DECOMPRESSIONL320
`
`[7777777‘]
`321
`
`
`
`] DECRYPTION L
`
`
`
`FPGAVVORH 1,350
`321a C’ DATA
`
`
`
`]
`
`DRAM
`
`
`
`310
`
`
`
`302
`DRAM
`
`
`LlN
`ADDREJESS
`
`
`1
`
`S‘s/fig?“
`ARRAY
`
`
`301
`
`
`
`ADDRESS
`
`
`SEQUENCER
`AND
`DECODER
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`
`306
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`308 72/ f
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`305
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`
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`DATA
`
`VALID
`
`
`GENERATOR
`
`
`
`
`
`303
`
` SHADOW
`.—
`
`
`
` FPGA
`
`
`Page 1 Ofll
`
`FLEX LOGIX EXHIBIT 1043
`
`FLEX LOGIX EXHIBIT 1043
`
`Page 1 of 11
`
`

`

`
`US. Patent
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`Dec. 8, 1998
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`
`Sheet 1 0f5
`
`5,847,577
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`° ' '
`
` ADDR
`
`|
`|
`I
`
`108
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`| |
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`|
`I
`
`o
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`
`FIG. 1
`
`PRIOR ART
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`DATA f 200
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`o o o
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`ADDR
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`Page 2 ofll
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`Page 2 of 11
`
`

`

`US. Patent
`
`Dec. 8, 1998
`
`Sheet 2 0f 5
`
`5,847,577
`
`
`Rm;onEEomn_§<Q
`
`com)95345%_mozmmZmo
`rHHHflHHLea;
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`ZOHHUmHmQ<H<Q
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`
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`Page 3 ofll
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`Page 3 of 11
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`

`

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`US. Patent
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`Dec. 8, 1998
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`Sheet 3 015
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`5,847,577
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`11
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`12
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`408
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`. -
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`.
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`414
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`406
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`OUT
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`'
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`415
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`401
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`FIG. 4
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`400
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`403
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`404
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`a
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`405
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`509
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`FIG. 5
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`Page 4 ofll
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`Page 4 of 11
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`US. Patent
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`Dec. 8, 1998
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`Sheet 4 0f5
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`5,847,577
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`TO MUX 520
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`621
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`
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`FIG6b
`
`620
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`><o
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`8535;:
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`FIG.6a 600
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`Page 5 ofll
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`Page 5 of 11
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`

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`US. Patent
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`Dec. 8, 1998
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`Sheet 5 0f5
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`5,847,577
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`72
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`11
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`I2
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`40°C
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`FIG. 7
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`II
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`12
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`400B
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`FIG. 8
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`Page 6 ofll
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`Page 6 of 11
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`

`

`5,847,577
`
`
`1
`DRAM MEMORY CELL FOR
`
`
`
`
`PROGRAMMABLE LOGIC DEVICES
`
`
`RELATED PATENT APPLICATIONS
`
`
`
`
`
`
`
`The present patent application is a continuation-in-part of
`
`
`
`
`
`
`
`
`
`patent application Ser. No. 08/394,092 filed Feb. 24, 1995,
`now US. Pat. No. 5,581,198, entitled “Shadow DRAM for
`
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`
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`
`
`
`
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`Programmable Logic Devices,” by Stephen Trimberger, and
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`assigned to the assignee of the present invention.
`BACKGROUND OF THE INVENTION
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`5
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`10
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`1. Technical Field
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`The invention relates to a field programmable gate array,
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`and more particularly, to a shadow memory circuit that is
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`adapted to effect and maintain selected interconnection of
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`various logic and other elements in a field programmable
`gate array.
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`15
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`20
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`25
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`30
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`35
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`45
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`Description of the Related Art
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`2. Afield programmable gate array (FPGA) is a program-
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`mable integrated circuit logic device that consists of a matrix
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`of configurable logic blocks (CLBs) embedded in a pro-
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`grammable routing mesh. The combined programming of
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`the CLBs and routing network define the function of the
`device. The device is referred to as an FPGA because the
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`array of CLBs contained on the device can be configured and
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`interconnected by the user in the user’s facility by means of
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`special hardware and software.
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`FPGAs are well known in the art. For example US. Pat.
`No. RE 34,363, reissued on 31 Aug. 1993, describes a
`
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`configurable logic array that includes a plurality of CLBs
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`interconnected in response to control signals to perform a
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`selected logic function, and in which a memory is used to
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`store the particular data used to configure the CLBs. US.
`Pat. No. 4,642,487, issued on 10 Feb. 1987, teaches a special
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`interconnect circuit for interconnecting CLBs in an FPGA
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`without using the general
`interconnect structure of the
`40
`FPGA. US. Pat. No. 4,706,216, issued on 10 Nov. 1987,
`
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`describes a configurable logic circuit that includes a config-
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`urable combinational logic element, a configurable storage
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`circuit, and a configurable output select logic circuit. US.
`Pat. No. 4,750,155, issued on 7 June 1988, describes a five
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`transistor memory cell for an FPGA that can be reliably read
`and written.
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`Each CLB can provide one or more of the functions
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`provided by an AND gate, flip-flop, latch, inverter, NOR
`gate, exclusive OR gate, as well as combinations of these
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`50
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`functions to form more complex functions. The particular
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`function performed by the CLB is determined by control
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`signals that are applied to the CLB from a control logic
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`circuit. The control logic circuit is formed integrally with,
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`and as part of, the integrated circuit on which the CLB is
`formed. If desired, control information can be stored and/or
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`generated outside of this integrated circuit and transmitted to
`the CLB. The actual set of control bits provided to each CLB
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`on the integrated circuit depends upon the functions that the
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`CLB and, more globally, the integrated circuit are to per-
`form.
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`Each CLB typically has a plurality of input and output
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`pins, and a set of programmable interconnect points (PIPs)
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`for each input and output pin. The general interconnect
`structure of the FPGA includes a plurality of interconnect
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`segments and a plurality of PIPs, wherein each interconnect
`segment is connected to one or more other interconnect
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`segments by programming an associated PIP. An FPGA also
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`2
`includes an access PIP that either connects an interconnect
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`segment to an input pin or an output pin of the CLB.
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`Because the PIPs in the FPGA are programmable, any
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`given output pin of a CLB is connectable to any given input
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`pin of any other desired CLB. Thus, a specific FPGA
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`configuration having a desired function is created by
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`selected generation of control signals to configure the spe-
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`cific function of each CLB in an FPGA,
`together with
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`selected generation of control signals to configure the vari-
`ous PIPs that interconnect the CLBs within the FPGA.
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`Each PIP typically includes a single pass transistor (i.e.
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`effectively a switch). The state of conduction, i.e. whether
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`the switch is opened or closed, is controlled by application
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`of the control signals discussed above to a transistor control
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`terminal, e.g. a gate. The programmed state of each pass
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`transistor is typically latched by a storage device, such as a
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`static random access memory (SRAM) cell 100, illustrated
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`in FIG. 1. As shown in FIG. 1, a high signal ADDR on
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`address line 102 identifies the SRAM cell to be programmed
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`by turning on an n-type pass transistor 104, thereby allowing
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`the desired memory cell state DATA to be transferred from
`the data line 101 to a latch 106. The state of the control
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`signal stored in the latch 106 determines whether a pass
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`transistor (PIP) 109 is turned on or off, thereby opening or
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`closing a path in the FPGA interconnect.
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`An SRAM cell
`is typically used as a storage device
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`because the SRAM cell reliably maintains its value as long
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`as power is supplied. However, as shown in FIG. 1, because
`SRAM cell 100 includes two inverters 107/108 and a pass
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`transistor 104, SRAM cell 100 requires significant area on
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`an integrated circuit. Typically, the larger the area needed to
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`implement a PIP, the fewer number of PIPs that can be fit
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`onto an integrated circuit.
`In view of the continuing trend to increase the number of
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`complex functions implemented by an FPGA, a need arises
`for a method to reduce the size of the memory cells used to
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`hold the program for the FPGA interconnect, thereby reduc-
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`ing the size of the FPGA and lowering its cost. Further,
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`smaller memory cells would permit larger capacity FPGAs
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`to be built than were previously possible.
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`A dynamic random access memory (DRAM) cell, which
`is much smaller than an SRAM cell, has previously not been
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`used in FPGAs for a number of reasons, including:
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`1. A DRAM cell is volatile and subject to alpha particle
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`upsets that can change the state stored in the cell;
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`2. A DRAM must be periodically refreshed. Sensing the
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`DRAM cell, for example to refresh the cell, destroys
`the current value in the cell; and
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`3. Nearby signals, or signals running over a DRAM cell,
`can affect the contents of the cell.
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`SUMMARY OF THE INVENTION
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`In accordance with the present invention, a plurality of
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`DRAM cells are used to store the state of the programmable
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`points in a programmable logical device (e.g., a field pro-
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`grammable gate array or FPGA). An individual DRAM cell
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`is used in conjunction with each programmable interconnect
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`point (PIP) within the FPGA to hold a logical state indicating
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`the connectivity state of the PIP. In one embodiment, the
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`information store is typically organized with the same num-
`ber of bits and words as there are FPGA DRAM cells within
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`the FPGA, e.g.
`there is a one-to-one correspondence
`between FPGA DRAM cells and the memory cells of the
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`information store. During a refresh cycle, each DRAM
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`memory cell is loaded with its current logical state in order
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`Page 7 of 11
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`3
`to maintain this state within the PIP. An information store
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`contains duplicate data for each DRAM cell and this dupli-
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`cate data is supplied and read during the refresh cycle in
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`order to provide each DRAM cell with its proper logical
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`state. In this manner, the refresh cycle does not alter the logic
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`configuration of its associated FPGA DRAM cell. The
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`information store can be a plurality of DRAM cells or the
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`information store can be of non-volatile memory,
`for
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`instance, read only memory (ROM), programmable ROM
`10
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`(PROM), erasable PROM (EPROM), electrically erasable
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`PROM (EEPROM), or of non-volatile magnetic storage.
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`The present invention significantly reduces area on the
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`FPGA compared to the area required by prior art memory
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`cells. Furthermore, the present invention also eliminates the
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`need for separate power and ground lines that support prior
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`art memory cells,
`thereby reducing the number of lines
`within the FPGA.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a schematic diagram of a prior art SRAM
`interconnect cell for an FPGA;
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`FIG. 2 is a schematic diagram of a DRAM interconnect
`cell for an FPGA;
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`FIG. 3 is a block schematic diagram of a DRAM inter-
`connect control and refresh circuit for an FPGA in accor-
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`dance with the present invention;
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`FIG. 4 is a schematic diagram of a prior art
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`configuration circuit for an FPGA;
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`FIG. 5 is a schematic diagram of a logic configuration
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`circuit for an FPGA in accordance with the present inven-
`tion;
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`FIGS. 6a and 6b are block schematic diagrams of alter-
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`native embodiments of a portion of a storage element circuit
`in accordance with the present invention;
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`FIG. 7 is a block schematic diagram of a logic configu-
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`ration circuit for an FPGA having a DRAM configuration
`element in accordance with the present invention; and
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`FIG. 8 is a block schematic diagram of another logic
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`configuration circuit for an FPGA having a DRAM configu-
`ration element in accordance with the present invention.
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`DETAILED DESCRIPTION OF THE DRAWINGS
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`FIG. 2 illustrates a DRAM cell 200 for an FPGA in
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`accordance with the present invention. As with SRAM cell
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`100 (FIG. 1), a high signal ADDR on an address line 202
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`turns on a first pass transistor 204,
`thereby allowing a
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`DRAM cell 200 to be programmed. The state stored by
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`DRAM cell 200 is set by a signal DATA supplied over a data
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`line 201. Specifically, if both signals DATA and ADDR are
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`high, then a capacitor 206 begins to charge. The charge
`stored in capacitor 206 sets the state of the control terminal
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`of the second pass transistor 209, thereby opening or closing
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`a path in the FPGA interconnect. Note that capacitor 206 is
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`implemented either as a separate circuit structure or as the
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`gate of second pass transistor 209.
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`The present invention significantly reduces area of the
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`FPGA compared to the area required by SRAM cell 100
`because DRAM cell 200 stores state information in capaci-
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`tor 206 (one device), whereas SRAM cell 100 stores state
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`information in latch 106 (four devices). DRAM cell 200 also
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`eliminates the need for separate power and ground lines (not
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`shown in FIG. 1) that support SRAM cell 100 in the prior art,
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`thereby reducing the number of lines within the FPGA.
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`In accordance with the present invention, a plurality of
`DRAM cells are used to control the FPGA interconnect
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`60
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`65
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`Page 8 ofll
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`logic
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`5,847,577
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`4
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`circuitry. Another information store (shadow memory) per-
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`forms a shadow memory function. The shadow memory can
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`be composed of volatile memory cells (e.g., DRAM cells) or
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`it can be composed of non-volatile memory cells. Example
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`non-volatile memory constitution of the shadow memory
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`includes read only memory (ROM), programmable ROM
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`(PROM), erasable PROM (EPROM), electrically erasable
`
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`PROM (EEPROM), or of non-volatile magnetic storage.
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`In one embodiment using DRAM as the shadow memory,
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`the shadow memory is typically organized with the same
`number of bits and words as there are DRAM interconnect
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`cells within the FPGA, i.e. there is a one-to-one correspon-
`dence between FPGA DRAM interconnect cells and shadow
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`DRAM memory cells.
`In this embodiment wherein the
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`shadow memory is DRAM memory, the shadow memory
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`cells are the same as DRAM cell 200 (FIG.2), with the
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`exception that pass transistor 209 is not required because the
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`shadow memory has no control function.
`As is well known to those in the art, while an SRAM cell
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`maintains the state of its contents as long as power is
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`supplied, a DRAM cell needs periodic refreshing.
`FIG. 3 illustrates a DRAM interconnect control and
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`refresh circuit 300 for an FPGA according to the present
`invention. A refresh cycle on a data word of the FPGA
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`interconnect DRAM includes the following steps:
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`1. Initially, a conventional address sequencer and decoder
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`303 (hereinafter “sequencer”) address a particular por-
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`tion of the shadow memory 301. In one embodiment
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`where the shadow memory is DRAM, the sequencer
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`and decoder 303 pulls one shadow memory address line
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`302 high to select one word of a shadow memory array
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`301. The contents of shadow memory array 301 for the
`current data word are sensed by a conventional sense
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`circuit 308, and read into a data register 309.
`In
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`embodiments of the present
`invention where the
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`shadow memory 301 is non-volatile, the conventional
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`sense amplifier 308 can be eliminated and data can be
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`written directly from memory 301 to the data register
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`309. If shadow memory can be read non-destructively,
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`the write back circuitry including buffer 306 can be
`eliminated.
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`2. The contents of data register 309 are written back into
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`the shadow memory array 301 via tri-state buffer 306
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`(after passing through error detection and correction
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`circuit 307) and these contents are also written into the
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`FPGA interconnect and logic DRAM (hereinafter
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`FPGA DRAM) 310 via data line 311 to refresh FPGA
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`DRAM 310. Shadow memory array 301 and FPGA
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`DRAM 310 are written to simultaneously,
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`independently, or at different intervals, as desired. A
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`preferred embodiment of the present invention pro-
`vides a simultaneous shadow memory and interconnect
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`DRAM refresh sequence.
`In that embodiment,
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`sequencer 303 provides address information via lines
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`302 to shadow memory array 301 and via lines 312 to
`FPGA DRAM 310.
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`3. A low DATA VALID signal generated by a data valid
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`circuit 305 (data valid generator circuit), is provided to
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`AND gates 304 to force the signals on bus 312 low. The
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`DATA VALID signal is generated to remain low until
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`the data read out of shadow memory array 301 is
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`latched into data register 309, provided to error detec-
`tion and correction circuit 307, and propagated to the
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`memory cells in FPGA DRAM 310. A high DATA
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`VALID signal, provided to tri-state buffer 306, allows
`the transfer of the data held in data register 309 back
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`Page 8 of 11
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`

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`5,847,577
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`5
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`10
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`into shadow memory array 301. In one embodiment,
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`the DATA VALID signal is asserted in a predetermined
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`delay period after the current address is presented over
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`bus 312 by the address sequencer and decoder 303.
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`Thus, the generation of the DATA VALID signal takes
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`into consideration all internal timing and propagation con-
`siderations of the FPGA before FPGA DRAM 310 is
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`refreshed, thereby ensuring that correct data is available to
`FPGA DRAM 310. The DATA VALID signal ensures that
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`valid data is present over bus 321a during the write cycle
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`when the FPGA DRAM 310 is updated so that transient
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`garbage or invalid data is not written into the FPGA DRAM
`310. In this manner, the contents of FPGA DRAM 310 are
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`not destroyed during the interval when the cell is written. A
`15
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`high DATA VALID signal,
`indicating valid data, and a
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`corresponding high signal on one of address lines 302 forces
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`the output signal from AND gates 304 (i.e. on line 312) high,
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`thereby triggering a refresh cycle and allowing data to be
`written into the cells of FPGA DRAM 310. Note that a high
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`DATA VALID signal, provided to tri-state buffer 306, per-
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`mits transfer of the data held in data register 309 to shadow
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`memory array 301. It is appreciated that data valid to 306
`and 304 need not be simultaneous.
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`4. Sequencer 303 which controls the refresh sequence
`
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`continuously cycles through all addresses to ensure that
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`all DRAM interconnect cells are regularly refreshed.
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`It is appreciated that the shadow memory array 301, the
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`address sequencer 303, the data valid circuit 305 and gate
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`304 can be located off-chip in a separate die or device from
`30
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`the FPGA integrated circuit device that contains the FPGA
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`DRAM 310. In this case,
`the shadow memory array is
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`interfaced to communicate the duplicate data to a receiving
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`circuit (e.g., 308) during a refresh cycle. A number of well
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`known communication interface protocols and circuitry can
`be used for this alternative embodiment of the present
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`invention. In this alternative embodiment,
`the data valid
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`circuit 305 operates as discussed above and the address
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`sequencer and decoder 303 address the shared memory array
`301 as discussed above. Gate 304 presents the address to
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`receiving circuit 310 to refresh the FPGA DRAM 310 during
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`a valid period of the refresh cycle.
`invention, DRAM
`In one embodiment of the present
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`interconnect control and refresh circuit 300 includes an error
`
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`detection and correction circuit 307 that minimizes data
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`integrity problems associated with alpha particle hits and
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`other data disturbances of shadow memory array 301. Fur-
`ther description of the codes associated with this conven-
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`tional circuit is provided in “Digital Design Principles and
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`
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`Practices” by J.F. Wakerly, pages 34—44, 1990, which is
`
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`
`
`herein incorporated by reference. Although shown in con-
`nection with the preferred embodiment of the invention,
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`error detection and correction circuit 37 is considered
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`optional.
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`In contrast to FPGA DRAM 310 which provides a single
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`storage cell at each PIP and therefore is distributed through-
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`out the FPGA, shadow memory array 301 is preferably a
`standard DRAM array and can therefore be very dense.
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`Shadow memory array 301 is typically built far enough
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`away from lines that carry currents sufficiently high to cause
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`DRAM storage problems. In this manner, the contents of
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`shadow memory array 301 are not disturbed by any FPGA
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`signal, thereby avoiding upset problems and other related
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`interference that might affect the cells of shadow memory
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`In this way, any errors introduced into the
`array 301.
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`memory cells of FPGA DRAM 310, for example by the
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`routing of various signals through the general interconnect
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`of the FPGA, are readily corrected by shadow memory array
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`6
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`301 during the next refresh cycle. In another embodiment,
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`each cell of the shadow memory array is built at the same
`location as its associated FPGA DRAM interconnect cell.
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`One embodiment of the shadow memory array includes
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`DRAM cells because of the compact size of such arrays. In
`one embodiment of an FPGA in accordance with the
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`invention, a shadow memory array having approximately
`100,000 cells is used. In other embodiments of the invention,
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`the shadow memory array uses other technologies. For
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`example, the shadow memory array could be an SRAM,
`EPROM, EEPROM, flash EPROM, or ferroelectric array.
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`Although the shadow memory array is integrated onto the
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`same die as the FPGA in typical embodiments of the
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`invention, other shadow memory arrays are fabricated on a
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`separate die. Finally,
`in yet another embodiment of the
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`present invention, a shadow memory is provided for use
`with standard SRAM interconnect cells, such that these
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`interconnect cells are periodically refreshed to repair any
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`errors that resulted from factors such as power surges.
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`It is appreciated that more than one read and write cycle
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`can be applied to shadow memory 301 to collect enough bits
`for one full FPGA DRAM address.
`In this alternative
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`embodiment, a second register 350 is used to store the full
`FPGA DRAM word.
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`The present invention is also intended for other applica-
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`tions in programmable or configurable devices in which a
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`logic state is set and stored. For example, FIG. 4 illustrates
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`a prior art logic configuration circuit that includes a plurality
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`of storage elements 400 which store logic states A, B, C and
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`D. These logic states, which determine the logic function
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`performed by the circuit, are provided to a multiplexer 401
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`via lines 402, 403, 404 and 405. Multiplexer 401 consists of
`a first set of transistors 410, 411, 412, 413 that are controlled
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`by signal 11 provided on a first input line 407, and a second
`set of transistors 414, 415 that are controlled by a signal I2
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`provided on a second input line 408. The signals on first
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`input line 407 and second input line 408 select the logic state
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`bit that is the function value on output line 406. For example,
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`assume logic states B, C, and D are a logic “0” and logic
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`state A is a logic “1”. Multiplexer 401 selects logic state A
`when both signals 11 and I2 are a logic “1”, the function of
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`the circuit is an AND gate because the function produces a
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`logic “1” only when both inputs are a logic “1”, and the
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`circuit produces a logic “0” if either of the signals provided
`on input lines 407, 408 is otherwise.
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`Prior art storage elements 400 are typically SRAM cells
`and, as such, are relatively stable. However, as discussed
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`above, SRAM cells require considerable area on an inte-
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`grated circuit.
`As is known in the art, a DRAM cell cannot source a
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`current for a logic operation because drawing current from
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