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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`Commissioner for Patents
`United States Patent ’and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`www.uspto,gov
`
`Konda Technologies, Inc
`6278 GRAND OAK WAY
`SAN JOSE CA 95135
`
`In re Application of
`Konda Technologies Inc.
`Application No.: 16/202,067
`Filing Date: 27 November 2018
`Attorney Docket No..: V-0070US
`
`MAILED
`
`NOV 27 2019
`
`INTERNATIONAL PATENT LEGAL ADM.
`
`:
`:
`'
`
`DECISION
`
`This Decision is in response to the filing of “Petition To Withdraw the Prior Filed
`Petition on 11/27/2018 To Accept The Unintentionally Delayed Claim Under 35 U.S.C. 119(e),”
`in the United States Patent and Trademark Office on 17 September 2019.
`
`This application does not contain a delayed claim of benefit. A petition for the
`unintentionally delayed payment of the basic national fee under 37 CFR 1.137(a) was accepted
`in 12/601,275.
`
`Applicant’s request to withdraw the petition and refund the petition fee is GRANTED.
`
`/Erin P. Thomson/
`Erin P. Thomson
`
`Attorney Advisor
`International Patent Legal Administration
`571-272—3292
`
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`Electronic Acknowledgement Receipt
`
`“—
`
`——
`
`Title of Invention:
`
`VLSI Layouts of Fully Connected Generalized Networks
`
`
`
`——
`——
`
`Payment information:
`
`Submitted with Payment
`
`no
`
`File Listing:
`
`Document
`Number
`
`Document Descri
`
`tion
`
`p
`
`File Size(Bytes)/
`Message Digest
`218167
`
`Pages
`Multi
`Part /.zip (if appl.)
`
`0b95d
`
`Reissue dec filed in accordance with
`MPEP 1414
`
`VOO7OUS—aia0005.pdf
`
`eb6d66b02b0eb5f341153179cc12222cd75
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`Information:
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`IPR2020-00262
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`238878
`
`Preliminary Amendment
`
`VOO7OUS—PrelimAmend.pdf
`
`4el ldf3fe54386626cl 600c646245d90669 '
`7be9
`
`
`
`Information:
`
`Total Files Size (in bytes)
`
`457045
`
`This Acknowledgement Receipt evidences receipt on the noted date by the USPTO of the indicated documents,
`characterized by the applicant, and including page counts, where applicable. It serves as evidence of receipt similar to a
`Post Card, as described in MPEP 503.
`
`
`New Applications Under 35 U.S.C. 111
`If a new application is being filed and the application includes the necessary components for a filing date (see 37 CFR
`1.53(b)—(d) and MPEP 506), a Filing Receipt (37 CFR 1.54) will be issued in due course and the date shown on this
`Acknowledgement Receipt will establish the filing date of the application.
`
`National Stage of an International Application under 35 U.S.C. 371
`If a timely submission to enter the national stage of an international application is compliant with the conditions of 35
`U.S.C. 371 and other applicable requirements a Form PCT/DO/EO/903 indicating acceptance of the application as a
`national stage submission under 35 U.S.C. 371 will be issued in addition to the Filing Receipt, in due course.
`New International Application Filed with the USPTO as a Receiving Office
`If a new international application is being filed and the international application includes the necessary components for
`an international filing date (see PCT Article 11 and MPEP 1810), a Notification of the International Application Number
`and of the International Filing Date (Form PCT/RO/105) will be issued in due course, subject to prescriptions concerning
`national security, and the date shown on this Acknowledgement Receipt will establish the international filing date of
`the application.
`
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`Doc Code: REESDECL
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`Document Description: Reissue Declaration Filed In Accordance With MPEP 1414
`
`Under the Pa ‘EFWOl’k Reduction Act oi 1995, no ‘EFSO
`
`PTO/AiA/‘OS (06-12)
`Approved for use through 01/31/2020. OMB 0651-0033
`U.~S. Patent and Trademark Office; US. DEPARTMENT OF COMMERCE
`are reouired to respond to a coliection of informat
`unless it dis lavs a vaiid OMB controi number.
`3 Docket Number (Optional)
`
`REESSUE APPLECATEON DECLARATEQN BY THE ENVENTQR
`
`V-0070US
`
`hereby declare that:
`Each inventor’s residence and mailing address are stated below next to their name.
`believe l am the originai inventor or an original joint inventor of the subject matter which is described and claimed
`in patent number 852695523
`, granted% and for which a
`reissue patent is sought on the invention titled
`VLS' Layouts 0f Fully Cenneeied Generalized Networks
`
`the specification otwhich
`
`I: is attached hereto.
`
`was filed on 11/27/2018
`
`as reissue application number 1%..
`
`scope of original claims.
`
`The above—identified application was made or authorized to be made by me.
`
`3
`
`i hereby acknowiedge that any wiiifui false statement made in this deciaration is punishable under 18 U.S.C. 100’: by fine
`or imprisonment of not more than five (5) years, or both.
`
`believe the original patent to be wholly or partiy inoperative or invalid, for the reasons described
`below. (Check all boxes that apply.)
`
`[:1 by reason of a defective specification or drawing.
`
`2] by reason of the patentee claiming more or iess than he had the right to oiaim in the patent.
`
`I: by reason of other errors.
`
`iftne reissue is a broadening
`At least one error upon which reissue is based is described beiow.
`reissue, a ciaim that the appiication seeks to broaden must be identified:
`
`Because the patentee claimed more than he had the right to claim in the US Patent No.
`8,269,523, the scope of the original claim 1
`is narrowed by incorporating limitations of claim 3
`into original claim 1. Newly added independent claims 49 and 50 also do not broaden the
`
`
`
`{Page i (#21
`
`This collection oi intorrnation is required by 37 CFR‘ 1.175. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO
`to process) an application. Confidentiality is governed by 35 U,S.C. 122 and 37 CFR 1.11 and 1.‘i4. This coilection is estimated to take 30 minutes to complete,
`including gathering. preparing, and submitting the completed application form to the USPTCE. Time wiil vary depending upon the individual case. Any comments on
`the amount of time you require to complete this form andior suggestions for reducing this burden, should be sent to the Chief information Ofticer, U.S. Patent and
`Trademark Office, US. Department of Commerce, P.O. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THES
`ADDRESS. SEND To: Commissioner for Patents, P.O. Box 1450, Alexandria, VA 223134450.
`
`if you need assistance in completing the form, call 1n800-PTO~9199 and select option 2.
`
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`
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`U.~S. Pat
`Under the Pa ‘erwork Reduction Act oi 1995, no leis ‘ s are reouired to res and to a colie
`
`(REiSSUE APPLiCATiON DECLARATION BY THE lNVENTOR, page 2)
`
`PTOIAlAIOS {06-12}
`Approved for use through U‘i/Sl/ZOZO. 0?le 0651-0033
`
`t and Trademark Office '.S DEPARTMENTFOF COMMER "E
`'
`riformation unless
`dis lavs a vaiid
`.
`.
`Docket Number (Optionai)
`V_0070US
`
`
`
`Note: To appoint a power or“ attorney, use form PTO/AlA/81.
`
`Correspondence Address: Direct all communications about the appiication to:
`The address associated with Customer Number:
`I
`38139
`OR
`
`Firm or
`individuai Name
`
`--I-
`
`Country
`
`T‘ - Em‘“-
`
`I
`
`WARNING:
`Petitioner/applicant is cautioned to avoid submitting personal information in documents tiled in a patent appiication that may
`contribute to identity theft, Personai information such as social security numbers, bank account numbers. or credit card
`numbers (other than a check or credit card authorization form PTOu2038 submitted for payment purposes) is never required by
`the USPTO to support a petition or an applications
`ifthis type of personai information is included in documents submitted to
`the USPTO, petitioners/applicants should consider redacting such personal information from the documents before submitting
`them to the USPTO. Petitioner/applicant is advised that the record of a patent application is available to the pubiic after
`publication of the application (unless a non—publication request in compliance with 37 CFR 1.213(a) is made in the appiication)
`or issuance of a patent. Furthermore, the record from an abandoned application may also be avaiiable to the public if the
`application is referenced in a published application or an issued patent (see 37 CFR 1.14). Checks and credit card
`authorization forms PTO—2038 submitted for payment purposes are not retained in the application fiie and therefore are not
`pubiiciy availabie.
`
`I
`
`I
`
`
`
`Legai name of soie or first inventor (E.g., Given Name (first and middle (if any) and Family Name or Surname
`
`Venkat Konda
`
`inventor‘s Signature
`
`/Venkat Konda/
`
`. Date (Optionai)
`
`September 23, 2019
`
`Residence: City
`San Jose
`
`Mailing Address
`
`6278 Grand Oak Way
`
`
`
`
`State
`CA
`
`. Country
`USA
`
` Country
`
`USA
`
`
`
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`Privacy Act Statement
`
`The Privacy Act of 1974 (P.L. 93-579) requires that you be given certain information in connection
`with your submission of the attached form related to a patent application or patent. Accordingly,
`pursuant to the requirements of the Act, please be advised that: (1) the general authority for the
`collection of this information is 35 U.S.C. 2(b)(2); (2) furnishing of the information solicited is voluntary;
`and (3) the principal purpose for which the information is used by the US. Patent and Trademark
`Office is to process and/or examine your submission related to a patent application or patent. If you do
`not furnish the requested information, the US. Patent and Trademark Office may not be able to
`process and/or examine your submission, which may result in termination of proceedings or
`abandonment of the application or expiration of the patent.
`
`The information provided by you in this form will be subject to the following routine uses:
`
`1. The information on this form will be treated confidentially to the extent allowed underthe
`Freedom of Information Act (5 U.S.C. 552) and the Privacy Act (5 U.S.C 552a). Records from
`this system of records may be disclosed to the Department of Justice to determine whether
`disclosure ofthese records is required by the Freedom of Information Act.
`2. A record from this system of records may be disclosed, as a routine use, in the course of
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`4. A record in this system of records may be disclosed, as a routine use, to a contractor of the
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`5. A record related to an International Application filed under the Patent Cooperation Treaty in
`this system of records may be disclosed, as a routine use, to the International Bureau of the
`World Intellectual Property Organization, pursuant to the Patent Cooperation Treaty.
`6. A record in this system of records may be disclosed, as a routine use, to another federal
`agency for purposes of National Security review (35 U.S.C. 181) and for review pursuant to
`the Atomic Energy Act (42 U.S.C. 218(c)).
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`be used to make determinations about individuals.
`
`8. A record from this system of records may be disclosed, as a routine use, to the public after
`either publication of the application pursuant to 35 U.S.C. 122(b) or issuance of a patent
`pursuant to 35 U.S.C. 151. Further, a record may be disclosed, subject to the limitations of 37
`CFR 1.14, as a routine use, to the public ifthe record was filed in an application which
`became abandoned or in which the proceedings were terminated and which application is
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`issued patent.
`9. A record from this system of records may be disclosed, as a routine use, to a Federal, State,
`or local law enforcement agency, if the USPTO becomes aware of a violation or potential
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`In ‘17ie UnitedStates @atentflnd'Trad'emarfi,Ofiice
`
`Reissue Application
`
`:
`
`16/202,067
`
`Filed: November 27, 2018
`
`Parent US Patent No : 8,269,523
`
`Issued: September 18, 2012
`
`Parent Application No:
`
`12/601,275
`
`Filed: May 31, 2010
`
`Examiner
`
`: Ton, My Trang
`
`Group Art Unit: 3992
`
`Applicant(s): Venkat Konda
`
`Filed: November 27, 2018
`
`Title: VLSI Layouts of Fully Connected Generalized Networks
`
`10
`
`AMENDMENT ACCOMPANYING REISSUE APPLICATION RESUBMITTED
`
`PURSUANT TO 37 C.F.R. §1.173(B)
`
`San Jose, 2019 Sept 23, Mon
`
`Mail Stop Reissue
`
`Commissioner for Patents
`
`15
`
`PO. BOX 1450
`
`Alexandria, VA 22313-1450
`
`Dear Sir/Madam:
`
`20
`
`25
`
`For the above above-referenced reissue patent application, in view of the petition
`
`granted on August 19, 2019 that was filed in the parent Patent No. 8,269,523 for the
`
`entire delay in filing the basic national fee from the due date for the fee until the filing of
`
`a grantable petition under 37 CFR 1.137 was unintentional, applicant is now submitting a
`
`new “the reissue application declaration by the inventor”. Furthermore the Amendment
`
`submitted for the above-referenced reissue patent application filed on November 27, 2018
`
`which supposed to set forth applicant’s requested amendments to US. Patent No.
`
`Page 1 of 26
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`8,269,523 is non-compliant with 37 C.F.R. §l. 173(B) at least since the submitted claims
`
`are not identified with correct format.
`
`Accordingly applicant respectfully requests to disregard the amendment submitted
`
`on November 27, 2018 and consider this amendment. This Amendment accompanies the
`
`reissue patent application filed on November 27, 2018, and sets forth applicant’s
`
`requested amendments to US. Patent No. 8,269,523.
`
`Amendment to Specification is set forth on page 4.
`
`Amendments to the claims are set forth in the Listing ofthe Claims, which begins on
`
`Page 5. Originally issued claims 1, 2, 4, 7, ll, 16, 22, 24, 28, 33, 36, 39, 43 are amended.
`
`Originally issued claims 3, 5, 6, 8 - 10, 12 -14,15, 17 — 21, 23, 25 — 27,29 — 32, 34 — 35,
`
`37 — 38, 40 — 42, 44 - 48 are now cancelled. Originally issued claims are amended
`
`perfecting the claim language. But no new matter is added. Furthermore:
`
`Incorporated limitations of Claim 3 into Claim 1 and cancelled claim 3.
`
`Incorporated limitations of Claims 5 — 6 into Claim 4 and cancelled claims 5 — 6.
`
`Incorporated limitations of Claims 8 — 10 into Claim 7 and cancelled claims 8 — 10.
`
`Incorporated limitations of Claims 12 — 14 into Claim 11 and cancelled claims 12 — l4.
`
`Incorporated limitations of Claims l8, 19, 21, 22, and 47 into Claim 16 and cancelled
`
`claims l8, 19, 21, 22, and 47.
`
`Incorporated limitations of Claims 25 — 27 into Claim 24 and cancelled claims 25 — 27.
`
`Incorporated limitations of Claims 29 — 32 into Claim 28 and cancelled claims 29 — 32.
`
`Incorporated limitations of Claims 34 — 35 into Claim 33 and cancelled claims 34 — 35.
`
`Incorporated limitations of Claims 37 — 38 into Claim 36 and cancelled claims 37 — 38.
`
`Incorporated limitations of Claims 40 — 42 into Claim 39 and cancelled claims 40 — 42.
`
`Incorporated limitations of Claims 44 — 46 into Claim 43 and cancelled claims 44 — 46.
`
`10
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`15
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`20
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`New claims 49 and 50 are added both narrowing the original Claim 1 in different ways.
`
`Therefore, the claims 1, 2, 4, 7, ll, 16, 22, 24, 28, 33, 36, 39, 43, 49, 50 are pending in
`
`this reissue application following entry of this amendment.
`
`Remarks are set forth on page 25.
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`Amendments to the Specification
`
`Amendments to the specification are indicated below wherein matter to added is indicated
`
`by underlining and matter to be deleted is indicated in [brackets].
`
`Please replace the paragraph at column 1, lines 7-15, following the heading
`
`“CROSS REFERENCE TO RELATED APPLICATIONS” with the following:
`
`This application [is related to and] is an application for reissue of US. Patent No.
`
`8 269 523 which claims priority of the PCT Application Serial No. PCT / U808 / 64605
`
`10
`
`entitled "VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS"
`
`by Venkat Konda assigned to the same assignee as the current application, filed May 22,
`
`2008, [and] which in turn claims prionfl of the US. Provisional Patent Application Serial
`
`No. 60/ 940, 394 entitled "VLSI LAYOUTS OF FULLY CONNECTED
`
`15
`
`GENERALIZED NETWORKS" by Venkat Konda assigned to the same assignee as the
`
`current application, filed May 25, 2007.
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`LISTING OF THE CLAIMS
`
`This Claim listing sets forth all the claims that will be pending in this reissue application
`
`following entry of the present amendment.
`
`1.
`
`(Amended): An integrated circuit [device] comprising a plurality of sub-
`
`integrated circuit blocks and a [routing network] multi-stage network, and
`
`[Said] each sub-integrated circuit block of said plurality of sub-integrated circuit
`
`blocks comprising a plurality of inlet links and a plurality of outlet links; and
`
`[Said] m [routing network] multi-stage network comprising [of] a plurality of
`
`stages y [in] corresponding to each [said] sub-integrated circuit block of said pluralifl of
`
`sub-integrated circuit blocks, starting from [the lowest] stage [of] l to [the highest] stage
`
`[of] y, where yZl; and
`
`[Said routing network comprising] each stage of said pluralifl of
`
`stages y comprising a plurality of switches of size d X d , where d 2 2 [, in each said
`
`stage] and each [said] switch of said pluralifl of switches of size d X d having d inlet
`
`links and d outlet links; and
`
`[Said] M plurality of outlet links of [said] each sub-integrated circuit block o_f
`
`said pluralifl of sub-integrated circuit blocks are directly connected to said pluralifl of
`
`inlet links of said pluralig of switches of size d X d of its corresponding said [lowest]
`
`stage [of] l of said pluralifl of stages y , and said plurality of inlet links of [said] each
`
`sub-integrated circuit block of said pluralifl of sub-integrated circuit blocks are directly
`
`
`connected from said pluralifl of outlet links of said pluralifl of switches of size d X d of
`
`[its corresponding] said [lowest] stage [of] l of said pluralifl of stages y; and
`
`[said] each sub-integrated circuit block of said pluralifl of sub-integrated circuit
`
`blocks comprising a plurality of forward connecting links connecting from said pluralig
`
`o_f switches in [a lower] each stage of said pluralifl of stages y to said pluralifl of
`
`10
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`15
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`20
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`25
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`switches in [its] Q immediate succeeding [higher] stage of said pluralifl of stages y , and
`
`also comprising a plurality of backward connecting links connecting from said pluralifl
`
`o_f switches in [a higher] each stage of said pluralifl of stages y to said pluralifl of
`
`switches in [its] fl immediate [succeeding lower] preceding stage of said pluralifl of
`
`stages y, and
`
`[Said each sub-integrated circuit block comprising a plurality straight links in said
`
`forward connecting links from switches in said each lower stage to switches in its
`
`immediate succeeding higher stage and a plurality cross links in said forward connecting
`
`links from switches in said each lower stage to switches in its immediate succeeding
`
`higher stage, and further comprising a plurality of straight links in said backward
`
`connecting links from switches in said each higher stage to switches in its immediate
`
`preceding lower stage and a plurality of cross links in said backward connecting links
`
`from switches in said each higher stage to switches in its immediate preceding lower
`
`stage,]
`
`said plurality of sub-integrated circuit blocks arranged in a two-dimensional grid
`
`of a pluralim of rows and a pluralifl of columns, and
`
`said pluralifl of forward connecting links and said pluralifl of backward
`
`connecting links compriselsl a pluralifl of [said all] straight middle links [are] connecting
`
`from said pluralifl of switches of a first stage of said pluralifl of stages y in [each said] a
`
`first sub-integrated circuit block of said pluralifl of sub-integrated circuit blocks [are
`
`connecting] to said pluralifl of switches of an immediate succeeding or an immediate
`
`preceding stage of said first stage of said pluralifl of stages y in [the same] said first sub-
`
`integrated circuit block of said pluralifl of sub-integrated circuit blocks, and
`
`10
`
`15
`
`20
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`said pluralifl of forward connecting links and said pluralifl of backward
`
`connecting links compriselsl a pluralim of [said all] cross middle links [are] connecting
`
`25
`
`[as either vertical or horizontal links between switches in two different said sub-
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
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`integrated circuit blocks which are either placed vertically above or below, or placed
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`horizontally to the left or to the right,] from switches of said pluralifl of switches in a
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`stage of said pluralig of stages y in a first sub-integrated circuit block of said pluralifl of
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`sub-integrated circuit blocks to switches of said pluralifl of switches in a succeeding
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`stage or a preceding stage a first sub-integrated circuit block of said pluralifl of sub-
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`integrated circuit blocks wherein said pluralifl of cross middle links are either vertical
`tracks or horizontal tracks and
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`a pluralifl of said pluralifl of cross middle links in succeeding stages of said
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`pluralifl of stages
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`are connected alternately as vertical tracks and horizontal tracks
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`10
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`hereinafter “h
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`ercube to 010
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`”
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`and
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`[each said plurality of sub-integrated circuit blocks comprising same number of
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`said stages and] each sub-integrated circuit block of said pluralifl of sub-integrated
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`circuit blocks connected with said pluralifl of switches of size d X d of said pluralig of
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`stages y [said switches in each said stage,] regardless of the size of said pluralifl of rows
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`and size of said pluralim of columns of said two-dimensional grid [so that] wherein each
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`sub-integrated circuit block of said plurality of sub-integrated circuit [block with its
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`corresponding said stages and said switches in each stage] blocks connected with said
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`pluralifl of switches of size d X d of said pluralig of stages y is replicable in both
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`vertical direction or horizontal direction of said two-dimensional grid.
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`2.
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`(Amended): The integrated circuit [device] of claim 1,
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`said two-dimensional grid of said pluralifl of sub-integrated circuit blocks connected with
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`[their corresponding] said pluralifl of stages y [and said switches in each stage] is
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`scalable by any power of 2, and,
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`for each multiplication of 2 of [the] size of total said pluralim of sub-integrated
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`circuit blocks, by adding one more stage [of switches] to said pluralifl of stages and said
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`hypercube [layout] topology is extended and placed in m hypercube topology [format]
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`and [also] the cross middle links between said one more stage to said pluralifl of stages y
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`15
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`20
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`25
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
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`of switches of said pluralifl of switches are connected in m hypercube topology
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`[format] .
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`3.
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`4.
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`(Cancel claim 3)
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`(Amended): The integrated circuit [device] of claim [3] 1, wherein [said cross
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`links from switches in a stage said stages in one of said sub-integrated circuit blocks are
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`connecting to switches in the succeeding stage in another of said sub-integrated circuit
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`blocks so that said cross links are either vertical links or horizontal and vice versa, and
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`hereinafter such cross links are “shuffle exchange links”).] said pluralifl of cross middle
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`links between switches in any two same succeeding stages of said pluralifl of stages y fl
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`substantially of equal length in said integrated circuit: and
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`the shortest cross middle links of said pluralifl of cross middle links are
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`connected at stage 1 of said pluralifl of stages y and between switches of said pluralifl of
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`switches in two nearest neighboring said pluralig of sub-integrated circuit blocks: and
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`length of the cross middle links is doubled in each succeeding stage of said pluralifl of
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`stages y in either said vertical tracks or said horizontal tracks.
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`5.
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`6.
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`7.
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`(Cancel claim 5)
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`(Cancel claim 6)
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`(Amended): The integrated circuit [device] of claim [6] fl, wherein y 2 (log2 N) ,
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`whereN >1, [so that] wherein [the] length or width of the [horizontal] pluralifl of cross
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`middle links [shuffle exchange links] in [the highest] stage y is equal to half the [size]
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`length or width [of the horizontal size] of said two dimensional grid of said pluralifl of
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`sub-integrated circuit blocks [and the length of the vertical shuffle exchange links in the
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`highest stage is equal to half the size of the vertical size of said two dimensional grid of
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`sub-integrated circuit blocks,] and wherein d = 2 and either
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`10
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`15
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`20
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
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`Attorney Docket No. V-0070US
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`each stage of said pluralifl of stages in each sub-integrated circuit block of said
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`pluralifl of sub-integrated circuit blocks comprises only one switch of said pluralifl of
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`switches connecting said pluralifl of forward connecting links and each stage of said
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`pluralifl of stages in each sub-integrated circuit block of said pluralifl of sub-integrated
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`circuit blocks comprises only one switch of said pluralifl of switches connecting said
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`pluralifl of backward connecting links and said multi-stage network is rearrangeably
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`nonblocking for unicast Benes network: or
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`each stage of said pluralifl of stages in each sub-integrated circuit block of said
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`pluralifl of sub-integrated circuit blocks comprises at least two switches of said pluralifl
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`10
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`of switches connecting said pluralifl of forward connecting links and each stage of said
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`pluralifl of stages in each sub-integrated circuit block of said pluralifl of sub-integrated
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`circuit blocks comprises at least two switches of said pluralifl of switches connecting said
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`pluralifl of backward connecting links and said multi-stage network is strictly
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`nonblocking for unicast Benes network and is rearrangeably nonblocking for arbitram
`fan-out multicast Benes network or
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`15
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`each stage of said pluralifl of stages in each sub-integrated circuit block of said
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`pluralifl of sub-integrated circuit blocks comprises at least three switches of said pluralifl
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`of switches connecting said pluralifl of forward connecting links and each stage of said
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`pluralifl of stages in each sub-integrated circuit block of said pluralifl of sub-integrated
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`20
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`circuit blocks comprises at least three switches of said pluralifl of switches connecting
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`said pluralifl of backward connecting links and said multi-stage network is strictly
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`nonblocking for arbitrafl fan-out multicast Benes network.
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`8.
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`(Cancel claim 8)
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`25
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`9.
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`(Cancel claim 9)
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`10.
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`(Cancel claim 10)
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
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`11.
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`(Amended): The integrated circuit [device] of claim [6] fl, wherein y 2 (log2 N) ,
`
`whereN >1, [so that] wherein [the] length or width of the [horizontal] pluralifl of cross
`
`middle links [shuffle exchange links] in [the highest] stage y is equal to half the [size]
`
`length or width [of the horizontal size] of said two dimensional grid of said pluralifl of
`
`sub-integrated circuit blocks [and the length of the vertical shuffle exchange links in the
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`highest stage is equal to half the size of the vertical size of said two dimensional grid of
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`sub-integrated circuit blocks,]3fld
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`[said] each sub-integrated circuit block of said pluralifl of sub-integrated circuit
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`M further comprising a plurality of U-tum links within switches of said pluralifl of
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`m in each st_ag§ of said pluralifl of stages in each of said pluralifl of sub-integrated
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`circuit blocks[.] and wherein d = 2 and either
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`each stage of said pluralig of stages in each sub-integrated circuit block of said
`
`pluralifl of sub-integrated circuit blocks comprises only one switch of said pluralifl of
`
`switches connecting said pluralifl of forward connecting links and each stage of said
`
`pluralifl of stages in each sub-integrated circuit block of said pluralifl of sub-integrated
`
`circuit blocks comprises only one switch of said pluralifl of switches connecting said
`
`pluralifl of backward connecting links and said multi-stage network is rearrangeably
`
`nonblocking for unicast butterfly fat tree network: or
`
`each stage of said pluralig of stages in each sub-integrated circuit block of said
`
`pluralifl of sub-integrated circuit blocks comprises at least two switches of said pluralifl
`
`of switches connecting said pluralifl of forward connecting links and each stage of said
`
`pluralifl of stages in each sub-integrated circuit block of said pluralifl of sub-integrated
`
`circuit blocks comprises at least two switches of said pluralifl of switches connecting said
`
`pluralifl of backward connecting links and said multi-stage network is strictly
`
`nonblocking for unicast butterfly fat tree network and rearrangeably nonblocking for
`
`arbitram fan-out multicast butterfly fat tree network: or
`
`each stage of said pluralig of stages in each sub-integrated circuit block of said
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`pluralifl of sub-integrated circuit blocks comprises at least three switches of said plurality
`
`10
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`15
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`20
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`25
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
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`of switches connecting said pluralifl of forward connecting links and each stage of said
`
`pluralifl of stages in each sub-integrated circuit block of said pluralifl of sub-integrated
`
`circuit blocks comprises at least three switches of s