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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`Commissionerfor Patents
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`www.uspto.gov
`
`Konda Technologies, Inc
`6278 GRAND OAK WAY
`SAN JOSE CA 95135
`
`In re Application of
`Konda Technologies Inc.
`Application No.: 16/202,067
`Filing Date: 27 November2018
`Attorney Docket No.: V-0070US
`
`MAILED
`
`NOV 27 2019
`INTERNATIONAL PATENT LEGAL ADM,
`
`:
`:
`:
`
`DECISION
`
`This Decisionis in response tothe filing of “Petition To Withdraw the Prior Filed
`Petition on 11/27/2018 To Accept The Unintentionally Delayed Claim Under 35 U.S.C. 119(e),”
`in the United States Patent and Trademark Office on 17 September 2019.
`
`This application does notcontain a delayed claim of benefit. A petition for the
`unintentionally delayed paymentof the basic national fee under 37 CFR 1.137(a) was accepted
`in 12/601,275.
`
`Applicant’s request to withdrawthe petition and refund the petition fee is GRANTED.
`
`/Erin P. Thomson/
`Erin P. Thomson
`Attorney Advisor
`International Patent Legal Administration
`571-272-3292
`
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`

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`Title of Invention:
`
`VLSI Layouts of Fully Connected Generalized Networks
`
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`Electronic AcknowledgementReceipt
`
`Application Number:
`
`16202067
`
`International Application Number:
`
`Confirmation Number:
`
`8134
`
`
`
`ee
`a
`
`Paymentinformation:
`
`Submitted with Payment
`
`File Listing:
`
`Ob9Sd
`
`Pages
`Multi
`File Size(Bytes)/
`DocumentDescription
`Document
`
`
`
`Number Message Digest|Part/.zip|P (if appl.)
`218167
`
`Reissue decfiled in accordance with
`MPEP 1414
`
`VO070US-aia0005.pdf
`
`eb6d66b02b0eb8f341153179cc12222cd75
`
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`Page 3 of 626
`Information:
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`IPR2020-00260
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`Preliminary Amendment
`
`V0070US-PrelimAmend.pdf
`
`238878
`
`4e1 1df3fe54386626c1600c646245d906699
`7be9
`
`Information:
`
`This AcknowledgementReceipt evidences receipt on the noted date by the USPTO of the indicated documents,
`characterized by the applicant, and including page counts, where applicable.It serves as evidence of receipt similar to a
`Post Card, as described in MPEP 503.
`
`
`
`
`New Applications Under 35 U.S.C. 111
`If a new application is being filed and the application includes the necessary componentsfora filing date (see 37 CFR
`1.53(b)-(d) and MPEP 506), a Filing Receipt (37 CFR 1.54) will be issued in due course and the date shownonthis
`AcknowledgementReceiptwill establish the filing date of the application.
`
`National Stage of an International Application under 35 U.S.C. 371
`If a timely submission to enter the national stage of an international application is compliant with the conditions of 35
`U.S.C. 371 and other applicable requirements a Form PCT/DO/EO/903indicating acceptanceof the application asa
`national stage submission under35 U.S.C. 371 will be issued in addition to the Filing Receipt, in due course.
`NewInternational Application Filed with the USPTO as a Receiving Office
`If a new international application is being filed and the international application includes the necessary components for
`an international filing date (see PCT Article 11 and MPEP 1810), a Notification of the International Application Number
`and of the International Filing Date (Form PCT/RO/105)will be issued in due course, subject to prescriptions concerning
`national security, and the date shown on this AcknowledgementReceiptwill establish the international filing date of
`the application.
`
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`Page 4 of 626
`Doc Code: REIS.DECL
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`IPR2020-00260
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`Document Description: Reissue Declaration Filed In Accordance With MPEP 714714
`
`scope oforiginal claims.
`
`Because the patentee claimed more than he had the right to claim in the US Patent No.
`8,269,523, the scope of the original claim 1
`is narrowed byincorporating limitations of claim 3
`into original claim 1. Newly added independent claims 49 and 50 also do not broaden the
`
`Under the Paperwork Reduction Act of 1995, no persons
`
`f
`| REISSUE APPLICATION DECLARATION BY THE INVENTOR
`
`PTO/AIA/0S (06-12)
`Approved for use through 01/31/2020. OMB 0651-0033
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`are required to respond to a collection of information
`unless it displavs a valid OMB control number.
`§ Docket Number (Optional)
`V-0070US
`
`5
`
`i hereby deciare that:
`f
`| Each inventor's residence and mailing address are stated below next to their name.
`f
`| believe | am the original inventor or an original joint inventor of the subject matter which is described and claimed
`
`
`in patent number _8.269.523iSeptember18,2012eee ald for which a, Granted
`
`
`f reissue patient is sought on the inventiontitled
`VLSI Layouts of Fully Connected Generalized Networks
`
`the specification of which
`[| is attached hereto.
`was filed on 11/27/2018
`
`as reissue application number 16/202,067
`
`The above-identified application was made or authorized to be made by me.
`
`| hereby acknowledge that any willful faise statement made in this dectaration is punishable under 18 U.S.C. 1001 by fine
`f
`f crimprisonment of not more thanfive (5) years, or both.
`
`i believe the original patent to be wholly or partly inoperative or invalid, for the reasons described
`below. (Check ail boxes that apply.)
`
`[| by reason of a defective specification or drawing.
`
`iv| by reason of the patentee claiming more or less than ne had the right to claim in the patent.
`
`| by reason of othererrors.
`
`[f the reissue is a broadening
`Ai least one error upon which reissue is based is described below.
`i reissue, a claim that the application seeks to broaden mustbe identified:
`
`
`[Page 1 of 2]
`
`This collection of information is required by 37 CFR 1.175. The information is required to obtain or retain a benefit by the public whichis to file (and by the USPTO
`to process) an apptication. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.11 and 1.14. This collection is estimated to take 30 minutes to complete,
`including gathering, preparing, and submitting the cornpleted application formto the USPT®. Time will vary depending uponthe individual case. Any comments on
`the amount of time you require to complete this form and/or suggestions for reducing this burden, should be sent to the Chief information Officer, U.S. Patent and
`Trademark Office, U.S. Department of Commerce, P.O. Box 1450, Alexandria, VA 22313-1450. BO NOT SEND FEES OR COMPLETED FORMS TO THIS
`ADDRESS. SENB TO: Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450.
`
`if you need assistance in completing the form, call 1-800-PTO-9199 and select option 2.
`
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`Under the Paperwork Reduction Act of 1995, no perso
`
`PTO/AIA/DS (06-12)
`Approved for use through 01/31/2020. OMB 0651-0033
`USP
`atent and Trademark Office; US. DEPARTMENT OF COMMERCE
`
`S$ are required to respond to a colle
`of
`
`information unlessit
`displays a valid OMB control number.
`
`
`
`i
`i (REISSUE APPLICATION DECLARATION BY THE INVENTOR, page 2)
`
`Docket Number (Optional)
`V-0070US
`
`Note: To appcint a power of attorney, use form PTO/AIA/81.
`
`Correspondence Address: Direct all communications about the application to:
`The address associated with Customer Number:
`
`38139
`
`
`
`v1]
`
`1 OR
`
`Firm or
`Individual Name
`
`f Country
`
`——cl
`eerJ
`
`|
`
`WARNING:
`Petitioner/applicant is cautioned to avoid submitting personal information in documentsfiled in a patent application that may
`i contribute fo identity theft. Personal information such as social security numbers, bank account numbers, or credit card §
`i numbers (other than a check orcredit card authorization form PTO-2038 submitted for payment purposes) is never required by |
`the USPTO to Support a petition or an application.
`if this type of personai information is included in documents submitied to
`} ihe USPTO, petitioners/applicants should consider redacting such personal information from the documents before submitting |
`| them io the USPTO. Petitioner/applicant is advised that the record of a patent application is available to the public after
`§
`i publication of the application (unless a non-publication request in compliance with 37 CFR 1.213 (a) is made in the application)
`i or issuance of a patent. Furthermore, the record from an abandoned application may also be available to the public if the |
`| application is referenced in a puolisned application or an issued’ patent (see 37 CFR 1.14). Checks and credit card
`} authorization forms PTO-2038 submitied for payment purposes are not retained in the application file and therefore are not
`| publicly availabie.
`
`}
`;
`
`State
`CA
`
`| Date (Optionai)
`September23, 2019
`Country
`USA
`
`Legal nameof soleor first inventor (E.g., Given Name(first and middie (if any) and Family Name or Surname
`| Venkat Konda
`|
`inventor's Signature
`| Venkat Konda/
`7 Residence: City
`
`|San Jose
`
`| Mailing Address
`|6278 Grand Oak Way
`Zip
`| State
`: City
`USA
`San Jose cA95135
`
`
`
`|
`
`Country
`
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`Privacy Act Statement
`
`The Privacy Act of 1974 (P.L. 93-579) requires that you be given certain information in connection
`with your submission of the attached form related to a patent application or patent. Accordingly,
`pursuant to the requirements of the Act, please be advised that: (1) the general authority for the
`collection of this information is 35 U.S.C. 2(b)(2); (2) furnishing of the information solicited is voluntary;
`and (3) the principal purpose for which the information is used by the U.S. Patent and Trademark
`Office is to process and/or examine your submission related to a patent application or patent. If you do
`not furnish the requested information, the U.S. Patent and Trademark Office may not be able to
`process and/or examine your submission, which may result in termination of proceedings or
`abandonmentof the application or expiration of the patent.
`
`The information provided by you in this form will be subject to the following routine uses:
`
`1. The information on this form will be treated confidentially to the extent allowed under the
`Freedom ofInformation Act (5 U.S.C. 552) and the Privacy Act (5 U.S.C 552a). Records from
`this system of records maybe disclosed to the Department of Justice to determine whether
`disclosure of these records is required by the Freedom of Information Act.
`2. A record from this system of records may be disclosed, as a routine use, in the course of
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`3. Arecord in this system of records may be disclosed, as a routine use, to a Member of
`Congress submitting a request involving an individual, to whom the record pertains, when the
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`4. A record in this system of records may bedisclosed, as a routine use, to a contractor of the
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`amended, pursuant to 5 U.S.C. 552a(m).
`5. Arecord related to an International Application filed under the Patent Cooperation Treatyin
`this system of records maybedisclosed, as a routine use, to the International Bureau of the
`World Intellectual Property Organization, pursuant to the Patent Cooperation Treaty.
`6. A record in this system of records may be disclosed, as a routine use, to another federal
`agency for purposes of National Security review (35 U.S.C. 181) and for review pursuant to
`the Atomic Energy Act (42 U.S.C. 218(c)).
`7. Arecord from this system of records may be disclosed, as a routine use, to the Administrator,
`General Services, or his/her designee, during an inspection of records conducted by GSA as
`part of that agency’s responsibility to recommend improvements in records management
`practices and programs, under authority of 44 U.S.C. 2904 and 2906. Such disclosure shall
`be made in accordance with the GSA regulations governing inspection of records for this
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`be used to make determinations aboutindividuals.
`8. A record from this system of records may be disclosed, as a routine use, to the public after
`either publication of the application pursuant to 35 U.S.C. 122(b) or issuanceof a patent
`pursuant to 35 U.S.C. 151. Further, a record may be disclosed, subject to the limitations of 37
`CFR 1.14, aS a routine use, to the public if the record wasfiled in an application which
`became abandonedor in which the proceedings were terminated and which application is
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`9. Arecord from this system of records may be disclosed, as a routine use, to a Federal, State,
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`violation of law or regulation.
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`In The UnitedStates PatentAndTrademarkOffice
`
`Reissue Application
`
`:
`
`16/202,067
`
`Parent US Patent No : 8,269,523
`
`Filed: November 27, 2018
`
`Issued: September 18, 2012
`
`Parent Application No:
`
`12/601,275
`
`Filed: May 31, 2010
`
`Examiner
`
`: Ton, My Trang
`
`Group Art Unit: 3992
`
`Applicant(s): Venkat Konda
`
`Filed: November27, 2018
`
`Title: VLSI Layouts of Fully Connected Generalized Networks
`
`10
`
`AMENDMENT ACCOMPANYING REISSUE APPLICATION RESUBMITTED
`
`PURSUANTTO 37 C.F.R. §1.173(B)
`
`San Jose, 2019 Sept 23, Mon
`
`Mail Stop Reissue
`
`Commissioner for Patents
`
`15
`
`P.O. Box 1450
`
`Alexandria, VA 22313-1450
`
`Dear Sir/Madam:
`
`20
`
`For the above above-referenced reissue patent application, in view of the petition
`
`granted on August 19, 2019 that wasfiled in the parent Patent No. 8,269,523 for the
`
`entire delay in filing the basic national fee from the due date for the fee until the filing of
`
`a grantable petition under 37 CFR 1.137 was unintentional, applicant is now submitting a
`
`new “the reissue application declaration by the inventor”. Furthermore the Amendment
`
`25
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`submitted for the above-referenced reissue patent application filed on November 27, 2018
`
`which supposed to set forth applicant’s requested amendments to U.S. Patent No.
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`8,269,523 is non-compliant with 37 C.F.R. §1.173(B)at least since the submitted claims
`
`are not identified with correct format.
`
`Accordingly applicant respectfully requests to disregard the amendment submitted
`
`on November 27, 2018 and consider this amendment. This Amendment accompanies the
`
`reissue patent application filed on November 27, 2018, and sets forth applicant’s
`
`requested amendments to U.S. Patent No. 8,269,523.
`
`Amendmentto Specification is set forth on page 4.
`
`Amendments to the claimsare set forth in the Listing ofthe Claims, which begins on
`
`10
`
`Page 5. Originally issued claims 1, 2, 4, 7, 11, 16, 22, 24, 28, 33, 36, 39, 43 are amended.
`
`Originally issued claims 3, 5, 6, 8 - 10, 12 - 14, 15, 17-21, 23, 25 — 27, 29 — 32, 34 — 35,
`
`37 — 38, 40 — 42, 44 - 48 are now cancelled. Originally issued claims are amended
`
`perfecting the claim language. But no new matter is added. Furthermore:
`
`Incorporated limitations of Claim 3 into Claim 1 and cancelled claim 3.
`
`15
`
`Incorporated limitations of Claims 5 — 6 into Claim 4 and cancelled claims 5 — 6.
`
`Incorporated limitations of Claims 8 — 10 into Claim 7 and cancelled claims 8 — 10.
`
`Incorporated limitations of Claims 12 — 14 into Claim 11 and cancelled claims 12 — 14.
`
`Incorporated limitations of Claims 18, 19, 21, 22, and 47 into Claim 16 and cancelled
`
`claims 18, 19, 21, 22, and 47.
`
`20
`
`Incorporated limitations of Claims 25 — 27 into Claim 24 and cancelled claims 25 — 27.
`
`Incorporated limitations of Claims 29 — 32 into Claim 28 and cancelled claims 29 — 32.
`
`Incorporated limitations of Claims 34 — 35 into Claim 33 and cancelled claims 34 — 35.
`
`Incorporated limitations of Claims 37 — 38 into Claim 36 and cancelled claims 37 — 38.
`
`Incorporated limitations of Claims 40 — 42 into Claim 39 and cancelled claims 40 — 42.
`
`25
`
`Incorporated limitations of Claims 44 — 46 into Claim 43 and cancelled claims 44 — 46.
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`Page 2 of 26
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`Newclaims 49 and 50 are added both narrowingthe original Claim 1 in different ways.
`
`Therefore, the claims 1, 2, 4, 7, 11, 16, 22, 24, 28, 33, 36, 39, 43, 49, 50 are pending in
`
`this reissue application following entry of this amendment.
`
`Remarks are set forth on page 25.
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`Amendments to the Specification
`
`Amendments to the specification are indicated below wherein matter to addedis indicated
`
`by underlining and matter to be deleted is indicated in [brackets].
`
`Please replace the paragraph at column 1, lines 7-15, following the heading
`
`“CROSS REFERENCE TO RELATED APPLICATIONS”with the following:
`
`This application [is related to and] is an application for reissue of U.S. Patent No.
`
`8.269.523 which claimspriority of the PCT Application Serial No. PCT/ US08/64605
`
`10
`
`entitled "VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS"
`
`by Venkat Konda assigned to the same assigneeas the current application, filed May 22,
`
`2008, [and] which in turn claimspriority of the U.S. Provisional Patent Application Serial
`
`No. 60/940, 394 entitled "VLSI LAYOUTS OF FULLY CONNECTED
`
`15
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`GENERALIZED NETWORKS"by Venkat Konda assigned to the same assignee as the
`
`current application, filed May 25, 2007.
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`LISTING OF THE CLAIMS
`
`This Claim listing sets forth all the claims that will be pendingin this reissue application
`
`following entry of the present amendment.
`
`1.
`
`(Amended): An integrated circuit [device] comprising a plurality of sub-
`
`integrated circuit blocks and a [routing network] multi-stage network, and
`
`[Said] each sub-integrated circuit block of said plurality of sub-integrated circuit
`
`blocks comprising a plurality of inlet links and a plurality of outlet links; and
`
`[Said] said [routing network] multi-stage network comprising [of] a plurality of
`
`10
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`stages y [in| correspondingto each [said] sub-integrated circuit block of said plurality of
`
`sub-integrated circuit blocks, starting from [the lowest] stage [of] 1 to [the highest] stage
`
`[of] vy, where y>1; and
`
`[Said routing network comprising] each stage of said plurality of
`
`stages y comprising a plurality of switches of size d xd, where d > 2 |, in each said
`
`15
`
`stage] and each [said] switch of said plurality of switches of size d xd having d inlet
`
`links and d@ outlet links; and
`
`[Said] said plurality of outlet links of [said] each sub-integrated circuit block of
`
`said plurality of sub-integrated circuit blocks are directly connected to said plurality of
`
`inlet links of said plurality of switches of size dxd_ of its correspondingsaid [lowest]
`
`20
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`stage [of] 1 of said plurality of stages y , and said plurality of inlet links of [said] each
`
`sub-integrated circuit block of said plurality of sub-integrated circuit blocks are directly
`
`connected from said plurality of outlet links of said plurality of switches of size d xd of
`
`[its corresponding] said [lowest] stage [of] 1 of said plurality of stages y ; and
`
`[said] each sub-integrated circuit block of said plurality of sub-integrated circuit
`
`25
`
`blocks comprising a plurality of forward connecting links connecting from said plurality
`
`of switches in [a lower] each stage of said plurality of stages y to said plurality of
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
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`Attorney Docket No. V-0070US
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`switches in [its] an immediate succeeding [higher] stage of said plurality of stages y , and
`
`also comprising a plurality of backward connecting links connecting from said plurality
`
`of switches in [a higher] each stage of said plurality of stages y to said plurality of
`
`switches in [its] an immediate [succeeding lower] preceding stage of said plurality of
`
`stages y ; and
`
`[Said each sub-integrated circuit block comprising a plurality straight links in said
`
`forward connecting links from switches in said each lower stage to switches in its
`
`immediate succeeding higher stage and a plurality cross links in said forward connecting
`
`links from switches in said each lower stage to switches in its immediate succeeding
`
`10
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`higher stage, and further comprising a plurality of straight links in said backward
`
`connecting links from switches in said each higher stage to switches in its immediate
`
`preceding lowerstage and a plurality of cross links in said backward connecting links
`
`from switches in said each higher stage to switches in its immediate preceding lower
`
`stage,|
`
`15
`
`said plurality of sub-integrated circuit blocks arranged in a two-dimensional grid
`
`of a plurality of rows and a plurality of columns, and
`
`said plurality of forward connecting links and said plurality of backward
`
`connecting links comprise[s] a plurality of [said all] straight middle links [are] connecting
`
`from said plurality of switches of a first stage of said plurality of stages y in [each said] a
`
`20
`
`first sub-integrated circuit block of said plurality of sub-integrated circuit blocks [are
`
`connecting] to said plurality of switches of an immediate succeeding or an immediate
`
`preceding stage of said first stage of said plurality of stages y in [the same] said first sub-
`
`integrated circuit block_of said plurality of sub-integrated circuit blocks; and
`
`said plurality of forward connecting links and said plurality of backward
`
`connecting links comprise[s| a plurality of [said all] cross middle links [are] connecting
`
`25
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`[as either vertical or horizontal links between switches in twodifferent said sub-
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`Reissue Application No. 16/202,067
`Reissue Application Filed: 11/27/18
`
`Attorney Docket No. V-0070US
`
`integrated circuit blocks which are either placed vertically above or below, or placed
`
`horizontally to the left or to the right,] from switches of said plurality of switches in a
`
`stage of said plurality of stages y ina first sub-integrated circuit block of said plurality of
`
`sub-integrated circuit blocks to switches of said plurality of switches in a succeeding
`
`stage or a precedingstage a first sub-integrated circuit block of said plurality of sub-
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`integrated circuit blocks wherein said plurality of cross middle links are either vertical
`tracks or horizontal tracks, and
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`plurality of stagesyare connected alternately as vertical tracks and horizontal tracks
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`a plurality of said plurality of cross middle links in succeeding stages of said
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`10
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`hereinafter “hypercube topology”),
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`and
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`[each said plurality of sub-integrated circuit blocks comprising same numberof
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`said stages and] each sub-integrated circuit block of said plurality of sub-integrated
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`circuit blocks connected with said plurality of switches of sizedxd _of said plurality of
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`stages y [said switches in each said stage,| regardless of the size of said plurality of rows
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`15
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`and size of said plurality of columns of said two-dimensional grid [so that] wherein each
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`sub-integrated circuit block of said plurality of sub-integrated circuit [block with its
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`corresponding said stages and said switches in each stage] blocks connected with said
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`plurality of switches of size d x d_of said plurality of stages y is replicable in both
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`vertical direction or horizontal direction of said two-dimensional grid.
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`20
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`2.
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`(Amended): The integrated circuit [device] of claim 1,
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`said two-dimensionalgrid of said plurality of sub-integrated circuit blocks connected with
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`[their corresponding] said plurality of stages y [and said switches in each stage] is
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`scalable by any powerof 2, and,
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`for each multiplication of 2 of [the] size of total said plurality of sub-integrated
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`25
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`circuit blocks, by adding one morestage [of switches] to said plurality of stages and said
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`hypercube [layout] topology is extended and placed in said hypercube topology|format]
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`and [also] the cross middle links between said one morestage to said plurality of stages y
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`Reissue Application Filed: 11/27/18
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`Attorney Docket No. V-0070US
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`of switches of said plurality of switches are connected in said hypercube topology
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`[format).
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`3.
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`4.
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`(Cancel claim 3)
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`(Amended): The integrated circuit [device] of claim [3] 1, wherein [said cross
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`links from switches in a stage said stages in one of said sub-integrated circuit blocks are
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`connecting to switches in the succeeding stage in another of said sub-integrated circuit
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`blocks so that said cross links are either vertical links or horizontal and vice versa, and
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`hereinafter such cross links are “shuffle exchange links”). |_said plurality of cross middle
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`links between switches in any two same succeeding stages of said plurality of stages y are
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`10
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`substantially of equal length in said integrated circuit, and
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`the shortest cross middle links of said plurality of cross middle links are
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`connected at stage 1 of said plurality of stages y_and between switches of said plurality of
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`switches in two nearest neighboring said plurality of sub-integrated circuit blocks, and
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`length of the cross middle links is doubled in each succeedingstage of said plurality of
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`15
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`stages y in either said vertical tracks or said horizontal tracks.
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`5.
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`6.
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`(Cancel claim 5)
`
`(Cancel claim 6)
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`7.
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`(Amended): The integrated circuit [device] of claim [6] 4, wherein y > (log, N) :
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`where NV > 1, [so that] wherein [the] length or width of the [horizontal] plurality of cross
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`20
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`middle links [shuffle exchange links] in [the highest] stage y is equal to half the [size]
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`length or width [of the horizontal size| of said two dimensional grid of said plurality of
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`sub-integrated circuit blocks [and the length of the vertical shuffle exchangelinks in the
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`highest stage is equal to half the size of the vertical size of said two dimensional grid of
`sub-integrated circuit blocks,], and wherein d = 2 and either
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`Attorney Docket No. V-0070US
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`each stage of said plurality of stages in each sub-integrated circuit block of said
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`plurality of sub-integrated circuit blocks comprises only one switch of said plurality of
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`switches connecting said plurality of forward connecting links and each stage of said
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`plurality of stages in each sub-integrated_ circuit block of said plurality of sub-integrated
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`circuit blocks comprises only one switch of said plurality of switches connecting said
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`plurality of backward connecting links and said multi-stage network is rearrangeably
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`nonblocking for unicast Benes network, or
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`each stage of said plurality of stages in each sub-integrated circuit block of said
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`plurality of sub-integrated circuit blocks comprises at least two switches of said plurality
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`10
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`of switches connecting said plurality of forward connecting links and each stage of said
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`plurality of stages in each sub-integrated_ circuit block of said plurality of sub-integrated
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`circuit blocks comprises at least two switches of said plurality of switches connecting said
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`plurality of backward connecting links and said multi-stage networkisstrictly
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`nonblocking for unicast Benes network and is rearrangeably nonblocking for arbitrary
`fan-out multicast Benes network, or
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`15
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`each stage of said plurality of stages in each sub-integrated circuit block of said
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`plurality of sub-integrated circuit blocks comprises at least three switches of said plurality
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`of switches connecting said plurality of forward connecting links and each stage of said
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`plurality of stages in each sub-integrated_ circuit block of said plurality of sub-integrated
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`20
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`circuit blocks comprises at least three switches of said plurality of switches connecting
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`said plurality of backward connecting links and said multi-stage networkis strictly
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`nonblocking for arbitrary fan-out multicast Benes network.
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`8.
`
`(Cancel claim 8)
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`25
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`9,
`
`(Cancel claim 9)
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`10.
`
`(Cancel claim 10)
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`Attorney Docket No. V-0070US
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`11.
`
`(Amended): The integrated circuit [device] of claim [6] 4, wherein y > (log, N) ;
`
`where NV > 1, [so that] wherein [the] length or width of the [horizontal] plurality of cross
`
`middle links [shuffle exchangelinks] in [the highest] stage y is equalto half the [size]
`
`length or width [of the horizontal size| of said two dimensional grid of said plurality of
`
`sub-integrated circuit blocks [and the length of the vertical shuffle exchangelinks in the
`
`highest stage is equalto half the size of the vertical size of said two dimensionalgrid of
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`sub-integrated circuit blocks,],and
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`[said] each sub-integrated circuit block of said plurality of sub-integrated circuit
`
`blocks further comprising a plurality of U-tum links within switches of said plurality of
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`10
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`switches in each stage of said plurality of stages in each of said plurality of sub-integrated
` circuit blocks|.], and wherein d = 2 and either
`
`each stage of said plurality of stages in each sub-integrated circuit block of said
`
`plurality of sub-integrated circuit blocks comprises only one switch of said plurality of
`
`switches connecting said plurality of forward connecting links and each stage of said
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`15
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`plurality of stages in each sub-integrated circuit block of said plurality of sub-integrated
`
`circuit blocks comprises only one switch of said plurality of switches connecting said
`
`plurality of backward connecting links and said multi-stage network is rearrangeably
`
`nonblocking for unicast butterfly fat tree network, or
`
`each stage of said plurality of stages in each sub-integrated circuit block of said
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`20
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`plurality of sub-integrated circuit blocks comprises at least two switches of said plurality
`
`of switches connecting said plurality of forward connecting links and each stage of said
`
`plurality of stages in each sub-integrated circuit block of said plurality of sub-integrated
`
`circuit blocks comprises at least two switches of said plurality of switches connecting said
`
`plurality of backward connecting links and said multi-stage network isstrictly
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`25
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`nonblocking for unicast butterfly fat tree network and rearrangeably nonblocking for
`
`arbitrary fan-out multicast butterfly fat tree network, or
`
`each stage of said plurality of stages in each sub-integrated circuit block of said
`
`plurality of sub-integrated circuit blocks comprises at least three switches of said plurality
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`of switches connecting said plurality of forward connecting links and each sta