Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`The stage (slice 1, ring 1, stage "m") consists of8 inputs namely Ri(l,l,2m+l),
`
`Ri(l,l,2m+2), Ui(l,l,2m+ 1), Ui(l,l,2m+2), J(l, l,m+ 1), K(l, l,m+ 1), L(l, l,m+ 1), and
`
`M(l,l,m+l); and 4 outputs Bo(l,l,2m+l), Bo(l,l,2m+2), Fo(l,l,2m+l), and
`
`Fo(l, l,2m+2). The stage (slice 1, ring 1, stage "m") also consists of four 4: 1 Muxes
`
`5
`
`namely F(l, l,2m+ 1), F(l,l,2m+2), B(l, l,2m+ 1), and B(l, l,2m+2). The 4: 1 Mux
`
`F(l, l,2m+ 1) has four inputs namely Ri(l, l,2m+ 1), Ri(l,l,2m+2), Ui(l,l,2m+2), and
`
`J(l,l,m+l), and has one outputFo(l,l,2m+l). The 4:1 Mux F(l,1,2m+2) has four inputs
`
`namely Ri(l,l,2m+l), Ri(l,l,2m+2), Ui(l,l,2m+l), and K(l,l,m+l), and has one output
`
`Fo(l, l,2m+2).
`
`10
`
`The 4:1 Mux B(l,l,2m+l) has four inputs namely Ui(l,1,2m+l), Ui(l,l,2m+2),
`
`Ri( 1, l ,2m+2), and L( 1, l ,m+ 1 ), and has one output Bo( 1, l ,2m+ 1 ). The 4: 1 Mux
`
`B(l, l,2m+2) has four inputs namely Ui(l, l,2m+ 1), Ui(l, l,2m+2), Ri(l, l,2m+ 1) and
`
`M(l,l,m+ 1), and has one output Bo(l, l,2m+2). In different embodiments the inputs
`
`J(l, l,m+ 1), K(l, l,m+ 1), L(l,l,m+ 1), and M(l,l,m+ 1) are connected from any of the
`
`15
`
`outputs of any other stages of any ring of any block of the multi-stage hierarchical
`
`Just the same way the stage (slice 1, ring 1, stage 0), there are also stages (slice 1,
`
`ring 1, stage 1), (slice 1, ring 1, stage 2), (slice 1, ring 1, stage 3), ... (slice 1, ring 1, stage
`
`"m-1"), (slice 1, ring 1, stage "m") in that order, where the stages from (slice 1, ring 1,
`
`20
`
`stage 1), (slice 1, ring 1, stage 2), ... , (slice 1, ring 1, stage "m-1") are not shown in the
`
`diagram 1 OOC.
`
`Referring to diagram 1 OOC5 in FIG. 1 C5 illustrates specific details of partial
`
`multi-stage hierarchical network Vcomb (N1,N2 ,d,s) lOOC in FIG. IC, particularly the
`
`internal connections between two successive stages of any ring of any slice, in one
`
`25
`
`embodiment. The stage (slice "c", ring "d", stage "e") consists of 8 inputs namely
`
`Ri(c,d,2e+l), Ri(c,d,2e+2), Ui(c,d,2e+l), Ui(c,d,2e+2), J(c,d,e+l), K(c,d,e+l),
`
`L( c,d,e+ 1 ), and M( c,d,e+ 1 ); and 4 outputs Bo( c,d,2e+ 1 ), Bo( c,d,2e+2), Fo( c,d,2e+ 1 ), and
`
`Fo(c,d,2e+2). The stage (slice "c", ring "d", stage "e") also consists of four 4:1 Muxes
`
`namely F(c,d,2e+ 1), F(c,d,2e+2), B(c,d,2e+ 1), and B(c,d,2e+2). The 4: 1 Mux F(c,d,2e+ 1)
`
`30
`
`has four inputs namely Ri(c,d,2e+l), Ri(c,d,2e+2), Ui(c,d,2e+2), and J(c,d,e+l), and has
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`-130-
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`FLEX LOGIX EXHIBIT 1055 (Part 2 of 2)
`Flex Logix Technologies v. Venkat Konda
`IPR2020-00260
`
`

`

`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`one output Fo(c,d,2e+ 1). The 4:1 Mux F(c,d,2e+2) has four inputs namely Ri(c,d,2e+ 1),
`
`Ri(c,d,2e+2), Ui(c,d,2e+l), and K(c,d,e+l), and has one output Fo(c,d,2e+2).
`
`The 4: 1 Mux B(c,d,2e+ 1) has four inputs namely Ui(c,d,2e+ 1), Ui(c,d,2e+2),
`
`Ri(c,d,2e+2), and L(c,d,e+ 1), and has one output Bo(c,d,2e+l). The 4: 1 Mux B(c,d,2e+2)
`
`5
`
`has four inputs namely Ui(c,d,2e+ 1), Ui(c,d,2e+2), Ri(c,d,2e+ 1) and M(c,d,e+ 1), and has
`
`one output Bo(c,d,2e+2). In different embodiments the inputs J(c,d,e+ 1), K(c,d,e+ 1),
`
`L(c,d,e+ 1), and M(c,d,e+ 1) are connected from any of the outputs of any other stages of
`
`any ring of any block of the multi-stage hierarchical network Vcomb (N1,N2 ,d,s).
`
`The stage (slice "c", ring "d", stage "e+ l") consists of 8 inputs namely
`
`10
`
`Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+3), Ui(c,d,2e+4), J(c,d,e+2), K(c,d,e+2),
`
`L(c,d,e+2), and M(c,d,e+2); and 4 outputs Bo(c,d,2e+3), Bo(c,d,2e+4), Fo(c,d,2e+3), and
`
`Fo(c,d,2e+4). The stage (slice "c", ring "d", stage "e+l") also consists of four 4:1 Muxes
`
`namely F(c,d,2e+3), F(c,d,2e+4), B(c,d,2e+3), and B(c,d,2e+4). The 4: 1 Mux F(c,d,2e+3)
`
`has four inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+4), and J(c,d,e+2), and has
`
`15
`
`one output Fo(c,d,2e+3). The 4: 1 Mux F(c,d,2e+4) has four inputs namely Ri(c,d,2e+3),
`
`Ri(c,d,2e+4), Ui(c,d,2e+3), and K(c,d,e+2), and has one output Fo(c,d,2e+4).
`
`The 4: 1 Mux B(c,d,2e+3) has four inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4),
`
`Ri(c,d,2e+4), and L(c,d,e+2), and has one output Bo(c,d,2e+3). The 4: 1 Mux B(c,d,2e+4)
`
`has four inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4), Ri(c,d,2e+3) and M(c,d,e+2), and has
`
`20
`
`one output Bo(c,d,2e+4). In different embodiments the inputs J(c,d,e+2), K(c,d,e+2),
`
`L(c,d,e+2), and M(c,d,e+2) are connected from any of the outputs of any other stages of
`
`any ring of any block of the multi-stage hierarchical network Vcomb(N1,N2 ,d,s).
`
`The output Fo(c,d,2e+ 1) of the stage (slice "c", ring "d", stage "e") is connected
`
`to the input Ri(c,d,2e+3) of the stage (slice "c", ring "d", stage "e+ l") which is called
`
`25
`
`hereinafter an internal connection between two successive stages of a ring. And the
`
`output Bo(c,d,2e+3) of the stage (slice "c", ring "d", stage "e+l") is connected to the
`
`input Ui(c,d,2e+ 1) of the stage (slice "c", ring "d", stage "e"), is another internal
`
`connection between stage "e" and stage "e+l" of the ring (slice "c", ring "d").
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`-131-
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`

`

`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`Just the same way the two successive stages (slice "c', ring "d", stage "e") and
`
`(slice 'c", ring "d", stage "e+ l ") have internal connections between them as described
`
`above, any two successive stages have similar internal connections for any values of "c",
`
`"d", "e" of the partial multi-stage hierarchical network T''camb(Nt,N 2 ,d,s) lOOC in FIG.
`
`5
`
`IC belonging to any block of the two dimensional grid 800 in FIG. 8, in some
`
`embodiments. For example stage (slice 1, ring 1, stage 0) and stage (slice 1, ring 1, stage
`
`1) have similar internal connections; and stage (slice 1, ring 1, stage "m-1") and stage
`
`(slice 1, ring 1, stage "m") have similar internal connections.
`
`Stage (slice 1, ring 1, stage 0) is also called hereinafter the "entry stage" or "first
`
`10
`
`stage" of (slice 1, ring 1), since inlet links and outlet links of the computational block are
`
`directly connected to stage (slice 1, ring 1, stage 0). Also stage (slice 1, ring 1, stage "m")
`
`is hereinafter the "last stage" or "root stage" of (slice 1, ring 1 ).
`
`The stage (slice 1, ring 2, stage 0) consists of 8 inputs namely Ri(l,2,1), Ri(l,2,2),
`
`Ui(l,2, 1), Ui(l,2,2), J(l,2, 1), K(l,2, 1), L(l,2, 1), and M(l,2, l); and 4 outputs Bo(l,2,1),
`
`15
`
`Bo(l,2,2), Fo(l,2,1), and Fo(l,2,2). The stage (slice 1, ring "2", stage "O") also consists
`
`of four 4:1 Muxes namely F(l,2,1), F(l,2,2), B(l,2,1), and B(l,2,2). The 4:1 Mux
`
`F(l,2,1) has four inputs namely Ri(l,2,1), Ri(l,2,2), Ui(l,2,2), and J(l,2,1), and has one
`
`output Fo(l,2,1). The 4:1 Mux F(l,2,2) has four inputs namely Ri(l,2,1), Ri(l,2,2),
`
`Ui(l,2, 1), and K(l,2, 1), and has one output Fo(l,2,2).
`
`20
`
`The 4:1 Mux B(l,2,1) has four inputs namely Ui(l,2,1), Ui(l,2,2), Ri(l,2,2), and
`
`L(l,2, 1), and has one output Bo(l,2, 1). The 4: 1 Mux B(l,2,2) has four inputs namely
`
`Ui(l,2,1), Ui(l,2,2), Ri(l,2,1) and M(l,2,1), and has one output Bo(l,2,2). In different
`
`embodiments the inputs J ( 1,2, 1 ), K( 1,2, 1 ), L( 1,2, 1 ), and M( 1,2, 1) are connected from any
`
`of the outputs of any other stages of any ring of any block of the multi-stage hierarchical
`
`25
`
`network Vcamb(Nt,N2 ,d,s).
`
`The stage (slice 1, ring 2, stage "n") consists of 8 inputs namely Ri(l,2,2n+ 1 ),
`
`Ri(l,2,2n+2), Ui(l,2,2n+ 1), Ui(l,2,2n+2), J(l,2,n+ 1), K(l,2,n+ 1), L(l,2,n+ 1), and
`
`M(l,2,n+ l); and 4 outputs Bo(l,2,2n+ 1), Bo(l,2,2n+2), Fo(l,2,2n+ 1), and Fo(l,2,2n+2).
`
`The stage (slice 1, ring 2, stage "n") also consists of four 4: 1 Muxes namely F(l,2,2n+ 1 ),
`
`30
`
`F(l,2,2n+2), B(l,2,2n+ 1), and B(l,2,2n+2). The 4: 1 Mux F(l,2,2n+ 1) has four inputs
`-132-
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`Page 386 of 818
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`

`

`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`namely Ri(l,2,2n+ 1), Ri(l,2,2n+2), Ui(l,2,2n+2), and J(l,2,n+ 1), and has one output
`
`Fo(l,2,2n+ 1). The 4: 1 Mux F(l,2,2n+2) has four inputs namely Ri(l,2,2n+ 1),
`
`Ri(l,2,2n+2), Ui(l,2,2n+ 1), and K(l,2,n+ 1), and has one output Fo(l,2,2n+2).
`
`The 4: 1 Mux B(l,2,2n+ 1) has four inputs namely Ui(l,2,n+ 1), Ui(l,2,2n+2),
`
`5
`
`Ri(l,2,2n+2), and L(l,2,n+ 1), and has one output Bo(l,2,2n+ 1). The 4: 1 Mux
`
`B(l,2,2n+2) has four inputs namely Ui(l,2,2n+ 1), Ui(l,2,2n+2), Ri(l,2,2n+ 1) and
`
`M(l,2,n+ 1), and has one output Bo(l,2,2n+2). In different embodiments the inputs
`
`J(l,2,n+l), K(l,2,n+l), L(l,2,n+l), and M(l,2,n+l) are connected from any of the
`
`outputs of any other stages of any ring of any block of the multi-stage hierarchical
`
`10
`
`network Vcamb(Ni,N2 ,d,s).
`
`Just the same way the stage (slice 1, ring 2, stage 0), there are also stages (slice 1,
`
`ring 2, stage 1), (slice 1, ring 2, stage 2), (slice 1, ring 2, stage 3), ... (slice 1, ring 2, stage
`
`"n-1"), (slice 1, ring 2, stage "n") in that order, where the stages from (slice 1, ring 2,
`
`stage 1), (slice 1, ring 2, stage 2), ... , (slice 1, ring 2, stage "n-1") are not shown in the
`
`15
`
`diagram lOOC.
`
`The stage (slice 2, ring 1, stage 0) consists of 8 inputs namely Ri(2, 1, 1 ), Ri(2, 1,2),
`
`Ui(2,1,1), Ui(2,1,2), J(2,1,1), K(2,1,1), L(2,1,1), and M(2,1,l); and 4 outputs Bo(2,1,1),
`
`Bo(2, 1,2), Fo(2, 1,1), and Fo(2, 1,2). The stage (slice 2, ring "1", stage "O") also consists
`
`of four 4:1 Muxes namely F(2,l,1), F(2,1,2), B(2,l,1), and B(2,l,2). The 4:1 Mux
`
`20
`
`F(2,1,1) has four inputs namely Ri(2,1,1), Ri(2,1,2), Ui(2,1,2), and J(2,1,1), and has one
`
`output Fo(2,l,1). The 4:1 Mux F(2,1,2) has four inputs namely Ri(2,1,l), Ri(2,1,2),
`
`Ui(2, 1, 1 ), and K(2, 1, 1 ), and has one output Fo(2, 1,2).
`
`The 4: 1 Mux B(2, 1,1) has four inputs namely Ui(2, 1,1), Ui(2, 1,2), Ri(2, 1,2), and
`
`L(2,1,1), and has one outputBo(2,l,1). The 4:1 Mux B(2,1,2) has four inputs namely
`
`25
`
`Ui(2,1, 1), Ui(2, 1,2), Ri(2, 1, 1) and M(2, 1, 1), and has one output Bo(2, 1,2). In different
`
`embodiments the inputs J(2, 1, 1), K(2, 1, 1), L(2, 1, 1), and M(2, 1, 1) are connected from any
`
`of the outputs of any other stages of any ring of any block of the multi-stage hierarchical
`
`network Vcamb (Ni, N 2 , d, s).
`
`-133-
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`Page 387 of 818
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`

`

`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`The stage (slice 2, ring 1, stage "x") consists of 8 inputs namely Ri(2, l,2x+ 1 ),
`
`Ri(2,l,2x+2), Ui(2,l,2x+l), Ui(2,l,2x+2), J(2,l,x+l), K(2,l,x+l), L(2,l,x+l), and
`
`M(2,l,x+l); and 4 outputs Bo(2,l,2x+l), Bo(2,l,2x+2), Fo(2,l,2x+l), and Fo(2,1,2x+2).
`
`The stage (slice 2, ring 1, stage "x") also consists of four 4: 1 Muxes namely F(2, l ,2x+ 1 ),
`
`5
`
`F(2, l,2x+2), B(2, l,2x+ 1), and B(2, l,2x+2). The 4: 1 Mux F(2, l,2x+ 1) has four inputs
`
`namely Ri(2,l,2x+l), Ri(2,l,2x+2), Ui(2,l,2x+2), and J(2,l,x+l), and has one output
`
`Fo(2, l,2x+ 1). The 4: 1 Mux F(2, l,2x+2) has four inputs namely Ri(2, l,2x+ 1),
`
`Ri(2, l,2x+2), Ui(2, l,2x+ 1), and K(2, l,x+ 1), and has one output Fo(2, l,2x+2).
`
`The 4:1 Mux B(2,l,2x+l) has four inputs namely Ui(2,l,2x+l), Ui(2,l,2x+2),
`
`10
`
`Ri(2,l,2x+2), and L(2,l,x+ 1), and has one output Bo(2, l,2x+ 1). The 4: 1 Mux
`
`B(2, l ,2x+2) has four inputs namely Ui(2, l ,2x+ 1 ), Ui(2, l ,2x+2), Ri(2, l ,2x+ 1) and
`
`M(2, l ,x+ 1 ), and has one output Bo(2, l ,2x+2). In different embodiments the inputs
`
`J(2,l,x+l), K(2,l,x+l), L(2,l,x+l), and M(2,l,x+l) are connected from any of the
`
`outputs of any other stages of any ring of any block of the multi-stage hierarchical
`
`15
`
`network VComb(Ni,N2,d,s).
`
`Just the same way the stage (slice 2, ring 1, stage 0), there are also stages (slice 2,
`
`ring 1, stage 1), (slice 2, ring 1, stage 2), (slice 2, ring 1, stage 3), ... (slice 2, ring 1, stage
`
`"m-1"), (slice 2, ring 1, stage "x") in that order, where the stages from (slice 2, ring 1,
`
`stage 1), (slice 2, ring 1, stage 2), ... , (slice 2, ring 1, stage "x-1") are not shown in the
`
`20
`
`diagram 1 OOC.
`
`The stage (slice 2, ring 2, stage 0) consists of 8 inputs namely Ri(2,2, 1 ), Ri(2,2,2),
`
`Ui(2,2, 1 ), Ui(2,2,2), J(2,2, 1 ), K(2,2, 1 ), L(2,2, 1 ), and M(2,2, 1 ); and 4 outputs Bo(2,2, 1 ),
`
`Bo(2,2,2), Fo(2,2, 1 ), and Fo(2,2,2). The stage (slice 2, ring "2", stage "O") also consists
`
`of four 4: 1 Muxes namely F(2,2, 1 ), F(2,2,2), B(2,2, 1 ), and B(2,2,2). The 4: 1 Mux
`
`25
`
`F(2,2, 1) has four inputs namely Ri(2,2, 1 ), Ri(2,2,2), Ui(2,2,2), and J(2,2, 1 ), and has one
`
`output Fo(2,2, 1). The 4: 1 Mux F(2,2,2) has four inputs namely Ri(2,2,l), Ri(2,2,2),
`
`Ui(2,2, 1 ), and K(2,2, 1 ), and has one output Fo(2,2,2).
`
`The 4: 1 Mux B(2,2,l) has four inputs namely Ui(2,2, 1), Ui(2,2,2), Ri(2,2,2), and
`
`L(2,2, 1 ), and has one output Bo(2,2, 1 ). The 4: 1 Mux B(2,2,2) has four inputs namely
`
`30 Ui(2,2, 1 ), Ui(2,2,2), Ri(2,2, 1) and M(2,2, 1 ), and has one output Bo(2,2,2). In different
`
`-134-
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`Page 388 of 818
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`

`

`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`embodiments the inputs J(2,2, 1 ), K(2,2, 1 ), L(2,2, 1 ), and M(2,2, 1) are connected from any
`
`of the outputs of any other stages of any ring of any block of the multi-stage hierarchical
`
`network VComb(N1,N2,d,s).
`
`The stage (slice 2, ring 2, stage "x") consists of 8 inputs namely Ri(2,2,2x+ 1 ),
`
`5
`
`Ri(2,2,2x+2), Ui(2,2,2x+ 1 ), Ui(2,2,2x+2), J(2,2,x+ 1 ), K(2,2,x+ 1 ), L(2,2,x+ 1 ), and
`
`M(2,2,x+ l); and 4 outputs Bo(2,2,2x+ 1), Bo(2,2,2x+2), Fo(2,2,2x+ 1), and Fo(2,2,2x+2).
`
`The stage (slice 2, ring 2, stage "y") also consists of four 4: 1 Muxes namely F(2,2,2y+ 1 ),
`
`F(2,2,2y+2), B(2,2,2y+ 1), and B(2,2,2y+2). The 4: 1 Mux F(2,2,2y+ 1) has four inputs
`
`namely Ri(2,2,2y+ 1), Ri(2,2,2y+2), Ui(2,2,2y+2), and J(2,2,y+ 1), and has one output
`
`10
`
`Fo(2,2,2y+ 1). The 4: 1 Mux F(2,2,2y+2) has four inputs namely Ri(2,2,2y+ 1),
`
`Ri(2,2,2y+2), Ui(2,2,2y+ 1), and K(2,2,y+ 1), and has one output Fo(2,2,2y+2).
`
`The 4: 1 Mux B(2,2,2y+ 1) has four inputs namely Ui(2,2,2y+ 1 ), Ui(2,2,2y+2),
`
`Ri(2,2,2y+2), and L(2,2,y+ 1), and has one output Bo(2,2,2y+ 1). The 4: 1 Mux
`
`B(2,2,2y+2) has four inputs namely Ui(2,2,2y+ 1 ), Ui(2,2,2y+2), Ri(2,2,2y+ 1) and
`
`15 M(2,2,y+ 1), and has one output Bo(2,2,2y+2). In different embodiments the inputs
`
`J(2,2,y+ 1), K(2,2,y+ 1), L(2,2,y+ 1), and M(2,2,y+ 1) are connected from any of the
`
`outputs of any other stages of any ring of any block of the multi-stage hierarchical
`
`Just the same way the stage (slice 2, ring 2, stage 0), there are also stages (slice 2,
`
`20
`
`ring 2, stage 1), (slice 2, ring 2, stage 2), (slice 2, ring 2, stage 3), ... (slice 2, ring 2, stage
`
`"y-1"), (slice 2, ring 2, stage "y") in that order, where the stages from (slice 2, ring 2,
`
`stage 1), (slice 2, ring 2, stage 2), ... , (slice 2, ring 2, stage "y-1") are not shown in the
`
`diagram 1 OOC.
`
`As illustrated in diagram 100C5 in FIG. 1 C5, the similar internal connections
`
`25
`
`between two successive stages of any ring of any slice of partial multi-stage hierarchical
`
`network Vcamb (N1,N2 ,d,s) IOOC in FIG. IC, in some embodiments are provided for all
`
`the slices c = 1, 2; for all the rings in each of the slices d = 1, 2; and for all the stages
`
`namely when c = 1 d = 1 e = [l m]· when c=l d=2 e=[l n]· when c=2 d=l e=[l x]·
`'
`'
`'
`'
`'
`'
`'
`'
`'
`'
`'
`'
`and when c=2, d=2; e=[l,y].
`
`-135-
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`Application Number: 16/562,450
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`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`Each stage of any ring of the partial multi-stage hierarchical network
`Vcomb(N 1,N2 ,d,s) lOOB consists of 2 * d = 4 outputs. Even though each stage has four
`4: 1 muxes, in other embodiments any of these stages can be one of the four by four
`
`switch diagrams namely 200A of FIG. 2A, 200B of FIG. 2B, 200C of FIG. 2C, and one
`
`5
`
`of the eight by four switch diagrams namely 200E of FIG. 2E, 200F of FIG. 2F.
`
`In general, any ring of the partial multi-stage hierarchical network
`
`Vcomb (N1 , N 2 ,d,s) illustrated in lOOC also may have inputs and outputs connected from
`
`computational block from either only from left-hand side as in the partial multi-stage
`
`hierarchical network Vcomb(N 1,N2 ,d,s) lOOA; or only from right-hand side; or from both
`
`10
`
`left-hand and right-hand sides as in the partial multi-stage hierarchical network
`
`Vcomb(N 1,N2 ,d,s) lOOB.
`
`Applicant now notes a few aspects of the diagram lOOC in FIG. IC an exemplary
`
`partial multi-stage hierarchical network Vcomb (N1 , N 2 , d, s) corresponding to one
`
`computational block, with each computational block having 16 inlet links and 4 outlet
`
`15
`
`links as follows: (Also these aspects are helpful in more optimization of the partial multi(cid:173)
`
`stage hierarchical network Vcamb (N1 , N 2 ,d, s) as well as faster scheduling of the
`
`connections between outlet links of the computational blocks and the inlet links of the
`
`computational blocks.)
`
`1) The partial multi-stage hierarchical network Vcomb(Ni,N2 ,d,s) lOOC in FIG.
`
`20
`
`IC is divided into two slices namely slice 1 and slice 2. The outlet links of the
`
`computational block namely 01 and 02 are connected to only one slice i.e. slice 1. In
`
`other words outlet links O 1 and 02 are absolutely not connected to slice 2. Similarly the
`
`outlet links of the computational block namely 03 and 04 are connected to only one slice
`
`i.e. slice 2. In other words outlet links 03 and 04 are absolutely not connected to slice 1.
`
`25
`
`2) The second aspect is all the hop wires and multi-drop hop wires originating from slice
`
`1 from any block will be terminating only in the slice 1 of any other block. Similarly all
`
`the hop wires and multi-drop hop wires originating from slice 2 from any block will be
`
`terminating only in the slice 2 of any other block. 3) The third aspect is the mux whose
`
`output is directly connected to each inlet link of the computational block must have at
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`-136-
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`Page 390 of 818
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`

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`Application Number: 16/562,450
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`Art Unit: 2464
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`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`least one input connected from each slice of the partial multi-stage hierarchical network
`
`Vcomb (N1, N 2 ,d,s) lOOC. That is for example since the 4: 1 mux B(l, 1,1), belonging to
`
`slice 1, and having its output Bo(l,1,1) directly connected to inlet link Il must have at
`
`least one of its inputs connecting from an output of a mux of a stage of a ring of slice 2 as
`
`5 well. This property must be satisfied for all the inlet links of the partial multi-stage
`
`hierarchical network T,'camb(N1,N2 ,d,s) lOOC.
`
`Referring to diagram lOOCl in FIG. lCl, diagram 100C2 in FIG. 1C2, diagram
`
`100C3 in FIG. 1C3, and diagram 100C4 in FIG. 1C4 illustrate the details of the foregoing
`
`third aspect of the partial multi-stage hierarchical network Vcmnb(N1,N2 ,d,s) lOOC of
`
`10
`
`FIG. IC. Applicant notes that diagram lOOCl in FIG. lCl, diagram 100C2 in FIG. 1C2,
`
`diagram 100C3 in FIG. 1C3, and diagram 100C4 in FIG. 1C4 are all actually part of the
`
`partial multi-stage hierarchical network Vcomb(N1 ,N2 ,d,s) lOOC of FIG. IC and these
`
`separate diagrams are necessary only to avoid the clutter in the diagram lOOC of FIG. 1 C.
`
`The connections illustrated between different slices in diagram lOOCl in FIG.
`
`15
`
`lCl, diagram 100C2 in FIG. 1C2, diagram 100C3 in FIG. 1C3, and diagram 100C4 in
`
`FIG. 1 C4 are the only connections between different slices, in some exemplary
`
`embodiments. In general the connections between different slices are given only at the
`
`terminating muxes i.e. whose outputs are directly connected to one of the inlet links of the
`
`computational block.
`
`20
`
`Referring to diagram 1 OOC 1 in FIG. 1 C 1 illustrate the connections between the
`
`stage (slice 1, ring 1, stage 0) and between the stage (slice 2, ring 1, stage 0). The same
`
`connection that is given to the input Ui(l, 1,1) is also connected to the input L(2, 1, 1). The
`
`same connection that is given to the input Ui(l,1,2) is also connected to the input
`
`M(2, 1, 1 ). Similarly the same connection that is given to the input Ui(2, 1, 1) is also
`
`25
`
`connected to the input L(l,l, 1). The same connection that is given to the input Ui(2,l,2)
`
`is also connected to the input M(l,1,1).
`
`Therefore inlet link 11 can be es sen ti ally connected through the 4: 1 mux B( 1, 1, 1)
`
`with three of its inputs connecting from slice 1 namely Ui(l,1,1), Ui(l,1,2), Ri(l,1,2) and
`
`one input L(l,1,1) connecting from slice 2. The inlet link 12 can be essentially connected
`
`-137-
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`Application Number: 16/562,450
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`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`through the 4:1 mux B(l,1,2) with three of its inputs connecting from slice 1 namely
`
`Ui(l,1, 1), Ui(l, 1,2), Ri(l,l, 1) and one input M(l,1, 1) connecting from slice 2. The inlet
`
`link 19 can be essentially connected through the 4: 1 mux B(l,2, 1) with three of its inputs
`
`connecting from slice 2 namely Ui(2,l, 1), Ui(2,l,2), Ri(2, 1,2) and one input L(2, 1,1)
`
`5
`
`connecting from slice 1. The inlet link 110 can be essentially connected through the 4: 1
`
`mux B(2,l,2) with three of its inputs connecting from slice 2 namely Ui(2,l,l), Ui(2,l,2),
`
`Ri(2, 1, 1) and one input M(2, 1, 1) connecting from slice 1. Hence all the inlet links 11, 12,
`
`19 and 110 are all independently reachable from both slice 1 and slice2.
`
`Referring to diagram 1 OOC2 in FIG. 1 C2 illustrate the connections between the
`
`10
`
`stage (slice 1, ring 2, stage 0) and between the stage (slice 2, ring 2, stage 0). The same
`
`connection that is given to the input Ui(l,2,1) is also connected to the input M(2,2, 1). The
`
`same connection that is given to the input Ui(l,2,2) is also connected to the input
`
`L(2,2, 1 ). Similarly the same connection that is given to the input Ui(2,2, 1) is also
`
`connected to the input M(l,2,1). The same connection that is given to the input Ui(2,2,2)
`
`15
`
`is also connected to the input L(l,2, 1).
`
`Therefore inlet link 13 can be essentially connected through the 4: 1 mux B( 1,2, 1)
`
`with three of its inputs connecting from slice 1 namely Ui(l,2, 1), Ui(l,2,2), Ri(l,2,2) and
`
`one input M(2,2, 1) connecting from slice 2. The inlet link 14 can be essentially connected
`
`through the 4:1 mux B(l,2,2) with three ofits inputs connecting from slice 1 namely
`
`20 Ui(l,2,1), Ui(l,2,2), Ri(l,2,1) and one input M(l,2,1) connecting from slice 2. The inlet
`
`link 11 1 can be essentially connected through the 4: 1 mux B(2,2, 1) with three of its inputs
`
`connecting from slice 2 namely Ui(2,2, 1 ), Ui(2,2,2), Ri(2,2,2) and one input L(2,2, 1)
`
`connecting from slice 1. The inlet link 112 can be essentially connected through the 4:1
`
`mux B(2,2,2) with three of its inputs connecting from slice 2 namely Ui(2,2, 1 ), Ui(2,2,2),
`
`25
`
`Ri(2,2, 1) and one input M(2,2, 1) connecting from slice 1. Hence all the inlet links 13, 14,
`
`111 and 112 are all independently reachable from both slice 1 and slice2.
`
`Referring to diagram 1 OOC3 in FIG. 1 C3 illustrate the connections between the
`
`stage (slice 1, ring 1, stage "m") and between the stage (slice 2, ring 2, stage "y"). The
`
`same connection that is given to the inputRi(l,l,2m+l) is also connected to the input
`
`30
`
`J(2,2,y+ 1). The same connection that is given to the input Ri(l, l,2m+2) is also connected
`
`to the input K(2,2,y+ 1 ). Similarly the same connection that is given to the input
`-138-
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`Page 392 of 818
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`Application Number: 16/562,450
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`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`Ri(2,2,2y+l) is also connected to the input J(l,1,m+l). The same connection that is given
`
`to the input Ri(2,2,2y+2) is also connected to the input K(l, l,m+ 1).
`
`Therefore inlet link I5 can be essentially connected through the 4:1 mux
`
`F(l,l,2m+l) with three of its inputs connecting from slice 1 namely Ri(l,l,2m+l),
`
`5
`
`Ri(l,l,2m+2), Ui(l,l,2m+2) and one input J(l,l,m+l) connecting from slice 2. The inlet
`
`link I6 can be essentially connected through the 4:1 mux F(l,l,2m+2) with three of its
`
`inputs connecting from slice 1 namely Ri(l, l,2m+ 1), Ri(l, l,2m+2),Ui(l, l,2m+ 1) and
`
`one input K(l, l,m+ 1) connecting from slice 2. The inlet link Il 5 can be essentially
`
`connected through the 4: 1 mux F(2,2,2y+ 1) with three of its inputs connecting from slice
`
`10
`
`2 namely Ri(2,2,2y+ 1 ), Ri(2,2,2y+2), Ui(2,2,2y+2) and one input J(2,2,y+ 1) connecting
`
`from slice 1. The inlet link Il6 can be essentially connected through the 4:1 mux
`
`F(2,2,2y+2) with three of its inputs connecting from slice 2 namely Ri(2,2,2y+ 1 ),
`
`Ri(2,2,2y+2), Ui(2,2,2y+ 1) and one input K(2,2,y+ 1) connecting from slice 1. Hence all
`
`the inlet links I5, I6, Il5 and Il6 are all independently reachable from both slice 1 and
`
`15
`
`slice2.
`
`Referring to diagram 1 OOC4 in FIG. 1 C4 illustrate the connections between the
`
`stage (slice 1, ring 2, stage "n") and between the stage (slice 2, ring 1, stage "x"). The
`
`same connection that is given to the input Ri(l,2,2n+ 1) is also connected to the input
`
`K(2, l,x+ 1). The same connection that is given to the input Ri(l,2,2n+2) is also connected
`
`20
`
`to the input J(2, l,x+ 1 ). Similarly the same connection that is given to the input
`
`Ri(2,l,2x+ 1) is also connected to the input K(l,2,n+ 1). The same connection that is given
`
`to the input Ri(2, l,2x+2) is also connected to the input J(l,2,n+ 1).
`
`Therefore inlet link I7 can be essentially connected through the 4: 1 mux
`
`F(l,2,2n+ 1) with three of its inputs connecting from slice 1 namely Ri(l,2,2n+ 1),
`
`25
`
`Ri(l ,2,2n+2), Ui(l ,2,2n+2) and one input J (1,2,n+ 1) connecting from slice 2. The inlet
`
`link I8 can be essentially connected through the 4: 1 mux F(l,2,2n+2) with three of its
`
`inputs connecting from slice 1 namely Ri(l,2,2n+l), Ri(l,2,2n+2),Ui(l,2,2n+l) and one
`
`input K( 1,2,n+ 1) connecting from slice 2. The inlet link Il 3 can be essentially connected
`
`through the 4:1 mux F(2,1,2x+l) with three of its inputs connecting from slice 2 namely
`
`30 Ri(2,l,2x+l), Ri(2,1,2x+2), Ui(2,l,2x+2) and one input J(2,l,x+l) connecting from slice
`
`1. The inlet link Il4 can be essentially connected through the 4: 1 mux F(2, l,2x+2) with
`-139-
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`Page 393 of 818
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`

`

`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`three of its inputs connecting from slice 2 namely Ri(2,1,2x+ 1), Ri(2,1,2x+2),
`
`Ui(2, l ,2x+ 1) and one input K(2, l ,x+ 1) connecting from slice 1. Hence all the inlet links
`
`I7, I8, Il3 and Il4 are all independently reachable from both slice 1 and slice2.
`
`The connections illustrated between different slices, in several embodiments, in
`
`5
`
`diagram lOOCl in FIG. lCl, diagram 100C2 in FIG. 1C2, diagram 100C3 in FIG. 1C3,
`
`and diagram 1 OOC4 in FIG. 1 C4 are the only connections between different slices. And
`
`also the terminating muxes i.e. whose outputs are directly connected to one of the inlet
`
`links of the computational block have three inputs coming from one slice and one input
`
`coming from another slice. In other embodiments it is also possible so that the
`
`10
`
`terminating muxes i.e. whose outputs are directly connected to one of the inlet links of the
`
`computational block have two inputs coming from one slice and two inputs coming from
`
`another slice.
`
`Also in general the number of slices in the partial multi-stage hierarchical network
`
`Vcomb(N 1,N2 ,d,s) lOOC of FIG. IC may be more than or equal to two. In such a case
`
`15
`
`terminating muxes i.e. whose outputs are directly connected to one of the inlet links of the
`
`computational block will have at least one input coming from each slice. And the outlet
`
`links of the computational block will be divided and connected to each slice; however
`
`each outlet link of the computational block will be connected to only one slice. Also in
`
`general the hop wires and multi-drop hop wires are connected to only between the
`
`20
`
`corresponding slices of different blocks, in some embodiments some of the hop wires
`
`and multi-drop hop wires may be connected between different slices of different blocks
`
`even if it is done partially.
`
`FIG. 2A illustrates a stage (ring "k", stage "m") 200A consists of 4 inputs namely
`
`Fi(k,2m+ 1 ), Fi(k,2m+2), Ui(k,2m+ 1 ), and Ui(k,2m+2); and 4 outputs Bo(k,2m+ 1 ),
`
`25
`
`Bo(k,2m+2), Fo(k,2m+ 1 ), and Fo(k,2m+2). The stage (ring "k", stage "m") also consists
`
`of six 2: 1 Muxes namely F(k,2m+ 1), F(k,2m+2) (comprising in combination a forward
`
`switch), U(k,2m+ 1 ), U(k,2m+2) ( comprising in combination a U-turn switch),
`
`B(k,2m+ 1 ), and B(k,2m+2) ( comprising in combination a backward switch). The 2: 1
`
`Mux F(k,2m+ 1) has two inputs namely Fi(k,2m+ 1) and Fi(k,2m+2) and has one output
`
`30
`
`Fo(k,2m+ 1). The 2: 1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+ 1) and Fi(k,2m+2)
`
`and has one output Fo(k,2m+2).
`
`-140-
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`Page 394 of 818
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`

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`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`The 2:1 Mux U(k,2m+l) has two inputs namely Ui(k,2m+l) and Fo(k,2m+l) and
`
`has one output Uo(k,2m+ 1). The 2: 1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2)
`
`and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2: 1 Mux B(k,2m+ 1) has two inputs
`
`namely Uo(k,2m+l) and Uo(k,2m+2) and has one output Bo(k,2m+l). The 2:1 Mux
`
`5
`
`B(k,2m+2) has two inputs namely Uo(k,2m+l) and Uo(k,2m+2) and has one output
`
`Bo(k,2m+2).
`
`FIG. 2B illustrates a stage (ring "k", stage "m") 200B consists of 4 inputs namely
`
`Ri(k,2m+ 1 ), Ri(k,2m+2), Ui(k,2m+ 1 ), and Ui(k,2m+2); and 4 outputs Bo(k,2m+ 1 ),
`
`Bo(k,2m+2), Fo(k,2m+ 1 ), and Fo(k,2m+2). The stage (ring "k", stage "m") also consists
`
`10
`
`of eight 2: 1 Muxes namely R(k,2m+ 1), R(k,2m+2) (comprising in combination a Reverse
`
`U-turn switch), F(k,2m+ 1), F(k,2m+2) (comprising in combination a forward switch),
`
`U(k,2m+l), U(k,2m+2) (comprising in combination a U-turn switch), B(k,2m+l), and
`
`B(k,2m+2) ( comprising in combination a backward switch). The 2: 1 Mux R(k,2m+ 1) has
`
`two inputs namely Ri(k,2m+ 1) and Bo(k,2m+ 1) and has one output Ro(k,2m+ 1). The 2: 1
`
`15 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output
`
`Ro(k,2m+2). The 2:1 Mux F(k,2m+l) has two inputs namely Ro(k,2m+l) and
`
`Ro(k,2m+2) and has one output Fo(k,2m+ 1 ). The 2: 1 Mux F(k,2m+2) has two inputs
`
`namely Ro(k,2m+ 1) and Ro(k,2m+2) and has one output F o(k,2m+2).
`
`The 2:1 Mux U(k,2m+l) has two inputs namely Ui(k,2m+l) and Fo(k,2m+l) and
`
`20
`
`has one output Uo(k,2m+ 1 ). The 2: 1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2)
`
`and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2: 1 Mux B(k,2m+ 1) has two inputs
`
`namely Uo(k,2m+l) and Uo(k,2m+2) and has one output Bo(k,2m+l). The 2:1 Mux
`
`B(k,2m+2) has two inputs namely Uo(k,2m+ 1) and Uo(k,2m+2) and has one output
`
`Bo(k,2m+2).
`
`25
`
`FIG. 2C illustrates a stage (ring "k", stage "m") 200C consists of 4 inputs namely
`
`Fi(k,2m+ 1), Fi(k,2m+2), Ui(k,2m+ 1), and Ui(k,2m+2); and 4 outputs Uo(k,2m+ 1),
`
`Uo(k,2m+2), Fo(k,2m+l), and Fo(k,2m+2). The stage (ring "k", stage "m") also consists
`
`of four 2: 1 Muxes namely F(k,2m+ 1 ), F(k,2m+2) ( comprising in combination a forward
`
`switch), U(k,2m+ 1 ), and U(k,2m+2) ( comprising in combination a U-turn switch). The
`
`30
`
`2: 1 Mux F(k,2m+ 1) has two inputs namely Fi(k,2m+ 1) and Fi(k,2m+2) and has one
`
`-141-
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`Page 395 of 818
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`Application Number: 16/562,450
`
`Art Unit: 2464
`
`AMENDMENT AFTER ALLOWANCE UNDER RULE 312, Contd.
`
`output Fo(k,2m+ 1). The 2: 1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+ 1) and
`
`Fi(k,2m+2) and has one output Fo(k,2m+2).
`
`The 2: 1 Mux U(k,2m+ 1) has two inputs namely Ui(k,2m+ 1) and Ui(k,2m+2) and
`
`has one output Uo(k,2m+l). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+l)
`
`5
`
`and Ui(k,2m+2) and has one output Uo(k,2m+2).
`
`However the stage "m" of ring "k" with "m" stages of the partial multi-stage
`
`hierarchical network Vcomb(N 1,N2 ,d,s), in another embodiment, may have 2 inputs and
`
`2 outputs as shown in diagram 200D in FIG. 2D. FIG. 2D illustrates a stage (ring "k",
`
`stage "m") 200D consists of 2 inputs namely Fi(k,2m+ 1) and Fi(k,2m+2); and 2 outputs
`
`10
`
`Fo(k,2m+ 1) and Fo(k,2m+2). The stage (ring "k", stage "m") also consists of two 2: 1
`
`Muxes namely F(k,2m+ 1 ), F(k,2m+2) ( comprising in combination a forward switch). The
`
`2: 1 Mux F(k,2m+ 1) has two inputs namely Fi(k,2m+ 1) and Fi(k,2m+2) and has one
`
`output Fo(k,2m+ 1). The 2: 1 Mux F(k,2m+