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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG DISPLAY CO., LTD. AND DELL INC.,
`Petitioner,
`
`v.
`
`SOLAS OLED, LTD.,
`Patent Owner.
`
`Case No. IPR2020-00140
`U.S. Patent No. 6,072,450
`
`PETITIONER’S REPLY TO PATENT OWNER RESPONSE
`
`
`
`

`

`IPR2020-00140
`
`LIST OF EXHIBITS
`
`
`Description
`U.S. Patent No. 6,072,450 (the “’450 patent”)
`File History for U.S. Patent No. 6,072,450
`U.S. Patent No. 5,670,792 (“Utsugi”)
`JPH053079 (certified translation, “Manabe”)
`WO 96/25020 (certified translation, “Eida”)
`S.W. Amos, Principles of Transistor Circuits, 8th Ed. (1994)
`Declaration of Dr. Adam Fontecchio
`Curriculum Vitae of Dr. Adam Fontecchio
`JPH053079 (“Manabe”)
`WO 96/25020 (“Eida”)
`U.S. Patent No. 5,847,516 (“Kishita”)
`Claim Construction Memorandum & Order, Solas OLED Ltd. v.
`Samsung Display Co., Ltd. et al., 2:19-cv-00152-JRG (E.D.
`Tex. Apr. 17, 2020)
`Frisch declaration
`Lerner declaration
`Haslam declaration
`Claim Construction Order, Solas OLED Ltd. v. Dell Inc., et al.,
`6:19-CV-00514, -00515, -00537 (W.D. Tex. August 30, 2020)
`Transcript of Deposition of Richard Flasck (November 11,
`2020)
`
`
`
`Exhibit
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`1012
`
`1013
`1014
`1015
`1016
`
`1017
`
`
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`IPR2020-00140
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`Table of Contents
`
`B.
`
`C.
`
`I.
`Introduction ...................................................................................................... 1
`Level of Ordinary Skill .................................................................................... 1
`II.
`III. Claim Construction .......................................................................................... 1
`IV. Grounds I and II: Anticipation and Obviousness Based on Utsugi ................. 3
`A.
`Limitation 1[c]: “an insulation film formed over said substrate
`so as to cover said active elements, said insulation having at
`least one contact hole” ........................................................................... 3
`1.
`Anticipation ................................................................................. 3
`2.
`Obviousness ................................................................................ 9
`Limitations 4[a]/4[b]: “The display apparatus according to
`claim 1, wherein said active elements are a selection transistor .
`. . and a drive transistor” ..................................................................... 12
`Claim 8: “The display apparatus according to claim 1, wherein
`a constant voltage is applied to said second electrode” ...................... 13
`1.
`Anticipation ............................................................................... 13
`2.
`Obviousness .............................................................................. 16
`Limitation 15[f]: “an insulation film formed over said substrate
`so as to cover said drive transistors, said address lines and said
`data lines, said insulation film having contact holes formed in
`correspondence with said drive transistors” ........................................ 17
`1.
`Anticipation ............................................................................... 17
`2.
`Obviousness .............................................................................. 19
`Limitation 15[j]: “a first driver circuit for selectively supplying
`said address signal to said address lines in sequence; and”
`/Limitation 15[k]: “a second driver circuit for supplying said
`image data to said data lines” .............................................................. 21
`1.
`Anticipation ............................................................................... 21
`
`D.
`
`E.
`
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`IPR2020-00140
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`2.
`Obviousness .............................................................................. 23
`V. Grounds III and IV: No Independent Disputes .............................................. 24
`
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`IPR2020-00140
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`I.
`
`INTRODUCTION
`As explained in the Petition (Paper 1, “Pet.”), claims 1–9, 11–13, and 15–18
`
`of U.S. Patent No. 6,072,450 (’450 patent) are unpatentable.
`
`Patent Owner Solas OLED, Ltd. (“Solas”)’s Response (Paper 20, “POR”)
`
`abandons the lead arguments from its Preliminary Response, in which it questioned
`
`whether Utsugi’s electroluminescent layer emits light in accordance with a voltage,
`
`whether Utsugi’s SiO2 layer is an insulating film, and whether Utsugi’s MgAg
`
`electron injection electrode shields visible light.
`
`Solas’s Response advances a new set of arguments that equally lack merit, as
`
`discussed below.
`
`II. LEVEL OF ORDINARY SKILL
`The parties articulate similar definitions of the level of ordinary skill. Solas
`
`merely criticizes Petitioner’s definition “to the extent” it does not specify a length of
`
`work experience. POR, 7–8. However, the differences in how the parties have
`
`articulated the skill level do not impact any of the patentability issues here. See id.,
`
`8 (acknowledging “the arguments in this response apply under petitioners’
`
`definition”); Ex. 1017, 77:13–19.
`
`III. CLAIM CONSTRUCTION
`Neither party has raised any claim construction disputes. Petitioner continues
`
`to believe that no specific constructions are necessary for this IPR. See Pet., 13. Solas
`
`does not contend otherwise.
`
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`IPR2020-00140
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`After the Petition was filed, the parties agreed to constructions for the “active
`
`elements” and “rough electrode” limitations in related district court litigation (Ex.
`
`1012) and the district court construed the term “cover” in a supplemental order (Ex.
`
`2006), as shown below.
`
`Claim Term
`“active elements” (claim 1)
`
`“wherein said at least one first
`electrode has a rough surface which is
`in contact with the said organic
`electroluminescent layer” (claim 12)
`
`District Court Construction
`“circuit elements that have gain or that
`direct current flow, e.g., transistors”
`
`(Ex. 1012, 7)
`
`“wherein said at least one first
`electrode is formed to have a
`substantially uneven surface in contact
`with the organic electroluminescent
`layer”
`
`(Ex. 1012, 7)
`
`cover (claims 1, 15)
`
`“lie over the surface of”
`
`(Ex. 2006, 14)
`
`
`
`The Petition is fully consistent with these constructions. For example, the
`
`“active elements” construction is consistent with the Petition’s explanation that
`
`“‘active elements’ should be interpreted to encompass transistors (at a minimum).”
`
`Pet., 14.
`
`In any event, the Board does not need to resolve any claim construction issues
`
`because Solas does not raise any arguments hinging on claim construction. Indeed,
`
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`IPR2020-00140
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`Solas states, “[u]nless otherwise noted, the arguments set forth in this declaration
`
`[sic, response brief] apply both under these constructions and under the plain
`
`meaning.” POR, 9; see Ex. 1017, 80:14–18 (Solas’s expert testifying “I don’t recall
`
`any instances” where claim constructions would impact opinions).1
`
`IV. GROUNDS I AND II: ANTICIPATION AND OBVIOUSNESS BASED
`ON UTSUGI
`Solas does not contest the Petition’s showing that Utsugi discloses all
`
`elements of claims 1–2, 4–8, and 15–16 (Pet., 22–53), except for independent claim
`
`limitations 1[c], 15[f], and 15[j]/[k], and dependent claim limitations 4[a]/[b] and
`
`claim 8. Solas does not raise any additional disputes about dependent claims 2, 5–7,
`
`or 16. See POR, 9.
`
`A. Limitation 1[c]: “an insulation film formed over said substrate so
`as to cover said active elements, said insulation having at least one
`contact hole”
`Anticipation
`1.
`Utsugi discloses an insulation film—an SiO2 layer—that covers both active
`
`elements (transistors) and satisfies this limitation. Pet., 24–25. In Utsugi,
`
`immediately after transistors QS and QI are formed, a 200nm SiO2 layer is grown on
`
`
`1 In another parallel lawsuit, the parties agreed to the same construction of “active
`
`elements” and to correct a typo in claim 12, replacing “light lays” with “light
`
`rays.” Ex. 1016, 3. This is likewise consistent with the Petition.
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`IPR2020-00140
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`the transistors (and over the entire array). Ex. 1003, 7:35–52. Utsugi even provides
`
`Figure 5, a cross-section showing the SiO2 layer formed on transistor QI.
`
`Solas does not dispute (a) that Utsugi’s SiO2 layer is insulating, (b) that it
`
`includes a contact hole, and (c) that it covers Utsugi’s current-controlling transistor
`
`QI. POR, 10–14. Moreover, Solas’s expert concedes that an insulating film would
`
`need to be formed over both transistors for Utsugi’s display to function, because the
`
`absence of an insulating film over switching transistor QS would lead to a short
`
`circuit. See Ex. 1017, 155:8–16.
`
`Solas asserts that the SiO2 layer “does not necessarily cover” Utsugi’s
`
`switching transistor QS, because Figure 5 does not illustrate QS with the insulation
`
`film covering it. POR, 10–12. This argument has no merit. See, e.g., Arlington
`
`Indust., Inc. v. Bridgeport Fittings, Inc., 632 F.3d 1246, 1254 (Fed. Cir. 2011)
`
`(“[D]rawings in a patent need not illustrate the full scope of the invention.”). Figure
`
`5 shows a cross-section along line A–A shown in Figure 4. Ex. 1003, 5:42. Due to
`
`where this cross-section is taken, transistor QS is not visible, and hence Figure 5 does
`
`not depict the insulating film covering this transistor. There was no need for Utsugi
`
`to provide a separate cross-sectional figure depicting switching transistor QS,
`
`because Utsugi disclosed the manufacturing steps that formed both transistors and
`
`the layers above them; Utsugi’s disclosures show that the SiO2 layer is deposited
`
`over the entire array (including both transistors QS and QI), and patterned only to
`
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`open contact holes. See Ex. 1003, 7:47–52; Ex. 1007, 82–84. Therefore, a POSA
`
`would understand this insulating layer covers QS. See Pet., 24–25.
`
`As Petitioner’s expert Dr. Fontecchio explained, Utsugi describes a
`
`manufacturing process in which layers (including the SiO2 layer) are sequentially
`
`deposited (or “grown”) across the entire substrate, and then patterned (selectively
`
`removed) with processes such as etching. Ex. 1007, ¶ 84. The process begins with a
`
`glass base. Ex. 1003, 7:20–21. Both transistors (QS and QI,) are subsequently formed,
`
`starting with their gate electrodes, id., 7:21–25, and ending with their drain and
`
`source electrodes and the etching of the a-Si TFT islands, id., 7:35–45. Utsugi then
`
`discloses growing the relevant SiO2 layer—immediately after transistors QS and QI
`
`have been formed—and patterning this layer only where the contact holes are located:
`
`Then, a SiO2 layer is let grow 200 nm, before an etching to open the
`second contact holes 56B for intercommunication between the source
`electrode SQI of the current-controlling transistor QI, and the electron
`injection electrode 55 . . . .
`
`Ex. 1003, 7:47–52. Utsugi does not disclose removing any portion of this layer other
`
`than for creation of contact holes. Therefore, a POSA would understand that the SiO2
`
`layer is formed as a continuous layer on top of the transistors, patterned only where
`
`contact holes are located. See Ex. 1007, ¶ 84; Ex. 2005, 49:20–51:7. Figure 5
`
`reinforces that the SiO2 layer is continuous apart from the contact holes, e.g., 56B:
`
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`IPR2020-00140
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`
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`Solas does not dispute that the SiO2 layer is formed by a deposition/patterning
`
`process after the formation of transistors QI and QS. Instead, Solas speculates that
`
`performing other process steps not disclosed or even suggested in Utsugi could result
`
`in the SiO2 layer not covering transistor QS. Specifically, Solas asserts the SiO2 layer
`
`“does not necessarily cover the transistor” because either (i) a “mask” could be used
`
`to prevent the SiO2 layer from being deposited above QS, or (ii) the SiO2 layer “may
`
`be removed” from this location by etching. POR, 12. However, Utsugi’s
`
`manufacturing process does not include such masking or etching steps—and these
`
`would increase the number of process steps required. Solas does not articulate any
`
`reason why a POSA would allegedly read Utsugi to employ such undisclosed
`
`processes. And Mr. Flasck’s declaration is of little to no probative value on this issue;
`
`it merely repeats, near-verbatim, the Response’s conclusory assertions and offers no
`
`factual analysis or citation to evidence. Compare POR, 12 with Ex. 2001, ¶ 54.
`
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`IPR2020-00140
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`Tellingly, Solas fails to identify any evidence that Utsugi discloses use of a
`
`mask to prevent the SiO2 layer from being deposited over QS, or that it discloses
`
`etching the portion of the SiO2 layer formed over QS. Solas’s expert, Mr. Flasck,
`
`admitted in deposition he knows of no such evidence. Ex. 1017, 129:17–130:9
`
`(“Q. . . . [I]s there any reason or is there any evidence in Utsugi suggesting this other
`
`approach that you’re hypothesizing of selective deposition [i.e., masking] in the first
`
`place? A. Well -- Q. If there is, please cite it. A. Well, I would say that Dr. Fontecchio
`
`was the one that brought up the -- the possibilities of selective deposition . . . . But,
`
`again, the burden’s not on me . . . .”); id. at 149:8–151:5 (“Q. Okay. And you haven’t
`
`identified anything specific in Utsugi that discusses or suggests patterning or etching
`
`the SiO2 layer above the QS transistor, have you? A. I -- I’ve -- I haven’t seen
`
`anything in Utsugi that specifically says that the SiO2 layer is etched from -- from
`
`QS.”) (emphasis added).
`
`Solas resorts to asserting, inaccurately, that “Petitioners acknowledge” that
`
`“the SiO2 layer may not be deposited over QS in the first place because a mask is
`
`used to prevent it from being deposited there.” POR, 12. Solas cites to testimony of
`
`Dr. Fontecchio (Ex. 1007, ¶¶ 84, 147), but this testimony flatly contradicts Solas’s
`
`assertion: Dr. Fontecchio explains that “in semiconductor manufacturing, . . . layers
`
`can be deposited on select areas of the substrate, using, for instance, a mask, or the
`
`layers can be applied across the entire substrate, . . . [and] Utsugi describes the
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`IPR2020-00140
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`latter technique.” Ex. 1007, ¶¶ 84, 147 (emphasis added). As Dr. Fontecchio makes
`
`clear, the layers in Utsugi—including the SiO2 layer—are deposited across the entire
`
`display. Indeed, Utsugi does not describe any of its layers as being selectively
`
`deposited. As to etching, Solas does not cite any evidence that Utsugi discloses or
`
`even suggests etching the SiO2 layer above QS (Utsugi does not). POR, 12. In fact,
`
`Solas’s expert could not articulate any reason why a POSA would purportedly
`
`contemplate such etching (which would require adding a different insulating film to
`
`avoid short circuit). See Ex. 1017, 129:17–130:9 (“Q. Is there anything specific that
`
`you can point to that would cause a POSA to contemplate removing the SiO2 from
`
`above QS, given that that would -- A. Okay. The -- the -- developing a manufacturing
`
`process for these types of active matrix displays is a very complex, subtle process. . . .
`
`It’s not simple, and it’s not something that can be done in the middle of a deposition.”
`
`(emphasis added)).
`
`Finally, a POSA would understand that Utsugi’s SiO2 insulation film covers
`
`switching transistor QS to prevent “shorting of the source and drain electrodes of the
`
`transistors and the electron injection electrode 55” (which would cause the device to
`
`malfunction). Pet., 25 (citing Ex. 1007, ¶ 84). Mr. Flasck admitted insulation is
`
`necessary between electrode 55 and transistor QS. Ex. 1017, 155:8–14 (agreeing
`
`“[t]here would be something necessary to insulate the source and drain of Transistor
`
`QS from Electrode 55 to prevent . . . a short across QS”). Solas also does not dispute
`
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`IPR2020-00140
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`the need to insulate QS from electrode 55. POR, 12. Solas asserts that, in theory, “a
`
`different insulating material could be deposited” or “the upper surfaces of the source
`
`and drain electrodes could be oxidized.” Id. But Solas disregards that Utsugi
`
`expressly discloses the SiO2 layer as the insulation, and Utsugi does not disclose
`
`these alternative insulation methods.
`
`2. Obviousness
`Additionally, even if Utsugi had not disclosed that its SiO2 layer covers the
`
`switching transistor QS, it would have been obvious to form the layer to cover this
`
`transistor. See Pet., 54–56.
`
`As explained above, Utsugi’s SiO2 insulation layer is deposited over the array
`
`after transistors QS and QI have been formed, and its very purpose is to form an
`
`insulation layer. It is used as an insulating layer above transistor QI, as shown in
`
`Figure 5. Mr. Flasck further admits that an insulation above transistor QS is necessary
`
`to prevent a short circuit. See Ex. 1017, 155:8–16. It would have been obvious (at a
`
`minimum) to leave the SiO2 insulation layer in place above transistor QS to insulate
`
`that transistor, just as it is used to insulate transistor QI. See Ex. 1007, ¶¶ 168–170.
`
`Indeed, using Utsugi’s SiO2 insulation layer to provide the insulation above
`
`transistor QS would be the most natural and straightforward implementation of
`
`Utsugi’s disclosures: it would entail simply not undertaking an undisclosed and
`
`unnecessary additional step of patterning or masking the SiO2 insulation to remove
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`IPR2020-00140
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`it from the area above transistor QS. Solas’s assertions would require adding steps
`
`that (a) are not disclosed in Utsugi (Solas identifies nothing in Utsugi suggesting
`
`such patterning or masking), (b) are unnecessary (the SiO2 layer would otherwise
`
`provide the necessary insulation), and (c) would create a need to add a replacement
`
`insulation layer (since insulation is necessary to prevent the source and drain of QS
`
`from short-circuiting with electrode 55).
`
`While Solas asserts that in theory “a different insulating material could be
`
`deposited” or “the upper surfaces of the source and drain electrodes could be
`
`oxidized to form an insulating film,” POR, 12 (emphases added)), these purported
`
`alternatives—which are nowhere referenced in or suggested by Utsugi—would
`
`require additional process steps that would increase cost and complexity, for no
`
`reason. See Ex. 1017, 155:20–22 (“Engineers try to . . . avoid any unnecessary
`
`process steps.”). Solas makes only a bare assertion that Utsugi’s SiO2 layer is not the
`
`“most effective, or most efficient way to avoid such a short.” POR, 12. And Solas
`
`cites only Mr. Flasck’s declaration, which merely repeats verbatim the same
`
`conclusory assertion with no factual explanation or evidence (Ex. 2001, ¶ 55).
`
`Solas fails to explain, let alone demonstrate, why a POSA would add these
`
`unnecessary further manufacturing steps rather than use the SiO2 layer over the
`
`transistor QS, when Solas admits that layer is insulating and Utsugi uses it to cover
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`IPR2020-00140
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`the other transistor, QI.2 At deposition, Mr. Flasck could not articulate any reason
`
`why a POSA would undertake gratuitous removal of the SiO2 insulating film, when
`
`doing so would require adding another insulating layer. Ex. 1017, 156:6–17.
`
`Finally, Solas attempts to take issue with the Petition’s discussion of Figure
`
`23 of the ’450 patent, arguing it is not prior art. POR, 13. This is a distraction, as
`
`element 1[c] is obvious based on Utsugi alone, for the reasons described above and
`
`in the Petition. Figure 23 is cited in the Petition as further confirmation of the
`
`predictability of the result. Pet., 55. In any event, Figure 23 is properly regarded as
`
`evidence of general knowledge of a POSA, consistent with the Director’s August 18,
`
`
`2 In deposition, Mr. Flasck introduced a new hypothesis that he believes Utsugi
`
`purportedly (i) “requires some other conductor line which is not described,” and
`
`(ii) “that other conductor line may be thick” such that (iii) “it may require some
`
`type of additional planarization layer” (iv) which layer could “act[] as the insulator
`
`over the scan transistor, in being different than . . . the SiO2 layer that is over the
`
`. . . drive transistor.” Ex. 1017, 116:14–117:1 (emphases added). He cited no
`
`evidence for this speculation. Yet even if a POSA did want to add a planarization
`
`layer to Utsugi, Mr. Flasck fails to explain why the POSA would also undertake
`
`the unnecessary extra step of removing the SiO2 insulation layer from above
`
`transistor QS.
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`2020 memorandum, since the figure is discussed in the ’450 patent’s “Description
`
`of the Related Art” section as a known existing approach. See Ex. 1001, 1:58–2:37;
`
`Memorandum: Treatment of Statements of the Applicant in the Challenged Patent
`
`in
`
`Inter
`
`Partes
`
`Reviews
`
`Under
`
`§
`
`311
`
`(available
`
`at
`
`https://www.uspto.gov/sites/default/files/documents/signed_aapa_guidance_memo.
`
`pdf). Although Solas selectively quotes a statement that Figures 22 and 23 propose
`
`“a display apparatus free from the above-described problems,” POR, 13, the ’450
`
`patent proceeds to explain that the display shown in Figures 22 and 23, while an
`
`improvement over passive matrix designs, suffered its own shortcomings that the
`
`alleged invention of the ’450 patent is directed at solving. See Ex. 1001, 2:32–37
`
`(“In the active matrix type EL display apparatus described above [in Figures 22 and
`
`23], the light emitting area of each pixel . . . is limited to an area in which the thin
`
`film transistors T1 and T2 are not located, and therefore the ratio of the light emitting
`
`area to the pixel area is small.”). Finally, the patent describes Figure 22 as depicting
`
`a display apparatus “according to the related art,” id., 5:12–13, with Figure 23
`
`providing a “sectional view” of this apparatus, see Pet., 55 n.5.
`
`B.
`
`Limitations 4[a]/4[b]: “The display apparatus according to claim
`1, wherein said active elements are a selection transistor . . . and a
`drive transistor”
`As the Petition explained, Utsugi discloses the additional limitations of claim
`
`4. Pet., 31–33. Solas offers no substantive response. Although the Response includes
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`IPR2020-00140
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`a section on limitations 4[a]/4[b], it does not provide any arguments as to why Utsugi
`
`supposedly does not teach or suggest these limitations beyond those articulated for
`
`limitation 1[c]—namely, that the Petition allegedly fails to establish that Utsugi’s
`
`insulating film is formed so as to cover the selection transistor (switching transistor
`
`QS), or that it would have been obvious to form it in this way. POR, 14–15. Solas’s
`
`arguments are unavailing as discussed above for limitation 1[c].
`
`C. Claim 8: “The display apparatus according to claim 1, wherein a
`constant voltage is applied to said second electrode”3
`Anticipation
`1.
`Utsugi discloses this limitation based on its disclosures on the “power source
`
`electrode line” through which a voltage “VDD” is applied to the relevant electrode.
`
`As the Petition explains, POSA would understand VDD to be a constant voltage. Pet.,
`
`40 (citing Ex. 1007, ¶ 129).
`
`As shown below in annotated Figure 3, Utsugi’s “power source electrode line
`
`5” carries line voltage VDD, which is applied to each of the electroluminescent (EL)
`
`elements (via hole injection electrode 54 the claimed “second electrode” see Pet.,
`
`30–31). See Ex. 1003, 6:43–47 (“electrode 54 corresponds to a power source
`
`electrode line 5”).
`
`
`3 Solas’s Response does not independently address claim 16. Utsugi anticipates and
`
`renders obvious claim 16 for the same reasons explained for claim 8.
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`
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`As Dr. Fontecchio explained in his declaration, and reiterated in his deposition,
`
`the term VDD is understood to refer to a constant DC voltage. Ex. 1007, ¶ 129 (“A
`
`POSA would appreciate that the term VDD is understood to refer to a direct current
`
`(DC) supply, as opposed to an alternating current (AC) supply, and would thus refer
`
`to a constant voltage source.”); Ex. 2005, 54:14–18 (“Q. And do you know why the
`
`letter ‘D’ appears twice to represent the voltage on the drain. A. I think it’s because
`
`it’s the DC line. So I think it’s voltage DC drain.”); id., 57:14–23 (“. . . And one of
`
`the stories I found was that originally to delineate source and drain, it was the DC
`
`drain . . . .”).
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`IPR2020-00140
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`Dr. Fontecchio also substantiated that VDD is understood to refer to a DC
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`supply voltage with a contemporary reference manual, the Principles of Transistor
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`Circuits. See 1007, ¶ 129 (citing Ex. 1006).
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`While Solas attempts to create confusion by focusing on the meaning of the
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`“DD” nomenclature, neither Solas nor Mr. Flasck provide any reason to question the
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`common understanding that VDD refers to a DC supply voltage. See POR, 16; Ex.
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`2001, ¶ 61. Nor does Solas or Mr. Flasck provide any evidence to substantiate their
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`speculation that the DC supply voltage of Utsugi might be anything other than a
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`constant voltage. See id.
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`Other disclosures of Utsugi reinforce that VDD is a constant voltage. Utsugi
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`describes an experiment “with a drive voltage of 7 V applied [across the EL
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`element].” Ex. 1003, 8:32–36. The description of a “drive voltage of 7 V” supports
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`the understanding that VDD is a constant voltage, as the Petition explained, as does
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`the fact that Utsugi does not discuss VDD ever changing. Pet., 40. Solas asserts that
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`VDD would need “to change over time” to maintain a constant voltage across the EL
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`element during the brief period when the associated scan line is selected. POR, 17.
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`However, there is no discussion of VDD changing in Utsugi, and Utsugi’s second
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`embodiment is inconsistent with such a notion. This embodiment adds a diode DI
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`between the EL element and the power source line 5, to prevent a “reverse voltage”
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`being applied across the EL element at the times when the scan electrode line 3N has
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`“a higher voltage . . . than the line voltage VDD.” See Ex. 1003, Fig. 6, 9:39–64. If
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`the “line voltage VDD” could be changed over time, no such diode would be
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`necessary, as VDD could instead be increased to avoid the formation of a reverse
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`voltage.
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`2. Obviousness
`Additionally, to the extent there is any question whether Utsugi teaches this
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`limitation, it would have been obvious to a POSA to use a constant voltage for the
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`line voltage VDD that is applied in Utsugi, as the Petition explained. Pet., 56–58.
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`Notably, Solas offers no argument and no evidence to the contrary. Use of a constant
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`voltage would be nothing more than the selection from a limited set of known
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`options, with predictable results. Id.; Ex. 1007, ¶¶ 171–172 (describing an AC
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`voltage, a constant DC voltage, and a pulsed DC voltage). And a POSA would be
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`motivated to select a constant voltage to avoid flicker or a perceivable change in
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`brightness. Pet., 57 (citing Ex. 1007, ¶ 172).
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`Solas does not address or respond to the obviousness of applying a constant
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`voltage to the second electrode. Rather, its only substantive arguments for the
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`“constant voltage” limitation of claim 8 are that it is allegedly not disclosed in Utsugi
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`as necessary for anticipation. See POR, 15–17. Thus, Solas has waived its
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`opportunity to dispute that the limitations of claim 8 would have been obvious to a
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`POSA.
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`D. Limitation 15[f]: “an insulation film formed over said substrate so
`as to cover said drive transistors, said address lines and said data
`lines, said insulation film having contact holes formed in
`correspondence with said drive transistors”
`Anticipation
`1.
`Solas’s arguments for this limitation are essentially the same as for limitation
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`1[c]. For limitation 1[c], Solas asserted that Utsugi’s SiO2 layer “does not necessarily
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`cover” the switching transistor QS because that transistor is not depicted in Figure 5.
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`For limitation 15[f], Solas similarly contends the SiO2 layer “does not necessarily
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`cover the scanning electrode lines” (address lines) because these lines are not
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`depicted in Figure 5. POR, 19 (emphasis added). Solas does not dispute that Utsugi
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`satisfies the other requirements of limitation 15[f].
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`Solas’s arguments for limitations 15[f] are unavailing for substantively the
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`same reasons as limitation 1[c], discussed above. Figure 5 is a cross section, which
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`was not meant to illustrate the location of the scan electrode lines, or the layers above
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`it. And Utsugi’s written disclosures show that the SiO2 insulation film is deposited
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`over the entire surface of the display and covers the scan electrode lines 3N (address
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`lines), as the Petition explained. Pet., 46–47.
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`Utsugi teaches growing the relevant SiO2 layer (after the scan electrode lines
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`3N have been formed, see Ex. 1003, 7:20–22), and describes patterning this layer
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`only where contact holes are located. Ex. 1003, 7:47–52 (“Then, a SiO2 layer is let
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`grow 200 nm, before an etching to open the second contact holes . . . .”). Therefore,
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`a POSA would understand the SiO2 layer is formed as a continuous layer on top of
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`these lines, and patterned only in the location of the contact holes. It covers the scan
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`electrode lines 3N (address lines), just as it covers the signal electrode lines 1M (data
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`lines), the current controlling transistor QI (drive transistor), the lower electrode of
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`the capacitor C, and the gate electrode GQI. See Pet., 47. Figure 5 of Utsugi reinforces
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`that the SiO2 is continuous apart from the contact holes, e.g., 56B:
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`
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`Solas does not dispute that the SiO2 layer is formed by a deposition/patterning
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`process after the formation of scan electrode lines 3N (address lines). Solas simply
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`repeats the same type of speculative assertions it offered for element 1[c] that
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`performing other process steps not disclosed or even suggested in Utsugi could result
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`in the SiO2 layer not covering the scan electrode lines. Specifically, Solas asserts
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`that the SiO2 layer “does not necessarily cover the scan electrode lines” because
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`either (i) a “mask” could be used to prevent the SiO2 layer from being deposited
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`above the scan electrode lines, or (ii) the SiO2 layer could “be removed” from this
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`location by etching. POR, 19. Utsugi, however, does not disclose such masking or
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`etching. Moreover, Solas does not articulate any reason why a POSA would
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`purportedly read Utsugi to employ such undisclosed and unnecessary additional
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`processes. Id. Mr. Flasck’s declaration is again of little to no probative value on this
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`issue, as it merely repeats near-verbatim the Response’s conclusory assertions.
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`Compare POR, 19 with Ex. 2001, ¶ 66. Mr. Flasck was unable to provide any basis
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`for Solas’s assertion as to masking, see Ex. 1017, 129:17–130:9, and neither Solas
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`nor Mr. Flasck cite any evidence why a POSA might read Utsugi as even
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`contemplating etching the SiO2 layer above the scan electrode lines, see POR, 19;
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`Ex. 2001, ¶ 66.
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`2. Obviousness
`Additionally, even if Utsugi had not disclosed that its SiO2 layer covers the
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`scan electrode lines, it would have been obvious to form the SiO2 layer to cover these
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`lines. See Pet., 58–59.
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`As explained above, Utsugi’s SiO2 insulation layer is deposited over the array
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`after scan electrode lines 3N (address lines) have been formed and after formation of
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`the signal electrode lines 1M (data lines) and transistors. See Ex. 1003, 7:20–52. Solas
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`does not dispute that scan electrode line 3N is contiguous with the lower electrode of
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`capacitor C and formed in the same metal layer as gate electrode GQI, and that, as
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`shown in Figure 5, both of these elements are covered by the SiO2 layer. See Pet., 47.
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`It would have been obvious (at a minimum) to leave the SiO2 insulation in place
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`above the scan electrode lines 3N as well. See Ex. 1007, ¶¶ 175–176.
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`Maintaining the SiO2 layer above the scan lines would be the most natural and
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`straightforward implementation of Utsugi’s disclosures, as it would entail not
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`undertaking an unnecessary and additional step of patterning or masking the SiO2
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`insulation to remove it from the area above scan lines 3N. Solas speculates that the
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`SiO2 layer might not be formed above the scan lines, theorizing that the SiO2 layer
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`could be selectively deposited or removed from this location by etching, or a
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`different insulating m