United States Patent to
`Fenwick et al.
`
`1 l)
`45
`
`4,001,692
`Jan. 4, 1977
`
`54) TIME DIVERSITY DATA TRANSMISSION
`APPARATUS
`75) Inventors: Robert B. Fenwick, Palo Alto;
`Clinton R. Gilliland, Menlo Park,
`both of Calif.
`73) Assignee: Barry Research Corporation,
`Sunnyvale, Calif.
`July 7, 1975
`(22 Filed:
`(21) Appl. No.: 593,690
`52) U.S. C. ............................... 325/38 R; 325/39;
`325/40; 325/42; 325/56; 325/60; 343/204
`(51) Int. C.’........................................... H04B 7106
`58 Field of Search ................ 325/56, 59, 60, 154,
`325/40, 38 R, 39, 473-476, 65, 42; 343/176,
`178, 200, 204; 179/15 R, 15 FD, 15 BA;
`340/172.5
`
`56)
`
`3, 195,048
`3,409,875
`3,422,357
`3,526,837
`
`References Cited
`UNITED STATES PATENTS
`7/1965 Adams ................................. 325/56
`1/1968 De Jager et al. .................... 325/59
`lf 1969 Browne ...............
`... 325/56 X
`9/1970 Zegers et al. .................... 325/59 X
`
`3,842,352
`
`10/1974 Cote .................................... 325/56
`
`Primary Examiner-Robert L. Richardson
`Assistant Examiner-Michael A. Masinick
`Attorney, Agent, or Firm-Flehr, Hohbach, Test,
`Albritton & Herbert
`
`ABSTRACT
`57
`An asynchronous, time diversity transmission appara
`tus including a data encoder at a transmitting location
`and an error-correcting data decoder at a receiving
`location for overcoming the effects of signal fading,
`impulsive noise and interference. The asynchronous
`data encoder encodes a single input data stream into
`three or more redundant, parallel data outputs having
`time diversity introduced by successive delays. The
`data outputs are frequency multiplexed and propagated
`over a transmission circuit. Received data is demulti
`plexed and input to the data decoder where it is pro
`cessed to remove the time diversity. Three or more
`outputs from the decoder are combined to form a sin
`gle, error-corrected data output.
`
`25 Claims, 5 Drawing Figures
`
`
`
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`U.S. Patent Jan. 4, 1977
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`Sheet 1 of 3
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`4,001,692
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`U.S. Patent
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`Jan. 4, 1977
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`Sheet 2 of 3
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`4,001,692
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`U.S. Patent Jan. 4, 1977
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`Sheet 3 of 3
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`4,001,692
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`4,001,692
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`APPARATUS
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`-
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`-
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`10
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`5
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`30
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`1.
`TIME DIVERSITY DATA TRANSMISSION
`
`2
`SUMMARY OF THE INVENTION
`The present invention is an asynchronous time diver
`sity method and apparatus which provides forward
`BACKGROUND OF THE INVENTION
`error correction in the transmission of data. The asyn
`chronous capability of the invention permits many
`The present invention relates to transmission appara
`different transmission data rates to be utilized without
`tus including encoders and decoders useful for forward
`requiring changes in operating frequency.
`error correction and more specifically to transmission
`In transmitter circuitry, a serial input data stream is
`circuits in which the effects of signal loss, noise, and
`converted to three or more transmitter data streams.
`interference, or any of them, are time variable. The
`The transmitter, data streams are each substantially
`present invention is particularly useful in high fre
`identical to the input data stream except that in order
`quency and troposcatter radio circuits.
`to obtain time diversity, the transmitter data streams
`Signal fading, impulsive noise and interference are
`are successively delayed, in an encoder, relative to the
`deleterious effects frequently encountered in many
`input data stream. The transmitter data streams are
`transmission circuits. Where these effects are present,
`multiplexed and transmitted to a receiver.
`the quality of transmission is deteriorated and an in
`In receiver circuitry, a received signal is demulti
`crease in the transmission error-rate occurs. Radio
`plexed asynchronously to form three or more receiver
`circuits employed to transmit teleprinter information
`data streams, one for each of the transmitter data
`are particularly susceptible to these deliterious effects.
`20
`streams. The receiver data streams are successively
`Radio teleprinter information is typically transmitted at
`delayed, in a decoder, to remove the time diversity.
`a rate of up to 75 bits per second (baud).
`The relative delays removed from the receiver data
`The quality of a transmission circuit is frequently
`streams by the receiver decoder correspond to the
`measured in terms of its character error, rate (CER).
`relative delays introduced into the transmitter data
`The character error rate is defined as the percentage of
`25
`streams by the transmitter encoder. The receiver data
`erroneous characters received relative to the total
`streams, after removal of time diversity, are algebra
`number of characters transmitted in a given time pe
`ically added to form a sum data stream. The sum data
`riod.
`stream is compared with a threshold to form an error
`Prior art techniques for improving the performance
`corrected output data stream.
`of data transmission circuits have utilized many differ
`In one preferred embodiment of the invention, the
`ent forms of redundancy in connection with forward
`transmitter encoder includes two or more delay circuits
`error correction. Diversity systems employing space
`for delaying the input data stream. The delay circuits
`diversity, polarization diversity, frequency diversity or
`are, for example, shift register stages which step the
`time diversity have all been known in one form oran
`input data stream under control of an encoder clock.
`35
`The input data stream is utilized as a first transmitter
`other.
`.
`. .
`.
`data stream. The output from the first shift register
`The term "time diversity' has usually been inter
`stage provides a delayed second transmitter data
`preted to mean synchronous transmission of data two
`stream. The second transmitter data stream in turn is
`or more times with a time delay between each transmis
`input to a second shift register stage and is delayed to
`sion. Each received data bit is compared with a corre
`40
`provide a third transmitter data stream. Up to N trans
`sponding delayed data bit. In such systems, synchro
`mitter data streams with successive delays are obtained
`nous operation is required in order to identify each bit.
`with N shift register stages.
`Synchronous operation has the undersireable require
`The frequency of the encoder clock is selected to be
`ment of being dependent upon the transmission data
`twenty or more times the data rate (baud rate) of the
`rate. A change in data rate requires a corresponding
`45
`input data stream. Lower encoder clock frequencies
`change in synchronous clocking in the transmitter and
`tend to introduce increasing numbers of errors. While
`receiver apparatus. If a difference is observed between
`an asynchronous encoder clock appears more desire
`bits as a result of a comparison of bits, an error is iden
`able in order to allow operation without change for
`tified. When an error is identified, one of the data bits,
`many different data rates, bit synchronous encoder
`SO
`for example the earlier transmitted data bit, is the one
`clocks can also be employed.
`selected for actual use. A time diversity system of this
`In one embodiment, each of the transmitter data
`type has been described by L. E. Zegers in an article
`streams is frequency multiplexed, is transmitted to the
`entitled "Error Control in Telephone Channels By
`receiver, and is demultiplexed. After demultiplexing,
`Means of Time Diversity' appearing in the Philips Re
`there is one receiver data stream for each transmitter
`55
`search Report, volumn 22, June, 1967.
`. .
`.
`.
`data stream.
`The term "time diversity' has also been applied to
`The receiver decoder includes a delay circuit for
`systems in which data bits are divided in time, with one
`each of the receiver data streams. The delay circuits
`half of each bit being transmitted on one frequency and
`include, for example, a plurality of shift register stages
`the other one half of each bit being transmitted on
`which are each stepped by a decoder clock. The num
`60
`another frequency.
`ber of stages in each.delay circuit varies and is selected
`The performance quality of known diversity systems
`to remove the time diversity from the receiver data
`is not entirely satisfactory particularly when the effects
`streams. The delay inserted in the transmitter data
`of signal loss, noise or interference have a duration of
`stream when added to the delay inserted in the corre
`up to several seconds. There is a need, therefore, for
`sponding receiver data stream is equal to a constant
`65.
`improved and economical apparatus useful in improv
`delay for all data streams. The constant delay is estab
`ing transmission and reducing character error rates in
`lished by making the total number of shift register
`transmission circuits.
`stages travelled by the combination of a transmitter
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`any change in the coding of data on line 14 and is not
`data stream and the corresponding receiver data
`required to identify individual bits in the data stream on
`stream equal to a constant.
`line 14. DTO is typically the input data stream and each
`In accordance with one feature, an integrating volt
`meter is provided for indicating the level of the output
`of the data streams DT1, ..., DT'N' is delayed after
`from the summing amplifier as an indication of the 5
`DTO by successive amounts. The transmitter diversity
`transmission character error rate. Signals having a level
`data streams DT0, ..., DT(N) are input to a conven
`tional multiplexer 5.
`near a threshold level tend to exhibit a high bit error
`Multiplexer 5 is any conventional multiplexer for
`rate while signals having a large deviation from the
`multiplexing up to N--1 of the diversity data streams
`threshold level tend to have a low bit error rate.
`over separate channels of a common data path 16.
`In accordance with another feature, individual data 10
`The multiplexed information on data path 16 is trans
`stream comparators are provided for comparing the
`mitted through a conventional transmitter 6 to a con
`error-corrected data output with the outputs from each
`ventional receiver 7 and appears in multiplexed form
`of the receiver delay circuits. In this manner, data
`on data path 17 as an input to a demultiplexer 8.
`streams which are in disagreement with the error-cor
`Demultiplexer 8 is any conventional device compati
`rected data output are identified.
`ble with multiplexer 5. The demultiplexer 8 demulti
`In accordance with another feature, a channel selec
`tion circuit is provided for adding and dropping data
`plexes the information on data path 17 to form the data
`receiver diversity data streams DR0, DR1,..., DR(N).
`streams. In one example, the number of data streams
`The diversity decoder 9 in accordance with the pre
`(channels) can vary between 3 and 7. The determina
`tion of the number of channels employed may be based 20
`sent invention removes the time diversity from the
`diversity data streams DR0, . . . , DR(N) and forms a
`upon the character error rate determined by the inte
`grating volt meter. A greater character error rate sug
`single error-corrected stream online 19. Decoder 9 can
`operate asynchronously with respect to the diversity
`gest the addition of more channels while a low charac
`data streams and without identifying individual bits.
`ter error rate suggest that channels may be eliminated.
`In accordance with the above summary of the inven- 25
`In FIG. 1, the data sink 10 is any conventional device
`tion, the present invention achieves the objective of
`for receiving the error-corrected data stream as binary
`providing an improved asynchronous time diversity
`digital data from line 19. Data sink 10 can be, for exam
`ple, another teletypewriter.
`method and apparatus which provides forward error
`The time diversity system of FIG. 1 has a variable
`correction in the transmission of data.
`redundancy capability in that the number of active
`Additional objects and features of the invention will 30
`appear from the following description in which the
`channels can be varied. Any number greater than two
`can be employed. Channels not employed in one time
`preferred embodiments of the invention have been set
`forth in detail and in conjunction with the drawings.
`diversity system, are available, of course, for transmit
`ting other data. The overall data transmission rate may
`BRIEF DESCRIPTION OF THE DRAWINGs
`be increased and decreased depending upon the num
`FIG. 1 depicts a block diagram representation of an
`ber of channels active in the time diversity system.
`asynchronous time diversity system including transmit
`DIVERSITY ENCODER-FIG. 2
`ter and receiver circuitry in accordance with the pre
`In FIG. 2, one preferred embodiment of the diversity
`sent invention.
`FIG. 2 depicts a block diagram representation of a 40
`encoder 4 of FIG. 1 is shown in detail. The serial input
`data encoder and a frequency multiplexer which form a
`data stream on line 14 appears as the first transmitter
`part of the transmitter circuitry within the system of
`diversity data stream DTO and connects to the delay
`stages 21. The delay stages 21-1, . . . , 21-6 provide
`F.G. 1.
`FIG. 3 depicts a schematic representation of a fre
`successive delays DL1, . . . DL6, respectively, of the
`input data stream DT0. The outputs from delays DL1,
`quency demultiplexer and a data decoder which form 45
`part of the receiver circuitry within the system of FIG.
`DL2, . . . , DL6 provide the transmitter diversity data
`stream signals DT1, DT2, . . . DT6, respectively. The
`1.
`signal DT1 is delayed behind the input signal DTO by
`FIG. 4 depicts an electrical schematic representation
`the amount of delay DL1. Similarly, the signal DT2 is
`of a portion of the FIG. 2 data decoder.
`FIG. 5 depicts wave forms representative of the oper- 50
`delayed behind the signal DT1 by the amount of delay
`DL2. Each of the other signals DT3 through DT6 is
`ation of the present invention.
`delayed in a similar manner.
`DETAILED DESCRIPTION
`The delay circuits 21 are any conventional delay
`devices for delaying binary signals. In a preferred em
`In FIG. 1, the transmitter circuitry includes the data
`source 3, the diversity encoder 4, the multiplexer 5, 55
`bodiment, each of the delays 21 is a 2048-bit shift
`register stage. The 2048-bit stages are selected because
`and the transmitter 6. The receiver circuitry includes
`the receiver 7, the demultiplexer 8, the diversity de
`of their ready commercial availability. Of course, shift
`register stages of any size can be employed. The shift
`coder 9, and the data sink 10.
`register stages 21 are shifted by an encoder clock (ENC
`In FIG. 1, the data source 3 provides on line 14 a
`serial stream of binary input data to the encoder 4. 60
`CLK) 20. For each clock pulse from clock 20, the
`logical 1 or 0 level of the respective input signal is
`Data source 3 is any conventional source of binary data
`loaded into the first bit position of shift register stage.
`such as a teletypewriter.
`The diversity encoder 4 of the present invention
`The contents of the other bit locations in each of the
`shift register stages are stepped also for each clock
`receives the input data stream on line 14 and forms
`pulse in a conventional shift register manner.
`three or more transmitter diversity data streams DT0, 65
`In a preferred embodiment, the encoder clock 20 has
`DT1,..., DT(N). The encoder 4 is capable of asyn
`a frequency of 2KHz. Therefore, the delay of each
`chronous operation with respect to the input data on
`delay circuit 21 is 1.024 seconds. Clock 20 is a conven
`line 14. Additionally, encoder 4 is not required to make
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`In FIG. 3, the diversity data stream DR0 through
`tional crystal controlled oscillator which provides an
`output which does not vary more than one part in 10.
`DR5 connect to the delay circuits 24-0 through 24-5,
`respectively. Since the DT0 signal was not delayed at
`The frequency of clock 20 is selected to be twenty
`all in FIG. 2, the corresponding signal DR0 receives the
`times greater than the baud rate of the data on input
`line 14. With a twenty-times greater clock frequency,
`maximum delay of six stages in delay circuit 24-0 of
`the signal on line 14 is sampled twenty times for each
`FIG. 3. The delayed signal D) is output from stage 24-0
`digital bit on line 14. Therefore, the sampling error
`on line 28-0. Delay circuit 24-0 includes a delay equal
`introduced into any data bit on line 14 will be compara
`to all six of the stages DL0 through DL6 in FIG. 2. In a
`preferred embodiment, delay circuit 24-0 includes six
`tively small, that is, not greater than two out of twenty.
`shift register stages of 2048 bits per stage.
`If less error is desired, then the clock frequency can be
`made more than twenty times greater than the input
`In FIG. 3, the delay circuit 24-1 includes a delay
`equivalent to the five stages DL2 through DL6 in FIG.
`data rate. The number of bits in each of the delay stages
`2. Since the DT1 signal received the one stage delay
`21-1 through 21-6 is determined in conjunction with
`DL1 in FIG. 2, the corresponding signal DR1 is further
`the frequency of clock 20 to provide the desired delay.
`delayed in FIG.3 for the five stages DL2 through DL6.
`In general it is desirable that the overall cumulative
`delay for stages 21-1 through 21-6 be twice as long as
`The output D on line 28-1 has received a full six stage
`the duration of any noise burst, signal fading, interfer
`delay. In a similar manner, the delay circuits 24-2,
`24-3, 24-4 and 24-5 have delays equal to the four stages
`ence or other error-causing effects associated with the
`DL3 through DL6, the three stages DL4 through DL6,
`transmission channel in the FIG. 1 apparatus. In FIG. 2,
`each of the stages 21 has an approximately one second
`the two stages DL5 through DL6, the one stage DL6,
`delay so that the overall cumulative delay is approxi
`respectively. The delays 24-2 through 24-5 when cou
`mately 7 seconds. Accordingly, the FIG. 2 embodiment
`pled with the delays in the encoder of FIG. 2 for the
`corresponding signals all total the maximum six stage
`is effective for error-causing effects which are less than
`delay. Similarly, the DR6 signal is not delayed in the
`approximately 3.5 seconds in duration.
`In FIG. 2, for asynchronous operation, the phase of
`FIG. 3 circuitry since the corresponding signal DT6 in
`25
`clock 20 need not have any relationship to data transi
`FIG. 2 receives the maximum delay DL1 through DL6
`tions on the data input line 14. Also, while delay stages
`in the FIG. 2 encoder.
`Because of the operation of the delay circuits 24 in
`21 have been selected as shift register stages, any other
`apparatus which accurately delays input binary signals
`FIG. 3, all of the signals on lines 28-0 through 28-6
`can be employed in the present invention. Delay stages
`have the time and diversity removed so that they are
`each an in phase representation of the data input signal
`may be employed which do not require a clock for
`timing. For example, the serial input data on line 14
`on line 14 to the encoder of FIG. 2. The in-phase sig
`can be written onto a circulating magnetic disc with a
`nals on lines 28 are delayed relative to the input signal
`on line 14 an amount equal to the six stage delay DL1
`write head where each of the output signals DT1
`through DL6 plus any delay resulting from transmis
`through DT6 is obtained from read heads spaced at
`successive distances (and hence delays) from the write
`SO
`In a preferred embodiment, the delay circuits 24-0
`head.
`through 24-5 are implemented with six, five, four,
`In FIG. 2, the multiplexer 5 is any standard multi
`plexer from a voice frequency telegraph group. For
`three, two, and one shift register stages with 2048 bits
`per stage. Each of those shift register stages is clocked
`example, the Western Electric model 43 Al is such a
`40
`multiplexer.
`by a decoder clock 23. The decoder clock 23 in FIG. 3
`The multiplexer 5 has seven frequency bands F0, F,
`is like the encoder clock 20 in FIG. 2 and has a 2K Hz
`output frequency Clock 23 is also crystal controlled so
`... F6. The frequency bands are utilized in a scattered
`that its output frequency varies approximately less than
`order with respect to the order of the transmitter diver
`one part in 10. Since clocking circuits having this
`sity data streams. In one embodiment, the data streams
`degree of accuracy are standard components in the
`DT0, DT1, DT2, DT3, DT4, DTS, and DT6 connect to
`data processing field, they are conveniently employed
`the frequency bands F2, F6, F0, F3, F5, F1, and F4,
`respectively. In one implementation, the frequency
`in a preferred embodiment. If the clocks 20 and 23
`bands each have a band width of 42.5Hz about center
`were less accurate, the invention would still work as
`frequencies. The center frequencies for the bands F0,
`intended. If the variations between the frequencies of
`clocks 20 and 23 became great enough, however, er
`F1,..., F6 are 765, 1105, 1445, 1785, 2125, 2465,
`and 2805Hz, respectively. Of course, these values are
`rors would be introduced as a function of the magni
`only one preferred embodiment as many other alterna
`tude of the variations.
`tives can be employed.
`The signals on lines 28 are input to channel gates 26.
`Channel gates 26 function to determine which ones of
`DIVERSITY DECODER - FIG.3
`the delayed signals D0, ..., D6 on lines 28 are actually
`In FIG. 3, one preferred embodiment of a diversity
`active in the operation of the FIG. 3 data decoder. The
`decoder 9 is shown receiving receiver diversity data
`gates 26 allow any combination of channels up to a
`streams from a demultiplexer 8. The demultiplexer 8 is
`total of seven channels to be active. The diversity sys
`a conventional device which demultiplexes the signals
`tem of the preferred embodiment requires three or
`on the data path 17 to form the receiver diversity data
`more channels. If all channels are active, then the gates
`streams. The diversity data streams DR0, DR1, . . . ,
`26 may be eliminated and lines 28 merely connect to
`DR6 are demultiplexed from the frequency bands F2,
`the corresponding lines 29.
`F6, F0, F3, F5, F1, and F4, respectively. Accordingly,
`The active data signals on the lines 29 connect to the
`the receiver diversity data streams DR0, DR1, ...,
`summing circuit 27. Circuit 27 operates to form the
`65.
`DR6 in FIG. 3 correspond to the transmitter diversity
`algebraic sum of the signals on lines 29 to form a sum
`data streams DT0, DT1,..., DT6, respectively, in FIG.
`signal on line 33. The signal on line 33 is compared
`2.
`with a threshold level in comparator 40. A threshold
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`ming transistors 43 is associated with a 10K base resis
`level is provided by threshold circuit 32. If the level of
`tor and a tie-up resistor connected to a positive voltage
`the sum signal on line 33 is more positive than the level
`equal to Vr. The base resistors connect each of the
`on line 41, the output from comparator 40 is a logical
`bases to a corresponding one of the inputs from selec
`0 and if the level on line 41 is more positive than the
`level on line 33 the output is a logical 1. The output
`tion gates 26.
`The summing transistors 43-0 are emitter-coupled
`from comparator 40 on line 19 has a serial data format
`having their emitters connected in common to a refer
`and has the benefit of the forward error correction of
`ence potential on line 39 from generator 31. Each of
`the present invention.
`In FIG. 3, the summing circuit 27 receives a summing
`the collectors for the transistors 43 connects through a
`voltage on line 39 from a voltage generator 31. The
`summing resistor R1 to the negative input of a conven
`voltage generator 31 provides a DC level which is pro
`tional amplifier 44. The value of R1 is typically 100K
`ohms. The positive input of amplifier 44 is connected
`portional to the reference voltage, Vr, divided by the
`to ground. A R1/2 feedback resistor connects from the
`number, n, of channels selected to be active by the
`output to the negative input of amplifier 44.
`channel gates 26. Both the channel gates 26 and the
`The sum signal (SS) on line 33 from amplifier 44 has
`voltage generator 31 are controlled by the seven con
`15
`a voltage equal to (n)Vr/(2n) where m is the number
`trol lines 36, one corresponding to each of the seven
`of logical 0's on the lines 29. The 0's on lines 29 repre
`data lines 28. The channel selector 30 can be any con
`sent the 1's (marks) for the active ones of the delayed
`ventional storage device such as seven on/off manual
`switches or a 7-bit register.
`channel data streams on lines 28.
`The sum signal output on line 33 is connected to the
`In FIG. 3, the signals on the data lines 28 are also
`negative input of a conventional comparator 40. The
`input to the individual channel comparator circuit 37.
`positive input to comparator 40 is derived from the
`in comparator circuit 37, each of the active data lines
`28 is compared with an error-corrected data output
`threshold circuit 32. Threshold circuit 32 establishes a
`threshold level on the positive input of comparator 40
`signal on line 19. The seven indicators 38-0 through
`equal to VrfA. Whenever the signal on line 33 is more
`38-6 function to indicate, for each of the active chan
`25
`positive than Vr/4, the output on line 19 is a logical 0
`nels, which channels have the same level as the error
`and otherwise is a logical 1.
`corrected data output on line 19.
`In FIG. 4, the integrating voltmeter 34 can be any
`ERROR-CORRECTING AND ERROR-INDICATING
`conventional device. In one embodiment, voltmeter 34
`CIRCUITRY - FIG. 4
`includes a full wave rectifier 48 which functions to full
`30
`In FIG. 4, the error correcting and indicating cir
`wave rectify the sum signal on line 33 to provide a
`rectified signal (FWR) on line 61 representative of the
`cuitry 58 of FIG. 4 is shown in further detail. The chan
`character error rate expected for the signal on line 19.
`nel selection gates 26 include the NAND gates 26-0
`The signal on line 61 is integrated by resistor R5 and
`through 26-6. Gates 26 each receive one of the seven
`capacitor 50. Thereafter, the voltage follower 51 pro
`control inputs from the 7-bit channel selection bus 36.
`vides the integrated output to the character error rate
`Bus 36 is derived from the channel selection unit 30.
`Unit 30 is any conventional switching device which
`indicator 35. Indicator 35 can be any conventional
`provides control outputs. For example, unit 30 can
`indicator, such as a moving vane meter, for indicating
`the level of the signal output from follower 51.
`include seven manual switches or a 7-bit register.
`Those gates 26 which receive a logical 1 from bus 36
`In FIG. 4, the individual channel comparator unit 37
`40
`receives delayed channel signals on lines 28-0 through
`are enabled. The enabled ones of the gates 26 invert
`and pass the logical 1 or 0 signal on the respective input
`28-6 and compares each of them with the error-cor
`line 28 to the corresponding output line 29. When any
`rected data output on line 19. The comparison is per
`formed by the EXCLUSIVE-OR gates 55-0 through
`one of the gates 26 receives a logical 0 input from bus
`36, that gate is forced to have a logical 1 on its output
`56-0. Whenever they are the same, the respective gates
`45
`55 provide a 0 output and whenever they are different,
`line 29 irrespective of the 1 or 0 condition of its input
`the gates 55 provide a 1 output. The comparison out
`line 28.
`puts from each of the gates 55-0 through 55-6 is stored
`In FIG. 4, the variable reference generator 31 pro
`in one of the conventional D-type flip-flops 56-0
`vides an output signal on line 39 which is determined
`through 56-6, respectively. The flip-flops 56 are peri
`by the number, n, of active channels. The number of
`50
`odically clocked through the OR gate 54 every one
`active channels is determined by the channel selection
`second, by a one second clock 52, and by delay circuit
`unit 30. Unit 30 also controls the open or closed condi
`53, seven milliseconds after both positive-going and
`tion of the switches 45. Switches 45 are, for example,
`negative-going transitions of the data on line 19. Each
`conventional relays each controlled open or closed by
`0 stored in the flip-flops 56 designates that the data on
`one of the lines from bus 36. The switches 45 function
`55
`the corresponding channels 28 is the same as the error
`to connect the resistors R2 in the feedback loop be
`tween the negative input and the output of conven
`corrected data on line 19. Whenever a 0 to 1 transition
`occurs on the O output of the flip-flops 56, it indicates
`tional amplifier 46. For each line in the bus 36 ener
`a lack of comparison between the respective channel
`gized with a 1, the corresponding switch 45 is closed.
`and the error-corrected data output. That positive
`Therefore, the number of resistors R2 connected in
`parallel in the feedback loop of amplifier 46 is equal to
`going transition is connected to the clock input of the
`respective single-shots 57. Single-shots 57 also receive
`the number, n, of active channels. Under these condi
`tions the output level on line 39 is a positive voltage
`on their D inputs an enable from the channel selection
`unit 30. Only those single shots having 1's on their D
`-Vr/n where Vr is negative.
`inputs are clocked to store a 0 on their Q* outputs. The
`The outputs 29 from the selection gates 26 connect
`as inputs to the summing circuit 27. The summing cir
`inactive channels have 0's connected to the D inputs of
`single-shots 57 and therefore those single shots always
`cuit 27 includes the summing transistors 43-0 through
`retain a 1 on their O* outputs. The Q* outputs from the
`43-6 and the summing amplifier 44. Each of the sum
`
`60
`
`65
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`MM EX1027, Page 8
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`4,001,692
`9
`single shots 57 are connected to the respective channel
`indicators 38. The channel indicators are any conven
`tional indicators and are, for example, light-emitting
`diodes. The light-emitting diodes are operative, for
`example, to indicate with a light output any 0 on the O*
`output of the connected single shot. For those O* out
`puts having a 1, the light emitting diodes are extin
`guished.
`When no data is being transmitted, no transitions will
`10
`occur on line 19. Therefore, the 1 sec clock 52 is con
`nected through OR gate 54 to the clock strobe inputs of
`single shots 57-0 through 57-6 by NAND gates 65-0
`through 65-6 to cause the respective indicators 38-0
`through 38-6 to flash if any one of the flip-flops 56-0
`through 56-6 is holding a 1.
`-
`.
`SUMMARY OF OPERATION
`The operation of the FIG. 1 apparatus will be de
`scribed in connection with the sample wave forms of
`20
`FIG. 5 and TABLE I below. For purposes of explana
`tion, the serial data in (SDI) signal on line 14 has been
`assumed to be 101101000 . . . 011. The three dots
`represent all O's for a duration of 4 or more seconds.
`With the SDI signal as indicated, each of the diversity
`25
`waveforms DTO through DT6 generated by the FIG. 2
`circuitry in the manner previously described. Specifi
`cally, The SDI signal is input to the first delay stage
`21-1. Since stages 21 are clocked at approximately 20
`times the bit rate of the SDI data, each SDI bit actually
`30
`occupies 20 shift register bits in the stages 21. Of
`course, each SDI bit is twenty times longer than each
`shift register bit. For example, a logical 1 is represented
`by 20 shift register logical 1's and an SDI logical 0 is
`represented by 20 shift register 0's in the delay stages.
`35
`In FIG. 2, the seven data streams DTO through DT6
`have the same 1 and 0 bits as the SDI data stream
`except that they are successively delayed by one sec
`ond increments and are represented by 20 shift register
`40
`bits for each SD bit.
`Diversity data streams DTO through DT6 are fre
`quency multiplexed and transmitted to the receiver
`circuitry and then demultiplexed into the rec