Apple Exhibit 1132
`Apple Inc. v. Rembrandt Wireless
`IPR2020-00034
`Page 00001
`
`

`

`TAKLA AND HAQUE: SINGLE—CHIP 300 BAUD FSK MODEM
`
`847
`
`TDO—-——————>
`
`‘
`
`mnnuumn
`
`
`
`
`PROGRAMMABLE
`
`
`
`TRANSMIT FILTER
`
`
`LOWPASS
`Fl 7
`
`
`BANUI’ASS
`FILTER
`
`CONTINUOUS
`smoorums
`FILTER
`
`
`
`Tc
`
`. + 5
`- — 5
`4mm
`- mun
`
`nm
`8L
`
`AnI:
`T,
`fit
`
`,
`
`TIMING
`CONTROL
`
`AND
`NANDSNAKE
`LOGIC
`
`
`
`-
`
`3.53"",
`
`OSCILLATOR
`
`“SCI
`
`use,
`
`ENERGY
`DETECT
`
`
`CIRCUIT
`
`
`
`me
`
`BASE BAND
`RECOVERY
`FILTER
`
`FSK]
`PULSE WIDTH
`CONVERTER
`DEMODULATOR
`
`LIMITER
`
`BANDPASS
`FILTER
`
`LOWPASS
`FILTER
`
`CONTINUOUS
`LOWPASS
`FILTER
`
`m;
`
`mew: FILTER
`
`Fig. 1.
`
`300 baud FSK modem block diagram.
`
`II.
`
`SYSTEM ARCHITECTURE
`
`TABLE I
`
`The block diagram of the FSK modem is shown in Fig.
`1. The input to the modulator is the TD (transmit data)
`signal, which is the digital datato be modulated. This input
`would typically be provided by the RS—232 interface, or a
`UART. The modulator generates a square wave whose
`frequency is shifted in response to the transmit data input.
`The transmit filter outputs a frequency shift keying
`signal at the TC (transmit carrier) output. The frequency of
`the FSK signal corresponds to the fundamental frequency
`of the square wave at the input of the filter.
`On the receive side, the receive filter, whose input is the
`receive carrier, rejects the adjacent channel energy and
`improves the signal—to-noise ratio of the incoming carrier.
`The output of the receive filter is fed into the demodula-
`tor, where the digital data are retrieved from the filtered
`FSK signal.
`The next major block is the energy detect circuit. It
`detects energy levels at which reception and demodulation
`of data are considered reliable.
`
`The last block is the timing control and handshake logic,
`which, besides controlling all the other blocks, also imple—
`ments the RS232 interface protocol and controls the Bell
`103 and CCITT V.21 operations.
`
`III. MODULATOR
`
`The modulator generates a square wave whose frequency
`is shifted in a phase—continuous fashion. The generated
`frequency is a function of four signals: TD (transmit data),
`mode (answer/originate), SL (103/V21 SELECT), and V25
`(2100 Hz answer tone). As shown in Table I, the modulator
`is capable of generating one of nine frequencies: four of
`
`MODULATOR FREQUENCY As A FUNCTION OF SL (V21/BELL 103),
`A/0 (ANSWER/ORIGINATE). TD (TRANSMIT DATA), AND V25
`ANSWER TONE
`
`103 ANSWER
`
`I
`
`-IIEE-_” Fneoueucvimn
`
`
`0
`0
`0
`0
`1070
`103 ORIGINATE
`o
`0
`I
`1
`I
`0
`I
`1270
`
`0
`I
`l
`I
`0
`I
`0
`I
`2025
`0
`l
`l
`0
`2225
`
`
` 1 o 1 0
`
`
`
`1
`O
`0
`0
`v21 ORIGINATE
`
`1
`1
`1
`0
`1
`‘
`0
`0
`
`
`
`v21 ANSWER
`
`those nine are used for 103 operation, two for high band,
`and two for low band. One of these two frequencies
`represents a mark and the other a space. Two bands are
`used to enable simultaneous transmission and reception of
`data on the same channel, hence, the duplex operation. The
`other four frequencies are allocated for V.21 operation, and-
`the ninth frequency is used for V.25 answer tone.
`The modulator, as shown in the left-hand side of Fig. 2,
`consists of a PLA (programmable logic array) driving a
`programmable polynomial counter, followed by a divide by
`32. The polynomial counter generates 32 times the desired
`frequency. on each edge of this signal the PLA is updated,
`thus determining the frequency of next pulse. This ensures
`p’hase coherency of the generated signal. Since the output
`of the programmable polynomial counter is divided by 32,
`the maximum delay between TD and corresponding
`frequency shift at TC is 30 us. The divide by 32 is also
`used as an auxiliary counter to control the divide of the
`programmable counter. This is used to maintain a devia~
`tion of all generated frequencies within 0.1 percent.
`
`IPR2020-00034 Page 00002
`
`IPR2020-00034 Page 00002
`
`

`

`848
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30-19, No. 6, DECEMBER 1984
`
`ENABLE
`
`mum
`cournm
`Lomc
`
`m
`
`:3:
`
`
`nus/onus.
`"WV“
`
`103/v21
`PROGRAMMABLE
`FREQUENCY
`
`«summon
`Q
`
`iswz<
`
`
`
`3
`am onnsn
`PROGRAMMABLE
`2nd onnsn
`
`
`
`
`
`
`
`y PROGRAMMABLE
`DIVIDE BY
`ELLIPTIC
`connuunus
`4th onuia
`u
`mvan
`32
`Low PASS
`smoommc
`ELLIPTIC
`
`
`
`
`
`
`FILTEII
`BAND PASS
`c
`FILTER
`
`Fig. 2. Block diagram of the modulator.
`
`Tc
`
`20
`
`730
`
`740
`
`~50
`
`I
`
`‘4 c:
`
`780
`
`~90
`
`, 100
`
`0
`
`—20
`
`730
`
`~00
`
`I
`
`u o
`
`700
`
`~00
`
`, mo
`
`0
`
`GAININdBm
`
`GAININdBm
`
`1000
`
`2000
`
`3000
`
`4000
`
`5000
`
`FBEOUENCY (Hz)
`(a)
`
`man
`
`2000
`
`3006
`
`woo
`
`soon
`
`FREQUENCY (Hz)
`(b)
`Fig. 3. Measured transfer function of the transmit filter.
`
`IPR2020-00034 Page 00003
`
`IPR2020-00034 Page 00003
`
`

`

`TAKLA AND HAQUE: SINGLE-CHIP 300 BAUD FSK MODEM
`
`849
`
`103IV21
`ANSJORIO.
`ANAL I G LOOPBACK
`
`ADC
`LINES
`FROM
`ENERGV
`DETEOT
`CIRCUIT
`
`DECODER
`
`
`
`
`
`
`TO
`2nd ORDER
`OIII ORDER
`
`2nd ORDER
`
`DEMODULATOR
`CONTINUOUS
`2nd onnsn
`BAND PASS
`
`CONTINUOUS
`
`
`
`SMOOTHING
`ANTIALIAS
`PROGRAMMABLE
`
`
`LOW PASS
`
`
`NERGY
`LOW PASS
`FILTER
`FILTER
`_ FILTER
`
`
`
`OETECT
`FILTER
`
`
`
`&E
`
`FREOUENCY
`
`GENERATOR
`59.7IIN1155.9I(HZ
` 238.6”!!!
`
`223.7KH1
`
`
`Fig. 4. Receive filter block diagram.
`
`
`
`IV.
`
`TRANSMIT FILTER
`
`The function of the transmit filter is to produce an FSK
`signal
`from the phase-continuous
`frequency-shifted
`square-wave input.
`The structure of the ninth-order filter is shown in the
`
`right-hand side of Fig. 2, while its measured frequency
`response is shown in Fig. 3. The filter consists of three
`major sections. The first is a third-order switched capacitor
`elliptic low-pass filter, sampled at 111.9—223.7 kHz, de-
`pending on the mode of operation. The cutoff frequency of
`this
`filter
`is programmed by changing the sampling
`frequency.
`.
`The second section is a fourth—order elliptic bandpass
`filter which is programmed to operate in either the high or
`low band by changing both the capacitor ratios and the
`sampling frequency. The third section of the filter is a
`second-order Sallen and Key continuous smoothing filter.
`It attenuates the sampling frequency of
`the preceding
`section by more than 31 dB and produces a smooth FSK
`signal at its output.
`‘
`'
`The prime objective of the transmit filter is to pass the
`square wave fundamental component, while attenuating its
`harmonics. These harmonics could be located in the receive
`band. Unless attenuated by the transmit filter, they would
`be coupled back through the hybrid, unattenuated by the
`receive filter, thus causing degradation of bit error rate.
`The transmit filter was designed to have a zero at the
`third harmonic of the square wave, to alleviate the above
`problem.
`The second objective of the transmit filter is to attenuate
`the out-of-band energy. This is necessary since the modula—
`tion process produces energy over a broad spectrum and
`not just at the mark/space frequencies. The fundamental
`component is attenuated by 24 dB to produce a signal at
`— 9 dBm at the TC (transmit carrier) output.
`
`implemented using biquadratic
`filters were
`The
`switched—capacitor second—order sections allowing imple-
`mentation of both poles and zeros [2]. The filters were
`designed using bilinear transformation [3] and the results
`were optimized for acceptable group delay and frequency
`attenuation performance.
`
`V. RECEIVE FILTER
`
`The block diagram of the receive filter is shown in Fig. 4.
`The receive carrier is first fed into a second-order Sallen
`
`and Key continuous low-pass filter, which is followed by a
`second-order antialiasing filter clocked at 4 times the
`frequency of the main filter to follow. This antialiasing
`filter attenuates the incoming signal by 41 dB at
`the
`sampling frequency of the following section. This mini-
`mizes the aliasing effects and allows the main filter to be
`clocked at a lower frequency with resulting smaller capaci-
`tor ratios [2]. The antialiasing filter has programmable gain
`that can vary between 5 and 17 dB. The gain of the filter is
`changed under control of the energy detect circuit thus
`implementing the automatic gain control function.
`The next section is an eighth-order bandpass program-
`mable filter. It can be programmed to operate in one of
`four configurations depending on the band (high or low)
`and the specifications (Bell 103 or CCITT V21). Changing
`the capacitor ratios and sampling frequencies is used to
`reconfigure this section for the appropriate transfer func-
`tion. Both the transmit and receive filter can also be
`
`configured to work in the same band of frequency allowing
`true analog loopback, which facilitates testing.
`The last section is a second-order Sallen and Key con-
`tinuous low-pass filter. It attenuates the sampling frequency
`of the preceeding section by 20 dB and produces a smooth,
`filtered FSK output, which is fed to the demodulator. This
`action reduces the jitter of the demodulated signal.
`
`IPR2020-00034 Page 00004
`
`IPR2020-00034 Page 00004
`
`

`

`850
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30-19, No. 6, DECEMBER 1984
`
`30
`
`K 3
`
`4000
`
`5000
`
`000
`
`GAININdBm
`
`0
`
`1000
`
`(m/
`l
`
`/
`
`2000
`
`Fneoueucv(un
`a)
`
`30
`
`20
`
`10
`
`0
`I d =
`
`l
`
`a»c:
`
`— 40
`
`7 50
`
`7 50
`
`7 70
`
`GAININdBm
`
`a
`
`1mm
`
`zoos,
`
`3000
`
`4000
`
`5000
`
`FnenUEch(Hn
`0))
`Measured transfer function of the receive filter. (a) Bell 103.
`(b) CCITT V21 specifications.
`
`Fig. 5.
`
`The measured frequency response of the receive filter is
`shown in Fig. 5. The receive filter rejects out-of—band noise
`so that
`the filtered signal can be demodulated with a
`resulting; low bit error rate.
`The filter was designed to reject the adjacent channel
`energy, which is attenuated by 60 dB. This is essential since
`that channel
`is used for carrier transmission, which is
`coupled back through the hybrid and into the receive
`section. Unless attenuated by the receive filter, this compo-
`nent would corrupt the demodulated data and result in
`excessive bit-error rate. The filter was also designed to
`minimize group delay distortion between the mark and
`space frequencies. The bandwidth of the filter is 500 Hz
`
`and is centered around the center frequency of the received
`carrier.
`
`The dynamic range of the receive signal is 50 dB due to
`the automatic gain control circuit employed.
`
`VI. DEMODULATOR
`
`The demodulator is the most critical part of the modem.
`Its block diagram, the corresponding waveforms, and the
`measured frequency response of the baseband recovery
`filter are shown in Fig. 6.
`The input
`to the demodulator is the filtered receive
`carrier (waveform A). The filtered signal
`is amplitude
`
`IPR2020-00034 Page 00005
`
`IPR2020-00034 Page 00005
`
`

`

`~ TAKLA AND HAQUE: SINGLE-CHIP 300 BAUD FSK MODEM
`
`851
`
`v _
`
`(E)
`V
`
`*
`"0
`
`sucrn
`
`
`
`BASE
`
`
`BAND
`RECOVERY
`
`
`FILTER
`
`PROGRAMMABLE
`rsx/
`PULSE wmm
`comma
`
`
`
`FILTEnEn
`nEcEwE
`CARRIER
`
`sum
`T0 ENERGY
`unset
`
`10
`
`U
`
`7 10
`
`E —20
`
`e E
`
`2 L
`
`5 740
`
`, — an
`
`(a)
`
`,
`
`DEMODULATOR
`
`
`
`B
`
`A
`
`{0 i
`
`—-+H‘-——
`AM
`
`|<-———
`———>‘
`Am)
`
`\_\
`
`— so
`- m
`
`0
`
`500
`
`1000
`
`‘500
`
`»——i
`2000
`
`FREQUENCY (Hz)
`
`0))
`
`Fig. 6. Demodulator. (a) Block diagram. (b) Corresponding waveforms
`and measured transfer function of baseband recovery filter.
`
`limited, generating a digital waveform B, which is fed into
`a programmable FSK/pulsewidth converter. The function
`of the converter is to generate 2 sequential pulses at 4 times
`the center frequency of the received signal. On each edge of
`the amplitude—limited signal the converter is reset.
`In this fashion the time interval, as shown in waveform
`C, is a function of the received signal frequency and can be
`used as a measure of it. To recover the baseband data, the
`
`converted signal is fed into a low-pass filter that rejects the
`X4 carrier frequency component while passing the base-
`band signal. The baseband recovery filter consists of a
`Bessel low-pass filter driven by a numerical generator. The
`output of this filter is followed by a smoothing filter. The
`output of the filter is the eye pattern and is available at
`the EP pin of the device. It is important to keep the high
`and low levels of the digital wave C (Fig. 6) of equal
`magnitude and opposite polarity since any asymmetry gives
`rise to voltage offset. The input to the baseband recovery
`filter uses a unique sampling scheme where switched-capa-
`citor techniques are used to make both the low and high
`levels referenced to one power supply with one of the
`polarities being inverted.
`
`The output of the baseband recovery filter is then fed
`into a slicer that recovers the digital signal. These are the
`received digital data which are made available at the RD
`pin under RSZ32C control. The block diagram of the
`programmable FSK/pulsewidth converter
`is shown in
`Fig. 7.
`
`VII.
`
`ENERGY DETECT CIRCUIT
`
`The energy detect circuit is used to detect three different
`energy levels. Detection of one of these levels is used to
`control the carrier detect output. Detection of this level,
`together with the other two,
`is used for automatic gain
`control of the receive filter.
`
`The energy detect circuit, as shown in Fig. 8, consists of
`three major sections: the rectifier, the integrator, and the
`comparator and latches. The rectifier stage samples the
`filtered receive carrier and either passes it
`through or
`inverts it, depending on the signal’s polarity. The integrator
`integrates the rectified signal for 1.67 ms after which it is
`reset. At the end of each integration period, the output of
`
`IPR2020-00034 Page 00006
`
`IPR2020-00034 Page 00006
`
`

`

`852
`
`IEEE JOURNAL or SOLID-STATE CIRCUITS. VOL. sc-19, NO. 6, DECEMBER 1984 .
`
`
`EDGE DETECTOR
`SIGN
`IN
`OUT
`
`(OUTPUT OF
`
`RECEIVE FILTER)
`
`
`
`
`
`COMBINATIONAL LOGIC
`
`PROGRAMMABLE FREQUENCY
`
`DIVIDER
`
`3.58 MHZ
`
`OUT
`(TO BASE BAND
`RECOVERY FILTER)
`
`Fig. 7. Block diagram of programmable FSK/pulsewidth converter.
`
`ENERGY DETECT CIRCUIT AND AGC
`
`CARRIER
`
`FILTERED
`RECEIVE
`
`RECTIFIER
`CONTROL
`|<—— wmI GAIN
`
`|4————— INTEGRATOR ——>|
`
`INPUT ENERGY
`IN dBm
`
` |<-———-— coMPAIIAmR ———>|
`
`Fig. 8. Block diagram of energy detect circuit.
`
`the integrator is compared with an internally generated
`reference voltage and the result is saved in one of the two
`latches. Time division multiplexing is used to detect differ-
`ent energy levels. During the first time frame the energy
`detect circuit is configured to detect energy levels corre-
`sponding to — 48 or — 43 dBm at the input of receive filter,
`depending on the state of the carrier detect output. The
`result of the comparison is saved in the lower latch and is
`used by the timing control section to generate the carrier
`detect output. It is worth noting that one energy level at
`the output of the receive filter corresponds to either —48
`or ~43 dBm at the input of the filter, depending on the
`filter’s gain at that time.
`During the second time frame, the gain of the rectifier
`and integrator is reduced to detect higher energy levels and
`the result
`is stored in the upper latch in Fig. 8. The
`
`contents of these latches are used to control capacitor
`ratios in the receive antialiasing filter, which enables imple-
`mentation of an AGC function as well as hysteresis control
`of the energy detect circuit (5 dB in this case).
`Offset voltage and correlated noise is reduced in the
`energy detect circuit by adding an additional signal in the
`integrator. This signal is the offset and correlated noise at
`the rectifier output (with no signal
`input) with proper
`weighting [4].
`
`VIII. TIMING CONTROL AND HANDSHAKE LOGIC
`
`This section configures the chip into the appropriate
`operating mode and implements the handshake protocol.
`A protocol, in this context, is an agreed upon sequence
`of events used to establish a data call. A typical example is
`
`IPR2020-00034 Page 00007
`
`IPR2020-00034 Page 00007
`
`

`

`TAKLA AND HAQUE: SINGLE-CHIP 300 BAUD FSK MODEM
`
`853
`
`TD
`Tc
`TERMINAL I MODEM
`fit
`RC
`
`
`
`COMPUTER
`
`ORIGINATING DEVICE
`
`DTR (ONE)
`
`ANSWERING DEVICE
`
`“Ts (ONE)_
`
`TC (OHIGJ
`_
`CTS KING.)
`
`DTR (ANS)
`
`‘
`
`F—ZAOMS-Vl
`
`1270 Hz
`
`fi (ANS.)
`
`in (ms) —2225 Hz
`
`230m:
`
`. 1c mus.)
`
`fi (Ans)
`
`We was.)
`
`120ms
`
`Fig. 9. Bell 103 protocol as implemented by chip.
`
`when the originating device is a terminal while the answer-
`ing device is connected to a computer. This is shown in
`Fig. 9.
`,
`The originating device starts by setting the. DTR (data
`terminal ready) high to enable its modern. It then proceeds
`by pulsing RTS (ready to send). This in effect pulse dials
`the number out. Once the connection is made and ringing
`is detected at the remote device, RIB (ring indicator bar) is
`pulsed. This takes the remote device off hook and puts it in
`the answer mode. The answering device responds by wait-
`ing for 2.1 s, the billing delay, and then starts sending the
`mark frequency, which is 2225 Hz, for the Bell 103 specifi-
`cations.
`
`Upon receiving the answer tone, the originating device
`indicates carrier detection by turning the carrier detect
`output on, waits for 240 ms, and then starts sending 1270
`Hz mark frequency for 640 ms. At the end of the this
`period, clear to send turns on indicating to the terminal
`that it is clear to send data.
`
`The answering device detects the carrier in 120 ms and
`indicates that to the data terminal equipment by turning
`the carrier detect output on. It also indicates to the DTE
`that it can start sending data by turning CTS on.
`On the right-hand side of Fig. 9,
`the loss of carrier
`termination is demonstrated. If one of the two modems
`does not receive the carrier at a detectable level for more
`
`than 10 ms, it will respond by turning the carrier detect
`and clear to send outputs off. If this condition lasts for
`more than 230 ms, the modem will respond by disabling
`the transmit section and going on hook, thus terminating
`the call.
`
`
`
`,‘
`
`_
`
`\»
`
`,
`
`,
`
`»
`
`"mm
`
`Fig. 10. Microphotograph of single-chip 300 baud modem.
`
`The chip also incorporates a 14 s abort timer. This is
`necessary for automatic operation; When a call is auto~
`matically originated, and the remote device is busy, then
`the originating device waitsfor 14 s and hangs up. On the
`other hand, if a modem is called by mistake it will hang up
`in 14 s, unless the appropriate carrier is received.
`The protocol described above implements the Bell 103
`specification. The chip also implements the CCITT V.21
`specification which is conceptually similar, although differ- .
`ent in implementation.
`
`IPR2020-00034 Page 00008
`
`IPR2020-00034 Page 00008
`
`

`

`854
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC—19, No. 6, DECEMBER 1984
`
`IX.
`
`EXPERIMENTAL RESULTS
`
`REFERENCES
`
`The photomicrograph of the chip is shown in Fig. 10. It
`measures 216x260 mils2. It uses a :5 V power supply.
`Typical power dissipation is 110 mW. The modulator
`frequency deviation is i0.095 percent. The transmit car-
`rier harmonic attenuation is 60 dB. The receive carrier
`
`range is 0 to — 50 dBm. Typical bit jitter measured at 300
`baud and at an input of — 30 dBm is 100 ,us. Bit-error rate
`at 5 dB SNR is 3X10‘5. The bit bias is measured at an
`
`input of — 30 dBm is 3 percent.
`
`X. CONCLUSION
`
`A single-chip frequency shift keying modem has been
`successfully integrated in a 5 am CMOS technology. This
`modem represents a higher level of system integration
`where modulation, demodulation, filtering, energy detec-
`tion, as well as RS-232 control functions, are performed on
`the same chip for boththe Bell 103 and V.21 standards.
`The devices meet all required specifications.
`
`ACKNOWLEDGMENT
`
`The authors would like to acknowledge the help of S. C.
`Fan and B. Ghaderi for designing the eighth-order receive
`filter. Also, very helpful suggestions from R. Gregorian
`and V. Godbole are gratefully acknowledged.
`
`[1 A. Takla and Y. Haque, “A 300 baud frequency shift keying modem,”
`in ISSCC Dig. Tech. Papers, 1984, pp. 188—189.
`[2] R. Gregorian, K. W. Martin, and G. C. Temes, “Switched—capacitor
`circuit design,” Proc. IEEE, vol. 71, Aug. 1983.
`[3] K. Martin and A. S. Sedra, “Stray insensitive switched—capacitor
`filters based on bilinear z transform,” Electron Lett., vol. 19, pp. 365,
`June 1979.
`Y. A. Haque, “Design technique for dynamic range improvement on
`CMOS circuitry,” in Proc. Cuslom Integrated Circuits C0nf., May
`1983, pp. 376.
`
`[4]
`
`
`
`Ashraf K. Takla (M’81) was born in Cairo, Egypt,
`in 1956. He received the B.S.E.E. and M.S.E.E.
`degrees from San Diego State University, San
`Diego, CA, in 1979 and 1981, respectively.
`In 1980 he joined the Micro Component
`Organization, Burroughs Corporation, San Di-
`ego, CA, where he designed computer communi-
`cation integrated circuits. Since 1982, he has been
`with the Communication Group, American Mi-
`crosystems, Inc, Santa Clara, CA, where he has
`been involved in the definition and design of
`data communications IC’s.
`
`
`
`Yusuf A. Haque received the PhD degree in
`electronics from Carleton University, Ottawa,
`Ont, Canada, in 1977, and the MBA. degree
`from the University of Santa Clara, Santa Clara,
`CA, in 1982.
`While in Ottawa (197371977), he designed
`several integrated circuits at Bell Northern Re—
`search. He joined American Microsystems, Inc,
`Santa Clara, CA,
`in 1978 and has since been
`involved in the design and development of tele-
`communications circuits. He is currently Manager
`for Communications Products. He has received several patents in the area
`Of MOS integrated circuits.
`
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