a2) United States Patent
`US 7,940,809 B2
`(10) Patent No.:
`May 10, 2011
`(45) Date of Patent:
`Lee
`
`US007940809B2
`
`
`2002/0181608 Al * 12/2002-Kim et:al-isiesssissnaanees 375/295
`DIGITAL VIDEO INTERFACE WITH
`(54)
`2004/0001447 Al*
`1/2004 Schater ......
`.. 370/280
`BI-DIRECTIONAL HALF-DUPLEX CLOCK
`
`2004/0264482 Al* 12/2004 Kang etal. .
`ss
`CHANNEL USED AS AUXILIARY DATA
`2008/0112371 AL*
`5/2008 Joshi et al. occ 370/337
`CHANNEL
`OTHER PUBLICATIONS
`
`(75)
`
`(73)
`
`Inventor: Bong-Joon Lee, Seoul (KR)
`
`Assignee: Synerchip Co. Ltd., Hsinchu (TW)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C, 154(b) by405 days.
`
`“Digital Visual Interface, DVI: Revision 1.0," Apr. 2, 1999, Digital
`Display Working Group,pp. 1-76.
`“High-Definition Multimedia Interface: Specification Version 1|.2a,”
`Dec. 14, 2005, pp. 1-193, HDMI Licensing, LLC.
`“High-Definition Multimedia Interface: Specification Version |.3a.”
`Nov. 10, 2006, pp. 1-276, HDMILicensing, LLC.
`“Unified Display Interface (UDI) Specification: Revision |.0a Final,”
`Jul. 12, 2006, pp. 1-185.
`
`(21)
`
`Appl. No.: 11/760,164
`
`* cited by examiner
`
`(22)
`
`Filed:
`
`Jun. 8, 2007
`
`Primary Examiner — Chi H Pham
`Assistant Examiner — Fan Ng
`Prior Publication Data
`(65)
`(74) Attorney, Agent, or Firm—Elizabeth Kim
`US 2008/0247341 Al
`Oct. 9, 2008
`
`(60)
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`Related U.S. Application Data
`
`Provisional application No. 60/910,759,filed on Apr.
`9, 2007.
`
`Int. Cl.
`
`(2006.01)
`HO4J 3/12
`US jsntievdncnncnnnnencnd SSS
`Field of Classification Search.
`........................ None
`
`See application file for complete search history.
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`6,507,592 BL*
`7,295,578 BL*
`2001/0024430 Al*
`
`ve 370/503
`.
`1/2003 Hurvigetal.
`
`vee 370/503
`11/2007 Lyle etal.
`.....
`9/2001 Sekine etal.
`............. 370/331
`
`(57)
`
`ABSTRACT
`
`A digital videointerface system and method for communi-
`cating digital video data from a source device to asink device
`is provided, where the clock channel is used to transmit data
`as well as clock signals in a bi-directional, half-duplex man-
`ner using time division multiplexing. The digital video inter-
`face system comprises one or more data channels configured
`to transmit digital video data from the source device to the
`sink device in time divisional multiplexing including a plu-
`rality offirst time slots and second timeslots, and a clock
`channel configured to transmit a clock signal from the source
`device to the sink deviceinthefirst time slots and configured
`to transmit additional data from the source device to the sink
`device or from the sink device to the source device in the
`secondtimeslots.
`
`32 Claims, 4 Drawing Sheets
`
`408
`
`
`
`data
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`weltancriebamtttenecoiarincadabhanientnnncsiteied
`Clock embedded,half-duplex data channel
`V-Blank
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`Conventional RGB
`Digital Video ios MINNITULAAIMNULTATULTA.
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`interfaces
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`Invention cigck(_Data_)
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`1207
`138
`140
`142
`
`
`
`Roku EX1038
`U.S. Patent No. 9,716,853
`
`Roku EX1038
`U.S. Patent No. 9,716,853
`
`

`

`U.S. Patent
`
`May10, 2011
`
`Sheet 1 of 4
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`US 7,940,809 B2
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`U.S. Patent
`
`May10, 2011
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`Sheet 2 of 4
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`U.S. Patent
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`May10, 2011
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`Sheet 3 of 4
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`U.S. Patent
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`May10, 2011
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`US 7,940,809 B2
`
`1
`DIGITAL VIDEO INTERFACE WITH
`BI-DIRECTIONAL HALF-DUPLEX CLOCK
`CHANNEL USED AS AUXILTARY DATA
`CHANNEL
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This application claims priority under 35 U.S.C. §119(e)
`from co-pending U.S. Provisional Patent Application No.
`60/910,759, entitled “Digital Video Interface with Bi-Direc-
`tional Half-Duplex Auxiliary Data Channel,”filed on Apr. 9,
`2007, which is incorporated by reference herein in its entirety.
`
`BACKGROUND OF THE INVENTION
`
`2
`channels are configured to operate in time divisional multi-
`plexing with a plurality offirst time slots and second time
`slots, and a clock channel configured to transmit a clock
`signal from the source device to the sink device in thefirst
`time slots and configured to transmit additional data fromthe
`source device to the sink device in the second timeslots. The
`clock channel may also be configured to transmit the addi-
`tional data in the opposite direction fromthe sink device to the
`source device in the second timeslots.
`The digital video data are transmitted from the source
`device to the sink device via the data channels in the second
`time slots, while control data corresponding to the digital
`video data are transmitted fromthe source device to the sink
`devicevia the data channels in thefirst time slots. In addition,
`additional control data may be transmitted from the source
`device tothe sink device via the clock channelin thefirst time
`slots.
`1. Field of the Invention
`is configured to
`In one embodiment, the clock channel
`
`The present invention relates to a digital video interface operate in one ofa plurality of operation modes. Inafirst
`mode, the clock signal is transmitted from the source device
`and, more specifically,to a digital video interface that uses the
`to the sink device via the clock channelin thefirst timeslots.
`clock channel as an auxiliary data channel.
`Ina second mode,the additionaldata are transmitted from the
`2. Description of the Related Art
`source device to the sink device via the clock channel in the
`Currentdigital video interfaces such as DV] (Digital Video
`second time slots. In a third mode, the additional data are
`Interface), HDMI (High-Definition Multimedia Interface),
`transmitted from the sink device to the source device via the
`and UDI (Unified Display Interface) typically use 3 or 6 RGB
`clock channelin the second timeslots.
`(Red, Green, and Blue video data) channels for the main data
`Accordingly, the digital video interface system further
`stream and | clock channelfor a frequency reference, in order
`comprises a sourceside transmitter configured to transmit the
`to transmit digital video data between a video source device
`clock signal in the first mode orthe additional data in the
`(e.g.,a digital video disk player) and a videosink device(e.g.,
`second mode to the sink device via the clock channel, a sink
`a high-definition television). Each channel (R, G, B, and
`side receiver configured to receive the clock signalin thefirst
`mode or the additional data in the second mode from the
`clock) is typically comprised of a differential pair of two
`matched wires. The clock channel is used to transmit the
`source device via the clock channel, a sink side transmitter
`frequency reference for the digital video data from the video
`configured to transmit the additional data in the third mode to
`source device to the video sink device, with the clock fre-
`the source device via the clock channel, and a source side
`quency being set to the video data rate ofthe digital video
`receiver configured to receive the additional data in the third
`data.
`mode from the sink device via the clock channel. The sink
`side transmitter is disabled in the first mode and the second
`mode, and the source side transmitteris disabled in the third
`mode.
`In one embodiment, the additional data transmitted via the
`clock channel from the source device to the sink device
`includes a control packet indicating whether subsequent pay-
`load data to be transmitted via the clock channelis ina first
`direction from the source device to the sink device or in a
`second direction fromthe sink device to the source device.
`The digital video interface systemofthe present invention
`enablesa bi-directional, half-duplex, auxiliary data channel
`using the clock channel of the digital video interface, yet
`neither changing the channel composition norsacrificing the
`performance ofthe data channels ofthe digital video inter-
`face. Thus, the clock channel is more efficiently used, and
`more data can be communicated betweenthe source device
`and the sink device without makingany significant changes to
`the channel composition ofthe digital video interfaces.
`The features and advantages described inthe specification
`are notall inclusive and,in particular, many additional fea-
`tures and advantages will be apparent to one of ordinary skill
`in the art in view of the drawings, specification, and claims.
`Moreover, it should be noted that the language used in the
`specification has beenprincipally selected for readability and
`instructional purposes, and may not have been selected to
`delineate or circumscribethe inventive subject matter.
`
`20
`
`30
`
`35
`
`In conventional digital video interfaces such as HDMI, the
`R, G, B data channels transmit video data and control data in
`an alternating manner with time-division multiplexing. That
`is, video data is transmitted in certain timeslots of the R, G,
`B data channels while contro] data is transmitted in other time
`
`40
`
`slots of the R, G, B data channels in an alternating manner.
`The clock signalis transmitted via the clock channel continu-
`ously regardless ofwhether the R, G, B data channels are used
`to transmit digital video data or control data.
`However, once the RGB links becomesettled, the fre-
`quency information is no longer needed by the video sink
`side, because the receiver clock and data recovery circuit in
`the digital videointerfaces can keep the link synchronized
`using the serial RGB data. Thus, conventional digital video
`interfaces use the clock channel inefficiently, transmitting the
`clock signal continuously even whenthe frequency informa-
`tion may not be needed at the video sink. This results in
`inefficient use of the clock channel.
`
`50
`
`Thus, there is a need for a technique for using the clock
`channel ofa digital video interface more efficiently.
`
`55
`
`SUMMARYOFTHE INVENTION
`
`Embodiments of the present invention include a digital
`videointerface system and method for communicatingdigital
`video data from a source device to a sink device, where the
`clock channelis used as an auxiliary data channelto transmit
`data as well as clock signals in a bi-directional, half-duplex
`manner using time division multiplexing. In one embodi-
`ment, the digital video interface system comprises one or
`more data channels configured to transmit digital video data
`from the source device to the sink device, where the data
`
`6
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The teachings of the embodiments of the present invention
`5 can be readily understood by considering the following
`detailed description in conjunction with the accompanying
`drawings.
`
`

`

`US 7,940,809 B2
`
`3
`FIG. 1 is a conceptual block diagram illustrating the bi-
`directional half-duplex auxiliary data channel using the clock
`channel ofthe digital video interface, according to one
`embodimentof the present invention.
`FIG. 2 illustrates a half-duplex link protocolandthe trans-
`ceiver configurations at each TDM (time-division multiplex-
`ing) step for implementing the auxiliary channel using the
`clock channelofthe digital video interface, according to one
`embodimentofthe present invention.
`FIG, 3 illustrates the hardware implementation ofthe bi-
`directional auxiliary data channelusing the clock channelof
`the digital video interface, according to one embodiment of
`the present invention.
`FIG. 4 illustrates the operation of the clock data recovery
`(CDR) circuits of the RGB channels, according to one
`embodiment ofthe present invention.
`
`DETAILED DESCRIPTION OF EMBODIMENTS
`
`The Figures (FIG.) and the following description relate to.
`preferred embodiments of the present invention by way of
`illustration only. It should be noted that from the following
`discussion, alternative embodiments ofthe structures and
`methods disclosed herein will be readily recognized as viable
`alternatives that may be employed without departing from the
`principles of the claimed invention.
`Reference will now be made in detail to several embodi-
`ments of the present invention(s), examples of which are
`illustrated in the accompanying figures. It is noted that wher-
`ever practicable similar or like reference numbers may be
`used in the figures and mayindicate similar or like function-
`ality. The figures depict embodiments ofthe present invention
`for purposes ofillustration only, One skilled in the art will
`readily recognize fromthe following description that alterna-
`tive embodiments ofthe structures and methods illustrated
`
`herein may be employed without departing from the prin-
`ciples of the invention described herein.
`FIG. 1 is a conceptual block diagram illustrating the bi-
`directional half-duplex auxiliary data channel using the clock
`channel of the digital video interface 100, according to one
`embodimentofthe present invention. The digital video inter-
`face 100 transmits digital video data, control data, and clock
`signals from the video source device 102 to the video sink
`device 104. Thedigital videointerface 100 includes transmit-
`ters (TX) 108, 110, 112 for transmitting R, G, B digital video
`data, respectively, from the video source 102 over the video
`cables 106 to the video sink device 104. The digital video
`interface 100 alsoincludes receivers (RX) 114, 116, 118 for
`receiving the R, G, B digital video data, respectively, over
`video cables 106 at the video sink 104. The R. G, B channels
`are unidirectionalfrom the video source 102 to the video sink
`104. The video cables 106 include 4 differential pairs (3+1) of
`2 wires, with eachof the 4 pairs corresponding tothe R, G, B,
`and clock channels, respectively.
`The digital video interface 100 also includes a clock chan-
`nel 120. The clock channel 120 includes a transmitter 124 for
`transmitting clock and data fromthe video source 102 to the
`video sink 104 via the video cable 106 and a receiver 126 for
`receiving the clock anddata from the video source 102 at the
`video sink 104 via the video cable 106, Thus, unlike the clock
`channel of conventional digital video interfaces, the clock
`channel 120 of the digital video interface 120 ofthe present
`invention is used to transmit both clock and data. The clock
`
`channel 120 also includesa transmitter 128 for transmitting
`data from the video sink 104to the video source 102 via the
`videocable 106 and a receiver 122 for receiving the data from
`the video sink 104 at the video source 102 via the video cable
`
`o
`
`wa
`
`2
`
`4
`106. Thus, unlike the clock channel of conventional digital
`video interfaces, the clock channel 120 ofthe digital video
`interface 120 ofthe presentinventionis bi-directional and can
`be used to transmit data in both directions between the video
`source 102 andthe video sink 104.
`As shownin FIG, 1, the conventional digital video inter-
`face protocol consists of repetitive ‘V-blank’(Vertical Blank)
`and ‘active’ sequences(or time slots) alternating in a time-
`divisional multiplexing (TDM) manner. The RGB channels
`131 transmit control signals (Ctrl) during the V-blank
`sequences and video data (Data) during the active sequences
`in an alternating manner, The clock channel 130 of the con-
`ventional digital video interface continuously transmits the
`clock signal 129 regardless ofwhether the RGBchannels are
`in the V-blank sequencesor in the active sequences.
`In contrast, the clock channel 120 of the present invention
`is configured to transmit data (in addition to the RGB data
`transmitted via the RGB channel) as well as clock signals.
`The clock channel 120 of the present inventionapplies time-
`division multiplexing (TDM) to the clock channel to enhance
`the clock channelutility. The clock channel 120 is configured
`to transmit clock signals and additional control signals (e.g.,
`frame headers, control packets, etc.) 138 while the RGB
`channel 119 transmits control data (Ctrl) 143 during the
`s V-blank sequences, and transmits data signals (Data) 140,
`142 while the RGB channel 119 transmits video data (Data)
`144 during the active sequences, The TDMof the clock chan-
`nel 120 is synchronized to the sequences (video channel
`periods) of the RGBchannels 121.
`The data 140, 142 may be, for example, audio data or other
`types of data. The clock channel 120 transmits data signals
`140, 142 bidirectionally. For example, the data 140 is trans-
`mitted in the direction from the video source 102 to the video
`sink 104 via the clock channel 120, and the data 142 is
`transmitted in the direction from the video sink 104 to the
`video source 102 via the clock channel 120. Thus,an auxil-
`iary data channel in addition to the RGB channels 121 is
`enabled by the clock channel 120. The clock channel 120 is
`bi-directional but half-duplex in the sense that data 140 and
`142are in different directions but that data can be transmitted
`
`had 5
`
`40
`
`4on
`
`a0
`
`only uni-directionally at a time in each sequence. Thus, the
`clock channel 120 does nottransmit data in bothdirectionsat
`the same time. By adopting a half-duplex protocol, the aux-
`iliary data channel can be easily transformed toa bi-direc-
`tional link, providing great flexibility in dynamic allocation
`of bandwidth, compared to the conventional digital video
`interfaces.
`FIG. 2 illustrates a half-duplex link protocolandthe trans-
`ceiver configurationsat each TDM step for implementing the
`auxiliary channel over the clock channel of the digital video
`interface, according to one embodimentofthe present inven-
`tion. The clock-embedded, half-duplex data channel imple-
`mented over the clock channel 120 is comprised of trans-
`ceiver cores in each video source/sink sides and a TDM
`
`protocol to control them.
`As shown in FIG,2, the clock channel 120 andtransceiver
`pairs have 3 operation modes—A,B, and C. In mode A,the
`clock pattern 138 is transmitted from the video source 102 to
`the video sink 104 via the clock channel 120 during V-blank
`sequences(time slots) of the RGB channels 121. In mode B,
`data 140 (NRZ (Non-Return to Zero) data) is transmitted
`fromthe video source 102 to the video sink 104 via the clock
`channel 120 during active sequences(timeslots) of the RGB
`channels 121. In mode C, data 142 (NRZ pattern)is transmit-
`ted in the opposite direction from the video sink 104 to the
`video source 102 via the clock channel during V-blank
`sequences of the RGB channels 121. Therefore, in modes A
`
`

`

`US 7,940,809 B2
`
`a
`and B, the source receiver 122 and the sink transmitter 128 are
`disabled(as illustrated by the high impedance notation Z in
`the sink transmitter 128). In mode C, the source transmitter
`124 and thesink receiver 126 are disabled (as illustrated by
`the high impedancenotation Z in the source transmitter 124).
`Referring to the example sequence of modes as shown in
`FIG, 2, in mode B 150, the data 140 (the frame header 170) is
`transmitted from the video source 102 to the video sink 104
`during the V-blank timeslot via the clock channel 120 using
`the transmitter 124 and the receiver 126. In mode A 152, the
`clock signal 138 (which is the training sequence 172) is
`transmitted fromthe video source 102 to the video sink 104
`
`during the V-blank timeslot via the clock channel 120 using
`the transmitter 124 and the receiver 126. The clock sequence
`138 is used as a frequency reference for main RGB data
`channels while subsequent control packet sets up a link pro-
`tocol for the auxiliary data channel. In mode B 154, data 140
`whichis a control packet 174 is transmitted from the video
`source 102 to the video sink 104 during the V-blank timeslot
`via the clock channel 120 using the transmitter 124 and the
`receiver 126. The control packet 174 indicates whether the
`next data streamis upward (fromsink to source) or downward
`(from source to sink), and the subsequent data stream is
`transferred accordingly during the active period. For
`example, the control packet 174 indicates downstreamtraffic.
`In addition, the control packet 174 may contains training
`sequences which help the auxiliary channel transmitter/re-
`ceiver switch their operation mode smoothly.
`Sull in mode B 154, data 140 which is payload data 176,
`178 are transmitted from the video source 102 to the video
`
`sink 104 during the active timeslot via the clock channel 120
`using the transmitter 124 and the receiver 126, Additionally in
`mode B 154, data 140 whichis a frame header 180 is also
`transmitted fromthe video source 102 to the video sink 104
`during a V-blank time slot via the clock channel 120 using the
`transmitter 124 and the receiver 126. Next, in mode A 156,
`another clock signal 138 (training sequence 182) is transmit-
`ted from the video source 102 to the videosink 104 during the
`V-blank timeslot via the clock channel 120 using the trans-
`mitter 124 and the receiver 126. In mode B 158, data 140
`
`(control packet 182) is transmitted from the video source 102
`to the video sink 104 via the clock channel 120 during the
`\-blank time slot using the transmitter 124 and the receiver
`126. This time, the control packet 182 indicates that the
`subsequent data stream will be transferred in the opposite
`direction from the video sink 104 to the video source 102.
`Thus, in mode C 160, data 142 (payload data 184, 186) is
`transmitted fromthe video sink 104 to the video source 102
`during the active time slot via the clock channel 120 using the
`transmitter 128 andthe receiver 122.
`
`The auxiliary data channel using the clock channel 120 of
`the presentinvention has an aggregate bandwidth comparable
`to one of the main stream channels (R, G, or B). The source
`device can control
`the bandwidth allocation between
`
`upstreamtraffic and downstream traffic between the video
`source 102 andthe videosink 104. Through a dynamic band-
`widthallocation, the auxiliary channelcan beeither dedicated
`to uni-directional communication or shared by the upward or
`downward data streams, maximizing bandwidth efficiency.
`FIG. 3 illustrates the hardware implementation 300 ofthe
`bi-directional auxiliary data channel using the clock channel
`ofthe digital videointerface, according to one embodimentof
`the present invention. Note that FIG. 3 only shows compo-
`nents necessary forillustrating the present invention, but the
`hardware mayinclude other componentsnot shown in FIG, 3
`in actual implementations. The hardware 300 includes a mas-
`ter link layer 302 corresponding to the video source 102, a
`
`wa
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`20
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`30
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`35
`
`6
`slave link layer 304 corresponding to the video sink 104,
`wires 106 connecting the masterlink layer 302 with the slave
`link layer 304, sourceside transmitter 124 for the clock chan-
`nel 120, source side receiver 122 for the clock channel 120,
`sink side receiver 126 for the clock channel 120, and sink side
`transmitter 128 for the clock channel 120.
`The RGB channels include latches 350 for storing RGB
`data, output drivers 352 for sending the RGB data via the
`cable 106, receiver buffers 354 for receiving and storing the
`received RGB data, and clock data recovery (CDR) circuits
`356 for recovering the data and clock signals. RGB data are
`transmitted over the RGB channels at the frequency ofthe
`transmitter clock Tclk as provided by the phase locked loop
`(PLL) 318 ofthe sourceside transmitter 124. Notethat, in one
`embodiment, three identical data channels exist (as shown in
`the three overlappingblocks in FIG, 3), one each for R, G, B.
`Aswill be explained in more detail with reference to FIG. 4,
`the RGB CDRs 356 acquire a frequency lock during the
`period when the clock pattern 138 is transmitted over the
`auxiliary channel implemented by the clock channel 120,
`then acquire phase lock to the incoming RGBdata, and pro-
`vide a stable receiver clock (Relk) to the sink side transmitter
`128 while it delivers NRZ data from the sink device 104 to the
`source device 102.
`Asillustrated above, the source side transmitter 124 is
`active in mode A and mode B, and includes a phase locked
`loop (PLL) circuit 318, a multiplexer 316, a latch 322, and an
`output driver 324. The multiplexer 316 is configured to select
`the clock signal Telk 138 in mode A and the data 140 in mode
`B in responseto a selection signal (not shown herein). The
`PLL 318 synchronizes to the clock signal Tclk and provides
`the synchronized clock signal to the latch 322, the multiplexer
`346 in the source side receiver 122, and the latches 350 in the
`RGBchannels. The latch 322 temporarily stores the output
`(either Tclk 138 in mode A or data 140 in mode B) ofthe
`multiplexer 316, and the output driver 324 transmits the
`stored clock signal Telk 138 or data 140 over the cable 106 to
`the sink side receiver 126.
`Thesink side receiver 126 is active in mode A and modeB,
`and includes a receiver buffer 340, a multiplexer 332, and a
`clock data recovery (CDR) circuit 330. The receiver buffer
`340 receives the clock signal Tclk 138 in mode Aorthe data
`140 in mode B astransmitted bythe source side transmitter
`124. In mode A,the received clock signal Tclk 138 is pro-
`bewT
`5 vided to the CDRcircuit 356 of the RGB channels,so that the
`CDRcircuit 356 can be tuned to the proper frequency to
`recover RGBdata correctly. Additional detailed explanation
`regarding the operation of the CDRcircuit 356 is set forth
`below with reference to FIG.4. In mode B the multiplexer 332
`selects the received data signal 140, but in mode A or mode C
`the multiplexer 332 selects the output clock 346 ofthe PLL
`336 foridling. In mode B, the CDRcircuit 330 recovers NRZ
`data (data) from the received data signal 140 and provides the
`recovered NRZ data 360) to the synchronizationcircuitry 308
`of the slave link layer 304. The synchronization circuitry 308
`synchronizes the recovered NRZ data 360 with the receiver
`clock Relk recovered by the CDR circuit 356 of the RGB
`channels.
`The sink side transmitter 128 is active in mode C, and
`includes a phase locked loop (PLL) circuit 366, a latch 334,
`and an output driver 338. The PLL 336 synchronizes to the
`receiver clock signal Relk recovered by the CDR circuit 356
`of the RGB channels, and provides the synchronized clock
`signal to the latch 334 and the multiplexer 332 in the sink side
`receiver 126. The latch 334 temporarily stores the data 142,
`and the output driver 338 sends the stored data 142 over the
`cable 106 to the source side receiver 122.
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`US 7,940,809 B2
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`7
`The source side receiver 122 is active in mode C, and
`includes a receiver buffer 326, a multiplexer 346, and a clock
`data recovery (CDR) circuit 328. The receiver buffer 326
`receives the data 142 in mode C as transmitted by the sink side
`transmitter 128 and provides it to the multiplexer 346. In
`mode Cthe multiplexer 346 selects the received data signal
`142, but in mode A or mode B the multiplexer 346 selects the
`output clock Tclk 344 of the PLL 318 for idling. In mode C,
`the CDR circuit 328 recovers NRZ data (data) from the
`received data signal 142 and providesthe recovered NRZ data
`364 to the synchronization circuitry 306 of the master link
`layer 302. The synchronization circuitry 306 synchronizes
`the recovered NRZ data 364 with the transmitter clock Telk.
`Asillustrated above, the architecture of each transmitter
`and receiveris different from conventional implementations,
`for example in the reference clock configuration. The CDRs
`in the auxiliary data channel (implemented by the clock chan-
`nel 120) alternatesits reference between system clock (Tclk
`in Source and Relk in Sink) and incoming data according to
`the link operation mode. In modes A and B,the source side
`CDR328is synchronizedto the system clock (Tclk) from the
`PLL 318 while the sink side CDR 330 is synchronizedto the
`incoming data (data 140). In mode C, the source side CDR
`328is synchronized to the incoming data (data 142) while the
`sink side CDR 330 is synchronized to the system clock (Relk)
`from the PLL 336. When the CDRs 328, 330 change their
`reference, a lock-in period is needed for the CDR loops to
`settle. The training sequences 172, 182 in the control packets
`help the CDRs 328, 330 switch their reference quickly and
`smoothly.
`As shownin FIG. 3, the source and sink devices are in a
`single mesochronous clock system, in whichall the building
`blocks operate in a single frequency domain but may not be
`aligned in phase. Thus, the phase synchronization blocks 306,
`308 are used at the boundary of the two different clock
`domains, but the cost of such phase synchronization blocks
`306, 308 is very low becausethe data rates are exactly iden-
`tical. No flow control suchas data rate conversionis required.
`Hence the phase synchronization blocks 306, 308 align the
`recovered data phase with the system clock phase to maxi-
`mize setup/hold time margins.
`As shown in FIG.3, the masterlink layer 302 handles the
`TDM based half-duplex communication protocol
`and
`dynamically allocates the auxiliary channel bandwidth to the
`upward or downward data stream. Since the uni-directional
`RGB channels are independent and identical to conventional
`DV] and HDMI RGBchannels,the digital video interface of
`the present invention can be fully compatible with conven-
`tional digital video interfaces by simply disabling the TDM
`operation in the clock channel 120.
`FG. 4 illustrates the operation of the clock data recovery
`(CDR)circuits 356 of the RGB channels, according to one
`embodiment ofthe present invention. Each of the CDR cir-
`cuits 356 for the RGB channel includes a data recovery loop
`402 and a frequency tracking loop 404. The data recovery
`loop 402 recovers RGB data from the NRZ RGBdata
`received over the RGB data channel using conventional data
`recovery circuits and techniques. The frequency tracking
`loop 404 tunes the center frequency ofthe CDR circuit 356 to
`the NRZ data rate of the RGB channel using conventional
`frequency tracking techniques, and the data recovery loop
`402 also regenerates the receiver clock signal Relk based on
`the tuned (locked) frequency. However, the data recovery
`loop 402 and the frequency tracking loop 404are unique and
`different from the conventional data recovery loop and the
`conventional frequency tracking loop in conventional CDR
`
`20
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`8
`in that they are enabled or
`circuits for the RGB channel,
`disabled also in a time-division multiplexed manner.
`Specifically, the data recovery loop 402 andthe frequency
`tracking loop 404 are enabled or disabled depending upon the
`operation modes of the auxiliary data channel implemented
`by the clock channel 120 and what auxiliary channel data
`(clock Telk 138 or data 140) are received over the auxiliary
`data channel. As shownin FIG. 4 together with reference to
`FIG. 3, whenthe receiver buffer 340 receives and outputs the
`clock signal Telk 138 over the auxiliary data channel during
`the V-blank period of the RGB channel, the CDR 356 is in
`frequency tracking mode. In the frequency tracking mode, the
`frequency tracking loop 404 is enabled, tuning the center
`frequency of the CDRcircuit 356 to the NRZ datarate of the
`RGBchannel, while the data recovery loop 402is disabled.
`Once the frequency tuning is done, the freq_lock signal is
`asserted from the frequency tracking loop 404 to the data
`recovery loop 402. This freq_lock signal enables the data
`recovery loop 402 to recover the RGB data from the NRZ
`RGBdata and regenerate the receiver clock Relk, making the
`CDRcircuit 356 enter clock/data recovery mode in which the
`data recovery loop 402 is enabled. Once the CDR 356 enters
`clock/data recovery mode, the frequency tracking loop 404is
`disabled, and is periodically activated only when the clock
`rm a
`5 pattern 138 is presentat the auxiliary data channelto check if
`the CDR 356 is running at the correct frequency. Typically,
`the V-Blank period is as long as several thousands times of a
`pixel period, which is long enough for the CDRs 356 to
`acquire frequency lock and smoothly changeits reference to
`the RGB NRZ data, As long as the NRZ RGB data are present,
`the CDR circuit 356 can sustain phase lock state by itself
`using the NRZ RGB data transitions as phase references.
`Thus, once the CDR 356 enters frequency lock state and
`switchesto clock/data recovery mode,it can provide a stable
`receiver clock (Relk) to the slave link layer 304 and the
`auxi