|||||||||||||||||||||||||l|||||||||||||||||||||||||||||||||||||||||||||||||
`
`U800794829OB2
`
`(12) United States Patent
`(10) Patent 140.:
`US 7,948,290 32
`
`Rate
`(45) Date 01' Patent:
`May 24, 2011
`
`(54} DIGITAL p”. DEVICE
`_
`.
`..
`Inve‘mr‘
`33"“11Kat0'0531‘aflpl
`_
`[73} Asslgm‘t-‘I Panasonic (-70l‘P9rafiufl-0mkatlpi
`
`(75)
`
`(*1 Notice:
`
`Subject to an}.r disclaimer. the ternwfthis
`patent is extended or adjusted under 35
`11.51:. 154(0) byOdays.
`
`5.034.901 A *
`5.945.856 A
`5.990.110 A *
`0.099.??? .4
`0.111.470 A -
`6.188.290 n1r
`0.331513 31-
`
`(“550-193 32'
`5'687'3“ '31
`
`............................. 332.42?
`I1.-I990 Den!
`81999 Ynnagiuchi
`10-1999 Li
`................................... 391-43
`0-3000 'l'ateishi ctal.
`0-2000 Dut‘our
`2.2001 Fallisgaard etaI..
`12.52001 Brown etal.
`..
`
`331:1?
`33l-"t8
`33152
`
`
`---------------------- 3315-73
`
`11*:3003 Emil)“ 31-
`32004 Nam“
`(Continued)
`
`(2” App1.No.:
`
`121439 644
`
`(22)
`
`PC'l‘Ii'iled:
`
`.ltll.8.2tIl}8
`
`(N
`
`FOREIGN PATIENTDOCUMENTS
`1409490 .4
`4-9003
`
`{Continued}
`
`(86}
`
`PC"1'No.:
`
`[’(I'l'tJPZUOSIOUISZT
`
`OTHER PUBLICATIONS
`
`3137] (CHI).
`{2). [-1) Date: Mar. 2. 2009
`
`High-Definition Multimedia Interface Specification Version L3a.
`NOV-193005-
`
`[tm PC“l'Pnb.No.: W()2t)09t013860
`PCT Pub. Date: Jan. 29, 2009
`
`(65}
`
`(30)
`
`Prior Publication Data
`US 20101011017173 A]
`Jan. 7. 2010
`
`Foreign Application Priority Data
`
`Jul. 23. 2007
`
`(11")
`
`2007-1901105
`
`(5])
`
`int. Cl.
`”03L 7/06
`{52) U.S. (II.
`[58}
`Field of Classification Search
`See application file for complete search history.
`
`(2006.01)
`
`3271'159; 3271150
`None
`
`(56)
`
`References Cited
`
`U.S. PATIENT I)(XTUM}ENTS
`
`4.3[10'35 A ‘
`5.028.387 A *
`5.265.081 A
`
`Till-"ll?
`131989 Rediget 2.1.
`'JI‘.-’199l Gilmore .......................... 331518
`| 1-"1993 Shimizumc et at.
`
`(cont'mled)
`- Cassandra Cox
`Primarji' Ermiiiner -
`(74) .Ittwrmjt'. Agent. or firm — McDemtott Will St Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`[requency-divides an input
`An input clock dividing unit
`clock. and an input clock multiplying unit frequency-mulli-
`piies the input clock. An operation clock selecting unit selects
`the frequency-divided clock when tlte input clock is fast and
`selects the frequetlcyvtnultiplied clock when the input clock is
`slow. based on the frequency detection result of frequencyr
`detecting unit. The operation clock selecting unit then outputs
`the selected clock to a phase comparing unit as an operation
`clock. The phase comparing unit operates according to the
`frequency-divided or Frequency-multiplied clock. and con-
`trols an oscillating unit so that the phase difference between a
`reference signal and a comparison signal becomes zero. The
`phase of an output clock is thus caused to track the phase of
`the reference signal.
`
`11 Claims, '1‘ Drawing Sheets
`
`INPUT
`
`CLOCK
`
`INP UT 0 LO 0 K
`MULTIPLYING
`UNIT
`
`OPERATION CLOCK
`
`OUTPUT
`CLOCK
`
`Roku EX 1 040
`
`US. Patent No. 9,716,853
`
`
`
`
`f2
`REFERENCE
`
`
`PHASE
`OSCILLATING
`
`
`
`UNIT
`n DlljflfilNG
`SIGNAL
`COMPARING
`UNIT
`
`1
`
`
`
`
`GO MPARISON
`SIGNAL
`
`
`
`Roku EX1040
`U.S. Patent No. 9,716,853
`
`

`

`US 7,948,290 82
`Page 2
`
`5.74 1 .846
`6.7517 1 1
`6.882.229
`7.2 l 5. 165
`7.301.414
`7.3 [2.649
`7.3 94,870
`7.4 36.264
`7.5 [2.205
`200 1 1'00 I75 73
`200630171496
`2000-0176525
`
`U.S. PATENT DOCUMENTS
`131*
`572004 Wellandcta].
`.........
`B2 “
`672004 McCollum cl :11.
`
`BI *
`4:“2005 Ho 12131.
`
`Bl ‘
`5:"2007 Yamamolo et a1.
`Bl ‘ 11.0007 Hino .................
`
`B2 *
`12-"2007 Origasa er a].
`32 *
`772008 Chicn Ct 51].
`
`Bl *
`10:"2008 Yu .............
`-- 33“”
`BI‘
`3.12009 Erol
`..............
`
`3751376
`Al‘
`8-"2001 Fallisgamdeta].
`331713
`Al
`812005 Nakamuta er a].
`A1“
`812005 Mizutaelal.
`...........
`...... 3587474
`
`...... 4557250
`3277156
`331:1 A
`3277156
`33 1:179
`327-636
`3757316
`
`JP
`JP
`JP
`JP
`JP
`
`FOREIGN PATENT DOCUMENTS
`10-2 24336
`871998
`2003 647933
`[27.2003
`2004-2 895 57
`[0.12004
`2007—08200!
`3"2007
`2007—0138398
`472007
`
`OTHER PUBLICA’I‘IONS
`
`Japanese Notice of Reasons for Rejection. with English tmnsIation.
`issued in Jamese Patenl Application No. zoos-554553. dated Jun.
`29.2010.
`
`* cited by examiner
`
`

`

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`US. Patent
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`US 7,948,290 E32
`
`2
`
`1
`DIGITAL PLL DEVICE
`
`RELATED APPLICATIONS
`
`signal is caused to track the phase ofthe reference signal. By
`thus locking the output clock to (l 28sz]. F5 can be regen-
`erated by the sink device.
`1: High-Definition Multimedia
`Non-patent document
`Interface Specification Version I .3a
`
`DISCLOSURE OF THE INVENTION
`
`Problems to be Solved by the Invention
`
`When a transmitted clock is fast in the above conventional
`digital PLL device. an operation clock is fast. causing
`increase in circuit scale and significant increase in power
`consumption. When the transmitted clock is slow. on the other
`hand. the operation clock is slow, causing increase in jitter
`and increase in tracking time.
`The transmitted clock has been increasingly becoming
`faster especially dtte to Deep Color defined in the l-IDMI
`specification. recent higher definition of image. and the like.
`Under such circumstances. conventional digital PLI. devices
`have been increasingly suffering from problems such as
`increased circuit scale and significantly increased power con—
`sumption.
`The conventional PLL devices thus have problems such as
`increased circuit
`scale.
`increased power consumption.
`iucreasedjitter. and increased tracking time depending on the
`transmitted clock rate.
`In view of the above problems. it is an object of the present
`invention to provide a digital PLL device having a structure
`capable of suppressing increase in circuit scaie and increase
`in power consumption when a transmitted clock is fast. and to
`provide a digital PLL device having a structure capable of
`suppressing increase in jitter and increase in tracking titne
`when a transmitted clock is slow.
`
`5
`
`It]
`
`21']
`
`I.) .1:
`\
`
`3t]
`
`35
`
`Means for Solving the Problems
`
`This application is the US. National Phase under 35 U.S.C.
`§371 of International Application No. PC'I‘IJPZOOSIOOI 8227.
`filed on Jul. 8. 2008. which in turn claims the benelit of
`
`Japanese Application No. 2007490405. filed on Jul. 23.
`2007. the disclosures ofvvhich Applications are incorporated
`by reference herein.
`
`TECHNICAL FIELD
`
`The present invention generally relates to a digital PLL
`device. More particularly. the present invention relates to a
`digital PLL device that is used for. for example, regeneration
`of an audio clock from a clock transmitted through a digital
`interface such as IEEE [394 and HDMI (High-Definition
`Multimedia Interface) used in a digital television and an AV
`amplifier.
`
`BACKGROUND A RT
`
`Many digital interfaces employ a system in which a param-
`eter is created by a transmitting party according to a prede-
`termined formula and a required audio clock is regenerated
`from a transmitted clock by using the parameter. As a typical
`structure of this system, a digital PLL is used by itself or in
`combination with an analog PLL.
`It has been common in the art to use a transmitted clock as
`
`an operation clock of a digital PLL for regenerating a clock
`(cg, see Non-patent document 1).
`FIG. 7 is a block diagram showing a structure of a conven-
`tional digital PLL device.
`The conventional digital PLI . device of FIG. 7 includes an
`n dividing tmit 1, a phase comparing unit 2. an oscillating u nit
`3. and an in dividing unit 4.
`As shown in FIG. 7, the n dividing unit 1 frequency-divides
`a clock transmitted through a digital interface by n to produce
`a digital PLL reference signal. The phase comparing unit 2
`operates by using the transmitted clock as an operation ctock.
`The phase comparing unit 2 obtains the phase diflerence
`between the reference signal generated by the n dividing unit
`1 and a comparison signal generated by dividing an output
`clock by m in the m dividing tmit 4. and outputs a control
`signal so as to reduce the phase difference. The oscillating
`tmit 3 changes the output clock by the control signal received
`from the phase comparing unit 2. This operation is repeated as
`a feedback loop. whereby the phase of the output clock is
`caused to track [lock to) the phase of the reference signal.
`For example. in an I-IDM] specification. parameters N and
`CTS are prepared as parameters for regenerating an audio
`clock. These parameters are defined by the following for-
`ntula:
`
`CH=t1mnsmilted clockxNI.-'[128xi'iit
`
`In order to achieve the above object, a digital PLL device
`according to one aspect of the present invention includes: an
`operation clock generating tmit configured to output a fre-
`quency-divided or frequency-multiplied input clock as an
`operation clock: an n dividing unit configured to frequency-
`divide an input clock by n to output a reference signal: a phase
`comparing unit configured to compare the reference signal
`. with a comparison signal and output a control signal: an
`oscillating unit configured to change an oscillation frequency
`of an output clock according to the control signal: and an m
`dividing unit configured to frequency-divide the output clock
`by m to output the comparison signal.
`In the digital PLL device according to the above aspect of
`the present invention, the operation clock generating unit is an
`output clock dividing unit configured to frequency-divide the
`input clock and output the resultant clock as the operation
`clock.
`
`5t]
`
`55
`
`In this case. the n dividing unit frequency-divides the
`operation clock instead of the input clock by n to output the
`reference signal. and the digital PLI. device further includes
`an input clock multiplying tmit configured to frequency-mol-
`tiply an output of the oscillating uttit and output the resultant
`clock.
`
`In the digital PLL device according to the above aspect of
`the present invention. the operation clock generating unit is an
`input clock multiplying unit configured to frequencyvmulti—
`ply the input clock and output the resultant clock as the
`operation clock.
`In this case. the n dividing unit frequency-divides the
`operation clock instead of the input clock by n to output the
`
`where Fs {Sampling Frequency) indicates an audio clock.
`A source device as a transtnitter determines the value of
`
`CTS by counting the number oftransmitted clocks in each of
`the (l28xlrs/N) clocks. A sink device as a receiver frequency-
`divides the transmitted clock by (TS to generate a digital
`PLL reference signal. By repeating an operation of compar-
`ing the phase ofa comparison signal generated by frequency—
`dividing an output signal by N with the phase ofthe generated
`reference signal and controlling the output clock so that the
`phase difference becomes zero. the phase of the comparison
`
`till]
`
`

`

`US 7,948,290 E32
`
`3
`reference signal. and the digital PLL device further includes
`an output clock dividing unit configured to frequency-divide
`an output ofthe oscillating ttnit and output the resultant clock.
`In the digital PLL device according to the above aspect of
`the present invention. the operation clock generating unit
`further includes an input clock dividing unit configured to
`frequency—divide the input clock and output the resultant
`clock. an input clock multiplying unit configured to fre-
`quency-multiply the input clock and output the resultant
`clock. and an operation clock selecting unit configured to
`select the output ofthe input clock dividing unit or the output
`of the inpttt clock multiplying unit and otttput the selected
`output as the operation clock.
`In this case. the digital PLL device further inclttdes a fre-
`quency detecting unit configured to detect a frequency of the
`input clock and output a frequency detection result. wherein
`the operation clock selecting unit selects the output of the
`input clock dividing ttnit or the output of the input clock
`tnuitiplying unit based on the frequency detection result.
`In the digital PLI. device according to the above aspect of
`the present invention, the n dividing unit frequency—divides
`the operation clock from the operation clock selecting ttnit
`instead of the input clock by 11 to output the reference signal.
`and the digital PLL device further includes: an output clock
`multiplying ttnit configured to frequency-multiply an output
`of the oscillating unit and output the resultant clock; an output
`clock dividing ttuit configured to freqttency~divide the output
`of the oscillating will and output the resultant clock: and an
`output clock selecting imit configured to select the output of
`the output clock multiplying unit or the output of the output
`clock dividing unit and output the selected output.
`In this case. the digital PLL device fttrlher includes a fre-
`quency detecting unit configured to detect a frequency 0 f the
`input clock and output a frequency detection result. the opera-
`tion clock selecting unit selects the output of the input clock
`dividing unit or the output of the input clock multiplying ttnit
`based on the frequency detection result. and the output clock
`selecting unit selects the output of the output clock multiply-
`ing unit orthe output of the output clock dividing unit based
`on the frequency detection result.
`In the digital PLL device according to the above aspect of
`the present invention,
`the phase comparing unit operates
`according to the operation clock.
`In the digital PLL device according to the above aspect of
`the present invention. the input clock is transtnitted through a
`digital interface.
`In the digital PLL device according to the above aspect of
`the present invention. the digital interface is IIEIEIE 1394 or
`I-lI)Ml.
`
`Effects ofthe Invention
`
`the digital PLL device
`As has been described above.
`according to one aspect of the present invention can reduce
`the circuit scale. power consumption. jitter. and tracking time
`regardless of the transmitted clock rate, as compared to cott-
`ventional digital PLI. devices.
`The transmitted clock rate has been rapidly increased due
`to. for example. an improved resolution resulting from Deep
`Color defined by the HDMI specification or recent increase in
`screen size ofdisplay devices. Accordingly. increase in circuit
`scale and increase in power consumption clue to the high-
`speed operation. for example. can be suppressed by operating
`the digital I’LL device based on a frequencydivided fast
`transmitted clock. In the case where the high—speed operation
`of the transmitted clock is not required such as in low-end
`devices. increase in jitter and increase in tracking time due to
`
`5
`
`It]
`
`21']
`
`I.) 1):
`
`3t]
`
`35
`
`4U
`
`50
`
`55
`
`an
`
`4
`
`the low-speed operation, for example. can be suppressed by
`operating the digital PLL device based on a frequency-mul-
`tiplied transtnitted clock.
`
`BRIEF [DESCRIPTION OF TI "-3 DRAWINGS
`
`FIG. 1 is a block diagram showing a structure ofa digital
`PLL device according to a first embodiment of the present
`invention:
`
`FIG. 2 is a block diagram showing a structure of a digital
`PLI, device according to a second embodiment ofthe present
`invention:
`FIG. 3IS a block diagram showinga structure of a digital
`I’LL device according to a third embodiment of the present
`invention;
`I-‘G. 4is a block diagram showing a structure of a digital
`PLL device according to a fourth etnbodiment of the present
`invention;
`FIG. 5 is a block diagram showing a structure of a digital
`PLL device according to a fifth embodiment of the present
`invention;
`FIG. 6 is a block diagram showing a structure ofa digital
`PLL device according to a sixth embodiment of the present
`invention: and
`F. G. 7Is a block diagram showing a structure of a conven-
`tional digital PI I device
`
`
`
`DESCRIPTION OF THE REFERENCE
`NUMERALS
`
`l n dividing unit
`2 phase comparing ttnit
`3 oscillating tutit
`4 m dividing unit
`5 input clock dividing unit
`6 input clock mttltiplying ttnit
`7 operation clock selecting unit
`8 frequency detecting unit
`9 output clock. multiplying unit
`10 output clock dividing unit
`11 output clock selecting unit
`
`BILST MODE FOR CARRYING OUT ‘I'[ IIi
`INVENTION
`
`I-Iereinafier. embodiments ofthe present invention will be
`described with reference to the accompanying drawings.
`
`First Etnboditnent
`
`FIG. 1 is a block diagram showing a structure ofa digital
`PLL device according to a first embodiment of the present
`invention.
`
`The digital PLL device according to the first embodiment
`of the present invention shown in FIG. 1 includes an n divid-
`ing unit 1. a phase comparing unit 2. an oscillating unit 3. an
`m dividing unit 4. and an input clock dividing unit 5.
`Operation ofthe digital PLL device ofthe present embodi-
`ment having the above structure will now be described.
`As shown in FIG. 1. the a dividing unit 1 frequency-divides
`an input clock transmitted through a digital interface by n (n
`is a natural number] to generate a digital PLL reference sig-
`nal. The input clock dividing ttnit 5 frequency~divides the
`input clock and outputs the resultant clock to the phase com—
`paring ttnit 2 as an operation clock. The phase comparing unit
`2 operates according to the operation clock received from the
`input clock dividing unit 5. The phase comparing unit 2
`
`

`

`US 7,948,290 132
`
`5
`obtains the phase difference between the reference signal
`generated by the n dividing unit I and a comparison signal
`generated by frequency-dividing an output clock by 111 [m is a
`natural number) in the m dividing unit 4. and outputs a control
`signal so that the phase difference becomes zero. The oscil-
`lating unit 3 changes the output clock by the control signal
`received from the phase comparing unit 2.
`Provided that tlte input clock frequency is x hertz and the
`output clock frequency is y hertz, the reference signal fre-
`quency is xfn hertz. Since the phase of the comparison signal
`tracks the phase ofthe reference signal. the comparison signal
`frequency is also xiii hertz. The output clock frequency is
`therefore y --{xxm)t’n hertz. A desired output clock is thus
`obtained.
`As has been described above. according to the digital PLL
`device of the first embodiment of the present invention. the
`phase comparing unit 2 can be operated by using a frequency-
`divided input clock as an operation clock. This structure
`suppresses increase in circuit scale and increase in power
`consumption caused by high-speed operation due to a high-
`speed transmitted clock, as compared to conventional digital
`PLL devices in which the phase comparing unit 2 is operated
`by using an input clock directly as an operation clock.
`Note that
`the input clock and the frequency dividing
`parameters In and It may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`
`cannot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. lixamples of such
`a digital interface includeaudio transmission of ll-EIEE 1394 or
`HUM].
`
`1t]
`
`21']
`
`I.) u:
`
`3t]
`
`Second Embodiment
`
`FIG. 2 is a block diagram showing a structure ol‘a digital
`PLL device according to a second embodiment of the present
`invention.
`
`35
`
`The digital PLL device according to the second embodi-
`ment of the present invention shown in FIG. 2 includes an n
`dividing unit 1. a phase comparing unit 2. an oscillating unit
`3. an m dividing tmit 4. and an input clock multiplying ttnit 6.
`Note that. as compared to the structure of the digital PLL
`device of the first embodiment shown in FIG. 1. the structure
`
`51]
`
`of the digital 1’th device of the present embodiment is char-
`acterized by including the input clock multiplying unit 6
`configured to frequency-multiply an input clock instead of 45
`the input clock dividing unit 5 of the first embodiment cott-
`figured to li'equency-divide an input clock.
`Operation ofthe digital PI..l. device of the present embodi-
`ment having the above structure will now be described.
`As shown in FIG. 2. the 11 dividing unit 1 frequencyoivides
`an input clock transmitted through a digital interface by n to
`generate a digital PLL reference signal. The input clock mul-
`tiplying unit 6 frequency-multiplies the input clock and out-
`puts the resultant clock to the phase comparing unit 2 as an
`operation clock. The phase comparing Limit 2 operates accord
`ing to the operation clock received front the input clock mul-
`tiplying unit 6. The phase comparing unit 2 obtains the phase
`difference between the reference signal generated by the n
`dividing unit 1 and a comparison signal generated by fre-
`quency-dividing an output clock by m in the nt dividing unit
`4. and outputs a control signal so that the phase difference
`becomes zero. The oscillating unit 3 changes the output clock
`by the control signal received from the phase comparing unit
`2.
`
`55
`
`on
`
`Provided that the input clock frequency is x hertz and the
`output clock frequency is y hertz. the reference signal fre-
`quency is xr‘n hertz. Since the phase of the comparison signal
`
`6
`tracks the phase ofthe reference signal, the comparison signal
`frequency is also xfn hertz. The output clock frequency is
`therefore y=[xxm)t'n hertz. A desired output clock is thus
`obtained.
`
`As has been described above. according to the digital PLL
`device ofthe second embodiment ofthe present invention. the
`phase comparing unit 2 can be operated by using a frequency-
`uutltiplied input clock as an operatith clock. This structure
`suppresses increase in jitter and increase in tracking tinte
`caused by low-speed operation due to a low-speed transmit-
`ted clock. as compared to conventional digital PLL devices in
`which the phase comparing unit 2 is operated by using an
`input clock directly as an operation clock.
`Note that the input clock and the frequency dividing
`parameters In and it may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`
`cannot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. Examples ofsuch
`a digital interface includcaudio transmission ofllil-EF. 1394 or
`HDMI.
`
`Third Embodiment
`
`FIG. 3 is a block diagram showing a structure of a digital
`PLL device according to a third embodiment of the present
`invention.
`The digital PLL device according to the third embodiment
`of the present invention shown in FIG. 3 includes an n divid-
`ing unit 1. a phase comparing unit 2. an oscillating unit 3. an
`I‘I'l dividing unit 4. an input clock dividing unit 5. an input
`clock multiplying unit 6. an operation clock selecting unit '7,
`and a frequency detecting unit 8.
`As compared to the structures ofthe digital PL-I. devices of
`the first and second embodiments shown in FIGS. 1 and 2. the
`
`structure ofthe digital PLL device ofthe present embodiment
`is characterized by including the input clock dividing unit 5 of
`the first embodiment configured to frequency-divide an input
`clock and the input clock multiplying unit 6 of the second
`embodiment configured to frequency-multiply an input
`clock, and characterized by further including the operation
`clock selecting unit 7 configured to select
`the clock fre-
`quency-divided by theinpul clock dividing unit 5 or the clock
`frequency-multiplied by the input clock multiplying unit 6
`and output the selected clock as an operation clock. The
`digital PLL device of the third embodiment may further
`include the frequency detecting unit 8 configured to detect an
`input clock frequency and output the detection result to the
`operation clock selecting unit 7 so that the operation clock
`selecting unit 7 can select an optimal operation clock.
`The digital PLL device of the tltird emboditueut of the
`present invention therefore has the effects of'both the first and
`second embodiments described above. More specifically, as
`compared to conventional digital PLL devices in which the
`phase comparing unit 2 is operated by using an input clock
`directly as an operation clock. the digital PLL device of the
`third embodiment suppresses increase in circuit scale and
`increase in povvcr consumption caused by high-speed opera-
`tiott due to a high-speed transmitted clock and also suppresses
`increase in jitter and increase in tracking time caused by
`low-speed operation due to a low-speed transmitted clock.
`Moreover. since the digital PLL device of the third embodi-
`ment
`includes the frequency detecting unit 8. an optimal
`operation clock can be selected according to the operation
`speed. based on the input clock frequency. The digital PLL
`device of the third embodiment can therefore operate ratio-
`nally.
`
`

`

`US 7,948,290 132
`
`8
`The digital PLL device according to the fifth embodiment
`of the present invention shown in FIG. 5 includes an n divid-
`ing unit 1. a phase comparing unit 2. an oscillating ttnit 3, an
`In dividing unit 4. an input clock multiplying unit 6. and an
`output clock dividing unit .10. Note that. as compared to the
`structure of the digital PLL device of the fourth embodiment
`shown in FIG. 4. the stntcture ofthe digital PLL device ofthe
`present embodiment is characterized by including the input
`clock multiplying unit 6 configured to frequency-multiply an
`input clock instead of the input clock dividing unit 5 config-
`ured to frequency-divide an input clock in the fourth embodi-
`ment, and by including the output clock dividing unit
`I!)
`configured to frequency-divide a clock received front the
`oscillating unit 3 and output the resttltaut clock instead of the
`output clock multiplying unit 9 configured to frequency—mul-
`tiply a clock received from the oscillating tulit 3 in the fourth
`embodiment.
`
`ll]
`
`7
`the input clock and the frequency dividing
`Note that
`parameters m and 11 may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`camtot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. Examples ofsuch
`a digital interface include audio transmission of IEEE 1394 or
`HDMII.
`
`Fourth Embodiment
`
`FIG. 4 is a block diagram showing a structure ofa digital
`PLL device according to a fourth embodiment of the present
`invention.
`The digital PLL device according to the fourth embodi—
`ment of the present invention shown in FIG. 4 includes an n
`dividing unit 1. a phase comparing unit 2. an oscillating unit
`3. an m dividing unit 4. an input clock dividing unit 5. and an
`output clock multiplying unit 9.
`Operation ofthe digital PLL device of the present embodi-
`ment having the above structure will now be described.
`As shown in FIG. 4. the input clock dividing unit 5 frc-
`quencydivides an input clock transmitted through a dig'tal
`interface and outputs the resultant clock to the phase compar—
`ing unit 2 and also to the n dividing unit 1 as an operation
`clock. The n dividing ttnit 1 frequency-divides the clock
`received from the input clock dividing unit 5 by n to generate
`a digital PLL reference signal. The phase comparing unit 2
`operates according to the operation clock received from the
`input clock dividing unit 5. The phase comparing unit 2
`obtains the phase difference between the reference signal
`generated by the n dividing unit I and a comparison signal
`generated by frequency-dividing an output clock by m in the
`m dividing unit 4. and outputs a control signal so that the
`phase difference becomes zero. The oscillating ttnit 3 changes
`the output clock by the control signal received from the phase
`comparing unit 2. The output clock multiplying unit 9 fre-
`quency-multiplies the clock received from the oscillating unit
`3 and outputs the resultant clock.
`Provided that the input clock frequency is x hertz. the
`output clock ii'equeney is y hertz. and the frequency-dividing
`factor of the input clock dividing unit 5 is a. the reference
`signal frequency is xffaxn) hertz. Since the phase of the
`comparison signal tracks the phase ofthe reference signal. the
`comparison signal frequency is also xr'(axn) hertz. The output
`clock frequency of the oscillating unit 3 is therefore y'=(x><
`m)t(axn) hertz. A desired output clock is thus obtained by
`using the value a as a frequency-multiplying factor of the
`output clock multiplying unit 9.
`As has been described above. according to the digital PLL
`device of the fourth embodiment ofthe present invention. the
`phase comparing unit 2 can beoperated by using a frequency~
`divided input clock as an operation clock. This structure
`suppresses increase in circuit scale and increase in power
`consumption caused by high—speed operation due to a high-
`speed transmitted clock. as cotnpared to conventional digital
`PLL devices in which the phase comparing unit 2 is operated
`by using an input clock directly as an operation clock.
`Note that
`the input clock and the frequency dividing
`parameters in and u may be transmitted through a digital
`interface. This structure is effective in the case where a clock
`carutot be transmitted directly but a clock synchronized with
`a transmitting party needs to be generated. Examples of such
`a digital interface include audio transmission ofIEEE 1394 or
`l-IIJMl.
`
`21']
`
`I.) a:
`
`3ft
`
`35
`
`Operation ofthe digital PLL device of the present embodi-
`ment having the above structure will now be described.
`As shown in FIG. 5. the input clock multiplying unit 6
`frequency-multiplies an input clock transmitted through a
`digital interface and outputs the resultant clock to the phase
`comparing unit 2 and also to the n dividing unit 1 as an
`Operation clock. The n dividing 1qu l frequency-divides the
`cloek received from the input clock multiplying unit 6 by n to
`generate a digital PLL reference signal. The phase comparing
`unit 2 operates according to the operation clock received from
`the input clock multiplying tutit 6. The phase comparing unit
`2 obtains the phase difference between the reference signal
`generated by the n dividing unit 1 and a comparison signal
`generated by frequency-dividing an otttput clock by m in the
`m dividing unit 4. and outputs a control signal so that the
`phase difference becomes zero. The oscillating ttnit 3 changes
`the output clock by the control signal received from the phase
`comparing ttnit 2. The output clock dividing unit 10 fre-
`quency-divides the clock received from the oscillating unit 3
`and outputs the rcsultant clock.
`Provided that the input clock frequency is x hertz. the
`output clock frequency is y hertz. and the frequency—multi-
`plying factor of the input clock multiplying unit 6 is b. the
`reference signal frequency is (xxbtr‘n hertz. Since the phase of
`the comparison signal tracks the phase ofthe reference signal.
`the comparison signal frequency is also (xxby‘n hertz. The
`output clock frequency of the oscillating unit 3 is therefore
`y'=(x><b)<m)ln hertz. A desired output clock is thus obtained
`by using a frequency-dividing factor b in the output clock
`. dividing unit 10.
`As has been described above. according to the digital PLL
`device of the fifth embodiment of the present invention. the
`phase comparing unit 2 can be operated by using a frequency-
`rnultiplicd input clock as an operation clock. This structure
`suppresses increase in jitter and increase in tracking time
`caused by low-speed operation due to a low~speed t