UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
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`Petitioner
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`v.
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`AQUILA INNOVATIONS INC.
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`Patent Owner
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`PATENT OWNER’S PRELIMINARY RESPONSE
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`Case IPR2019-01526
`U.S. Patent No. 6,895,519
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
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`Petitioner
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`v.
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`AQUILA INNOVATIONS INC.
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`Patent Owner
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`PATENT OWNER’S PRELIMINARY RESPONSE
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`Case IPR2019-01526
`U.S. Patent No. 6,895,519
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`TABLE OF CONTENTS
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`Page
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`I.
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`II.
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`BACKGROUND ............................................................................................ 1
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`IT IS NOT NECESSARY TO CONSTRUE ANY CLAIM TERMS
`DETERMINATION THAT THE PREAMBLE OF CLAIM 1 IS
`LIMITING IS REQUIRED ............................................................................ 4
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`III. THE PETITION’S COMBINATION OF OBER AND NAKAZATO
`DOES NOT RENDER OBVIOUS ANY OF THE CHALLENGED
`CLAIMS ......................................................................................................... 7
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`1.
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`2.
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`3.
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`4.
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`5.
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`Ober ............................................................................................ 8
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`Nakazato ................................................................................... 10
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`The Petition Does Not Establish That Ober Discloses “A
`Plurality Of Ordinary Operation Modes.” ............................... 11
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`The Absence Of A “Plurality Of Ordinary Operation
`Modes” Impacts Several Other Limitations Of Claim 1 ......... 18
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`The Petition Does Not Establish That The Combination
`of Ober and Nakazato Discloses “A First Memory
`Storing A Clock Control Library For Controlling Clock
`Frequency Transitions Between Said Ordinary Operation
`Modes.” .................................................................................... 19
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`a.
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`b.
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`Nakazato and Ober Are Incompatible ........................... 22
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`The Petition Does Not Sufficiently Support Its
`Claimed Motivation To Combine Ober and
`Nakazato ........................................................................ 24
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`6.
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`The Petition Does Not Establish That Ober Discloses
`“Generates A Clock Supplied To Said Central Processing
`Unit.” ........................................................................................ 25
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`7.
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`8.
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`9.
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`The Petition Does Not Establish That Ober And
`Nakazato Render Obvious “Calling Of Said Clock
`Control Library And Changing Of Said Register Value
`Are Programmably Controlled By Said Application
`Program To Enable User Selectable Clock Frequency
`Transitions.” ............................................................................. 28
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`a.
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`b.
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`Nakazato’s Utility Does Not Control Its Driver ............ 28
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`The Petition Does Not Establish That Nakazato’s
`Utility Controls the Changing Of A Register Value ..... 29
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`Ober Does Not Disclose a “Second Special Mode.” ............... 30
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`Ober Teaches Away From A Combination With
`Nakazato ................................................................................... 32
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`IV. GROUND 2 .................................................................................................. 35
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`A.
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`The Petition Does Not Establish That Exhibit 1005 Is A Printed
`Publication .......................................................................................... 35
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`V. GROUND 3 .................................................................................................. 38
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`VI. THE BOARD LACKS AUTHORITY TO RULE ON THE
`PATENTABILITY OF THE CHALLENGED CLAIMS OF THE
`’526 PATENT ............................................................................................... 38
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`VII. CONCLUSION ........................................................................................................... 40
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`-ii-
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`TABLE OF AUTHORITIES
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` Page(s)
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`Federal Cases
`Arthrex, Inc. v. Smith & Nephew, Inc.,
`2019 U.S. App. LEXIS 32613 (Fed. Cir. Oct. 31, 2019) ................................... 39
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`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) .......................................................................... 5, 6
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`In re Cronyn,
`890 F.2d 1158 (Fed. Cir. 1989) .......................................................................... 37
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`Edmond v. United States,
`520 U.S. 651 (1997) ............................................................................................ 39
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`Free Enter. Fund v. Pub. Co. Accounting Oversight Bd.,
`561 U.S. 477 (2010) ...................................................................................... 38, 39
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`Freytag v. Commissioner,
`501 U.S. 868 (1991) ............................................................................................ 39
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`In re Gurley,
`27 F.3d 551 (Fed. Cir. 1994) .............................................................................. 33
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`Harmonic Inc. v. Avid Tech., Inc.,
`815 F.3d 1356 (Fed. Cir. 2016) .......................................................................... 30
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`Hulu, LLC v. Sound View Innovations, Inc.,
`IPR2018-01039, Paper No. 29 (PTAB Dec. 20, 2019) ...................................... 36
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`Infineon Techs. AG et al. v. Atmel Corp.,
`No. 11-307-RGA, Dkt No. 174 (D. Del. Dec. 4, 2012) ....................................... 8
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`Kyocera Wireless Corp. v. Int’l Trade Comm’n,
`545 F.3d 1340 (Fed. Cir. 2008) .......................................................................... 36
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`Lucia v. SEC,
`138 S. Ct. 2044 (2018) .................................................................................. 38, 39
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`Masias v. Sec’y of HHS,
`634 F.3d 1283 (Fed. Cir. 2011) .................................................................... 38, 39
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`-iii-
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`SRI Int’l, Inc. v. Internet Sec. Sys., Inc.,
`511 F.3d 1186 (Fed. Cir. 2008) .................................................................... 36, 37
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`TQ Delta, LLC v. Cisco Sys.,
`942 F.3d 1352 (Fed. Cir. 2019) .......................................................................... 24
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`Wellman, Inc. v. Eastman Chem. Co.,
`642 F.3d 1355 (Fed. Cir. 2011) ............................................................................ 4
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`Federal Statutes
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`35 U.S.C. § 102 ........................................................................................................ 36
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`35 U.S.C. § 313 .......................................................................................................... 1
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`Regulations
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`37 C.F.R. § 42.104(b)(4) .......................................................................................... 26
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`37 C.F.R. § 42.104 ............................................................................................. 26, 29
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`37 C.F.R. § 42.104(b) .............................................................................................. 22
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`37 C.F.R. § 42.104(b)(3) .......................................................................................... 26
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`37 C.F.R. § 42.107 ..................................................................................................... 1
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`-iv-
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`PATENT OWNER’S EXHIBIT LIST
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`2002
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`Exhibit No. Description
`2001
`Joint Claim Construction Statement dated May 17, 2019
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`Revised Joint Claim Construction Statement dated November 1,
`2019
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`Markman Order re Infineon Technologies AG and Infineon
`Technology North America Corp. v. Atmel Corporation
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`2003
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`-v-
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`Pursuant to 35 U.S.C. § 313, 37 C.F.R. § 42.107 and the Notice of Filing
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`Date Accorded to Petition, Paper No. 4, and Errata, Paper No. 5, Patent Owner
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`Aquila Innovations Inc. (“Aquila”) timely submits this preliminary response and
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`respectfully requests that the Board deny the petition for inter partes review
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`against U.S. Patent No. 6,895,519 (the “’519 patent”) submitted by Petitioner
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`Advanced Micro Devices, Inc. (“Petitioner”).
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`The Petition does not establish that the Petitioner is reasonably likely to
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`prevail against any claim of the ’519 patent. The asserted combination of U.S.
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`Patent No. 6,665,802 to Ober (“Ober”) and U.S. Patent 6,681,331 to Nakazato
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`(“Nakazato”) is insufficiently supported and does not teach or suggest multiple
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`limitations of claim 1. The rest of the Petition falls with the challenge to claim 1
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`because the Petition depends upon the same combination of Ober and Nakazato for
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`all of the remaining claims, all of which depend from claim 1.
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`I.
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`BACKGROUND.
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`The ’519 patent is titled “System LSI,” and relates generally to the dynamic
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`control of a clock supplied to a central processing unit. The claimed system LSI
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`has a plurality of ordinary operation modes and a plurality of special modes. Claim
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`1 is duplicated below for reference:
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`A system LSI having a plurality of ordinary operation
`modes and a plurality of special modes in response to
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`clock frequencies supplied to a central processing unit,
`comprising:
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`a first memory that stores a clock control library
`for controlling a clock
`frequency
`transition
`between said ordinary operation modes;
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`a system control circuit which has a register,
`wherein said system control circuit carries out the
`clock frequency transition between said ordinary
`operation modes and said special modes
`in
`response to a change of a value in said register,
`and also carries out the clock frequency transition
`among said ordinary operation modes in response
`to said clock control library;
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`a clock generation circuit that receives a plurality
`of standard clocks, wherein said clock generation
`circuit generates a clock supplied to said central
`processing unit according to control by said system
`control circuit; and
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`a second memory that stores an application
`program, wherein calling of said clock control
`library and changing of said register value are
`programmably controlled by said application
`program to enable user selectable clock frequency
`transitions,
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`-2-
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`wherein said special modes comprise a first special
`mode
`in which clock supply
`to principal
`constituents of said central processing unit is
`halted, a second special mode in which clock
`supply to an entirety of said central processing unit
`is halted, and a third special mode in which supply
`of power to the entirety of said central processing
`unit is halted.
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`Claim 1 is the only independent claim in the ’519 patent. Claims 2 – 11 are
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`dependent claims of claim 1.
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`The inventor of the ’519 patent noted that conventional chips, such as ST7
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`or ARM cores, only operated on bi-modal (high speed and low speed) operation
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`modes. Bi-modal operation modes were inadequate because they did not allow for
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`the dynamic and speedy control of the CPU clocks. Ex. 1001 at 2:61-67; Fig. 10.
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`To solve this problem, the ’519 patent teaches “clock gears,” analogous to gears in
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`a vehicle, controlled by a clock control library stored in memory. Id. at 4:12-18;
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`4:38-44. The clock control library controls the frequency transitions between
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`“ordinary operation modes,” such as highest speed, high speed, low speed and
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`lowest speed. Similar to a transmission in a vehicle, the ’519 patent discloses that
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`the clock control library can control the “clock gear” shifts between the operation
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`modes:
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`-3-
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`Ex. 1001 at Fig. 5.
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`II.
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`IT IS NOT NECESSARY TO CONSTRUE ANY CLAIM TERMS
`DETERMINATION THAT THE PREAMBLE OF CLAIM 1 IS
`LIMITING IS REQUIRED.
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`Petitioner identifies three terms for construction: “system LSI,” “a clock
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`control library for storing clock frequency transitions between said ordinary
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`operation modes,” and “principal constituents of said central processing unit.” The
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`Petition does not turn on the construction of these terms and it is not necessary to
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`construe any of them at this juncture. See Wellman, Inc. v. Eastman Chem. Co.,
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`642 F.3d 1355, 1361 (Fed. Cir. 2011) (explaining “claim terms need only be
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`construed ‘to the extent necessary to resolve the controversy’”) (quoting Vivid
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`-4-
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`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)). It is
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`necessary, however, to determine whether the preamble of claim 1 is limiting.
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`The preamble recites “[a] System LSI having a plurality of ordinary
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`operation modes and a plurality of special modes in response to clock frequencies
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`supplied to a central processing unit.” Petitioner has not stated whether the
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`preamble is limiting. See Petition at 25 (“To the extent the preamble is determined
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`as limiting …”), but it did find the term sufficiently important that it proposed a
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`construction. There is no reason to propose a construction for “system LSI” if
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`“system LSI” in not part of the claim. Petitioner should not be able to propose a
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`construction for a term that only appears in the preamble, advocate for that
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`construction, only to hedge its bets by stating that the construction applies only “to
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`the extent” the preamble is limiting. Moreover, in district court, where the same
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`parties have been litigating for over a year, Petitioner agrees that the preamble is
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`limiting, and it has not presented any reason why it should be allowed to depart
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`from that position before this tribunal. See Ex. 2001 at 1; Ex. 2002 at 2.
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`The preamble is limiting because it recites an essential element of the
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`invention, the “system LSI.” See Bicon, Inc. v. Straumann Co., 441 F.3d 945, 952
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`(Fed. Cir. 2006) (“[T]he preamble is regarded as limiting if it recites essential
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`structure that is important to the invention or necessary to give meaning to the
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`claim… if the claim drafter ‘chooses to use both the preamble and the body to
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`-5-
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`define the subject matter of the claimed invention, the invention so defined, and
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`not some other, is the one the patent protects.’”) (internal citations omitted). The
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`invention claimed in claim 1 is not complete without the term “system LSI,” nor is
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`the remainder of the preamble. Without the term “system LSI,” it is not clear that
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`the structural limitations mentioned in claim 1 reside on a chip, which is a critical
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`feature of the ’519 patent. Even Petitioner’s proposed a construction requires a
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`chip.
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`In addition to reciting necessary structure, the preamble also provides the
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`antecedent basis for the “ordinary operation modes,” “special modes,” and “central
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`processing unit,” each of which is recited in the body of claim 1. “When the
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`limitations in the body of the claim rely upon and derive antecedent basis from the
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`preamble, then the preamble may act as a necessary component of the claimed
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`invention.” Bicon, 441 F.3d at 952 (internal citations and quotations omitted).
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`Here, the preamble is a necessary component of the claimed invention and the
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`preamble of claim 1 of the ’519 patent should be construed as limiting.
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`-6-
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`III. THE PETITION’S COMBINATION OF OBER AND NAKAZATO
`DOES NOT RENDER OBVIOUS ANY OF THE CHALLENGED
`CLAIMS.
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`Ground 1 of the Petition challenges claims 1, 7, 10, and 11 of the ’519 patent
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`over Ober in view of Nakazato.1 The Petition asserts that a person of ordinary skill
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`in the art would have been motivated to combine Ober’s power management
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`microcontroller with Nakazato’s clock driver to arrive at the invention claimed in
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`claim 1 of the ’519 patent. But Ober does not disclose the “plurality of ordinary
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`operation modes” recited in the preamble of claim 1 or the second “special mode”
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`recited in the last limitation of claim 1. The combination of Ober and Nakazato
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`also does not disclose “a first memory storing a clock control library for
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`controlling a clock frequency transition between said ordinary operation modes”
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`because Ober teaches only one operational mode, not the required plurality of
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`“ordinary operation modes.” The Petition also does not establish that Ober teaches
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`or suggests “generating a clock supplied to the central processing unit,” or “calling
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`of said clock control library and changing of said register value are programmably
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`controlled by said application program.” The Petition, therefore, does not establish
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`that Petitioner is reasonably likely to prevail as to claim 1 of the ’519 patent.
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`1 As noted above, the Petition also relies upon this combination for all of the
`dependent claims challenged in the other Grounds.
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`-7-
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`1. Ober.
`Ober is titled “Power Management And Control For A Microcontroller” and
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`relates generally to power management in a microcontroller. Ober’s stated concern
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`is providing power management to each of the peripheral subsystems in the
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`microcontroller, not the central processing unit core. Ex. 1004, Col. 1:25-40. Ober
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`explains that prior attempts to minimize the power consumed by microcontrollers
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`involved reducing the speed or stopping the clock supplied to the central
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`processing unit. Id. at 2:16-20. Ober criticizes such an approach because
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`controlling the power consumption of a microcontroller centrally at the central
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`processing unit fails to optimize the power consumption of the peripheral
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`subsystems and results in complicated and costly designs. Id. at 2:21-40. Because
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`“power management of a particular peripheral for a computer system may be best
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`optimized at the peripheral device itself,” Ober’s objective was to “provide a
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`power management system for a microcontroller which enables the microcontroller
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`subsystems to be independently controlled.” Id. at 2:45-48. See also Ex. 2003,
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`Infineon Techs. AG et al. v. Atmel Corp., No. 11-307-RGA, Dkt No. 174 at * 3-4
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`(D. Del. Dec. 4, 2012) (district order construing Ober and finding Ober’s goal is
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`“decentralized and independent power management for peripheral units,” not the
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`CPU core). Ober accomplishes this goal by independently controlling either the
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`frequency of the clock or the power supplied to the peripheral systems.
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`-8-
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`Ober discloses a microcontroller architecture that allows the power level of
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`each of the peripheral subsystems to be controlled independently of the CPU.
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`Ex. 1004, Fig. 1. For example, Ober discloses Flexible Peripheral Interface (“FPI”)
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`devices 42-52 that connect each of the peripherals 30-40 to management system 26
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`and CPU 22 through the FPI bus 24. Each of the FPI devices has a special function
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`register (“SFR”) that “control[s] the response of each subsystem 30-40 during the
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`different power modes of operation.” Ex. 1004 at 9:21-25. The distribution of the
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`SFRs to each peripheral “allow[s] the operating system to control each of the
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`subsystems independently.” Id. at 9:49-51.
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`-9-
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`The management system 26 contains a power manager that controls the
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`power modes of the CPU core and the peripheral subsystems. Id. at 5:37-40. Ober
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`discloses three main power modes – RUN, IDLE, and SLEEP. SLEEP mode has
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`further “submodes,” such as SLEEP (Clocks Not Distributed) and DEEP SLEEP.
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`The core CPU is fully operational in RUN mode, but is stopped in IDLE and
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`SLEEP mode, including the SLEEP submodes. The core CPU may be powered off
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`in SLEEP mode. In addition, in SLEEP mode, the system clock provided to the
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`peripheral devices may be divided by 2, 4, or 128. This means that the power level
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`to the peripherals may vary. But in RUN mode, the only mode in which the CPU
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`core is operational, the system clock operates on a single, fixed frequency that
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`cannot be selected or altered. Id. at 17:15-27. Thus, the core CPU does not operate
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`in more than one power mode. This is fatal to the Petition.
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`Nakazato.
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`2.
`The Petition relies on Nakazato for its purported teaching of “‘a clock
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`control library’ and an ‘application’ for controlling CPU frequency.” Petition at 8.
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`Nakazato relates generally to power savings in computer systems, such as a
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`personal computer. Ex. 1008 at 1:20-24; 4:1-5:52 (describing “battery-operable
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`notebook type personal computer (PC)” in accordance with disclosed
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`embodiments). Nakazato discloses a “set it and forget it” system wherein the user
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`may select a designated CPU frequency through the system firmware (BIOS) at
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`-10-
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`startup. The system maintains this speed until shutdown or reset, and then returns
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`the CPU to the highest speed. See Ex. 1008 at Abstract. Nakazato teaches that this
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`is accomplished through a “power-saving driver” working in concert with a power-
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`saving utility in the BIOS that presents a graphical user interface (“GUI”) to the
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`user. See Ex. 1008, Fig. 2. The power-saving utility saves the selected frequency in
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`storage for later reference by the power-saving driver. Nakazato does not disclose
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`on-demand clock frequency transitions during operation, as the Petition asserts.
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`3.
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`The Petition Does Not Establish That Ober Discloses “A
`Plurality Of Ordinary Operation Modes.”
`
`The preamble of claim 1 recites “a System LSI having a plurality of ordinary
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`operation modes and a plurality of special modes in response to clock frequencies
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`supplied to a central processing unit.” The Petition asserts that Ober alone
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`discloses all of the elements of the preamble. Petition at 25 (“Ober alone teaches or
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`suggests the preamble.”). Ober does not teach or suggest the “plurality of ordinary
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`operation modes” of claim1’s preamble.
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`“Ordinary operation mode” plainly requires “operation.” The ’519 patent
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`teaches that the ordinary operation modes are achieved by varying the frequency of
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`the clock signal used by the CPU during operations, FCLK.
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`In case of the CPU 510, the clock FCLK for use in the
`core CPU and others could be set in detail in the register
`group inside the system control circuit 534 as shown in
`FIG. 3. The function capable of dynamically and speedily
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`-11-
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`
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`controlling the clock group like this will be called “Clock
`Gear” hereinafter in the present specification.
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`Ex. 1001 at 8:56-65. The ’519 patent compares the various speeds of the CPU’s
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`frequency in the various ordinary operation modes to shifting gears in an
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`automobile:
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`This has been done for the purpose of the invention,
`which is to dynamically and quickly control the clock
`with a lot of frequencies covering the wide range of the
`operation modes from the high-speed operation mode to
`the low-speed operation mode based on the concept we
`call the clock gear.
`
`Ex. 1001 at 11:34-38.
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`-12-
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`
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`Ex. 1001 at Fig. 5. The revolutions of an engine may be compared to the pulses of
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`a clock signal because they are both periodic. The revolutions per minute (“RPM”)
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`and the frequency (measured in various magnitudes of hertz, or Hz) are both
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`measures of the rates of revolutions or pulses. In a car, shifting gears while the car
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`is moving will change the engine’s RPM at a given speed. For example, at 40
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`MPH, an automobile engine may “rev” at 6500 RPM in first gear, 4500 RPM in
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`second gear, and 3500 RPM in third gear. This is consistent with the ’519 patent’s
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`teaching of various ordinary operation modes seen in Figure 5. The ’519 patent
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`explicitly compares changing from high speed operation mode to a lower speed
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`operation mode to a “gear up,” and conversely, the transition from a lower speed
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`-13-
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`
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`operation mode to a higher speed operation mode to a “gear down.” Ex. 1001 at
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`12:37-45; see also Id. at 4:12-18; 13:54-60 (comparing clock state transitions to
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`“gear-change operation[s]”).
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`Unlike the’519 patent, Ober’s CPU is only operational in one mode: RUN.
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`In IDLE and the various SLEEP submodes, the Ober CPU is not operational. See
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`Ex. 1004, Tables 8 and 9. In the parlance of the automobile analogy, Ober is a
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`single-speed vehicle that only has one gear – RUN.
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`Ober explicitly defines its sole operational mode, RUN, to operate on a fixed
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`clock frequency that cannot be selected or reduced. Low Speed Clocks are not
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`available in the RUN mode.
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`
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`Ex. 1004 at 17:15-26. Similarly, Ober discloses that the CPU enters the IDLE
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`mode “when no outstanding actions are pending.” Id. at 13:55-57. The CPU clears
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`its pipelines and halts in IDLE mode, and is thus not operational. Id. at 15:24-27.
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`Finally, the core CPU is idle when Ober’s system is in SLEEP mode. If the core
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`CPU is idle, it is not operational in the SLEEP mode. Id. at 13:61.
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`-14-
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`
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`The Petition argues that Ober teaches or suggests “a plurality of ordinary
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`operation modes” through “adjusting the frequency of [its] CPU by changing the
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`value in a register.” See, e.g., Petition at 7, 18, 32. Petitioner, however, admits that
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`“Ober does not disclose how and under what conditions its CPU clock frequency
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`would be adjusted.” Petition at 28. Of course not. The CPU clock is not adjusted.
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`Variance in clock frequency occurs only in SLEEP mode, not RUN mode.
`
`“SLEEP” mode is not an “ordinary operation mode.” In fact, Petitioner contends
`
`the SLEEP mode corresponds to the “second special mode.” The “second special
`
`mode” is not an “ordinary operation” mode because ordinary operation modes
`
`cannot be special modes. Petitioner similarly contends that the “DEEP SLEEP”
`
`mode corresponds to the “third special mode.” The “third special mode” is not an
`
`“ordinary operation” mode.
`
`The Petition attempts to overcome Ober’s shortcomings by arguing that
`
`Ober’s CPU clock executes at various frequencies corresponding to the amount of
`
`division in the clock. Petition at 24. Ober’s CPU cannot run on lower frequency
`
`clocks because Ober explicitly defines RUN mode to preclude the use of low speed
`
`clocks. Ex. 1004 at 17:15-26 (“Low Speed Clocks = False”).
`
`The Petition also unconvincingly cites to column 8, lines 58 to 64 to
`
`establish that the Ober system operates on various frequencies. But that passage
`
`-15-
`
`
`
`
`
`only describes how the system clock is generated. It does not support the assertion
`
`that the system runs on various frequencies.
`
`The main crystal 84 (FIG. 2), for example, 15 MHz,
`depending on the clock speed of the CPU core 22, is
`connected to the system oscillator 104 to generate an
`oscillation frequency of 150 MHz. The PLL 106 locks in
`the oscillation frequency, while the clock circuit 108
`divides the oscillation frequency to provide the system
`clock frequency, for example 75 MHz.
`
`Ex. 1004 at 8:58-64. The Petition does not mention that Ober’s division of the
`
`system clock by 2, 4, or 128 occurs only during SLEEP mode when the CPU core
`
`clock is disabled. Ex. 1004 at 13:55; 14:62. The clock that is distributed during
`
`SLEEP mode is distributed only to the peripheral subsystems, not the CPU. Id. at
`
`13:61-64 (“In [SLEEP (distributed clock)] mode, the [] clock is distributed to the
`
`subsystems which have been preconfigured to operate in the SLEEP mode.”). Even
`
`then, the frequency supplied to the peripherals is preconfigured “by the operating
`
`system or application program prior to this state being entered.” See also Ex. 1004
`
`at 13:60; 14:45-53. In other words, while in RUN (ordinary) mode, the CPU may
`
`trigger a transition to SLEEP (special) mode, by setting the ReqSlp bits (bits 1:0 of
`
`the SFR register 116) to Sleep Request, and the SlpClk bits of the SFR register 116
`
`(26:24) to set the frequency of the system clock while in SLEEP, i.e. after the
`
`-16-
`
`
`
`
`
`transition is complete. See Table 5. Table 5 of Ober is clear that the division of the
`
`system clock by 2, 4, and 128 is limited to the SLEEP mode:
`
`
`
`Ex. 1004 at Table 5 (highlighting in exhibit).
`
`Finally, the Petitioner’s allegation that “Ober explains that its system can
`
`supply a divided clock signal during ‘normal operating mode,’” Petition at 24-25,
`
`does not support its assertion that Ober discloses a plurality of ordinary operation
`
`modes. The divided clock signal provided during normal operation mode is simply
`
`the system clock provided to the subsystems during RUN mode, which Ober
`
`explains is a signal generated by clock circuit 108 through the division of the
`
`frequency generated by the system oscillator. Ex. 1004 at 8:58-64. The Petition
`
`incorrectly conflates the preconfigured low speed frequency clocks provided only
`
`to the peripherals during SLEEP (during which the core is idle and not receiving
`
`the System Clock), Ex. 1004 at 13:61-64; Table 5, with the fixed frequency clock
`
`provided to the core and peripherals during RUN. As shown in the charts of
`
`columns 17 and 18, the state variable Low Speed Clocks is always “False” during
`
`-17-
`
`
`
`
`
`RUN mode, Ex. 1004 at 17:15-26 (“Low Speed Clocks = FALSE”), and
`
`conditionally “True” in SLEEP mode. Ex. 1004 at 18:13. Ober’s RUN mode uses
`
`only a single frequency. RUN mode is explicitly defined to be mutually exclusive
`
`with the low speed divided clocks.
`
`4.
`
`The Absence Of A “Plurality Of Ordinary Operation
`Modes” Impacts Several Other Limitations Of Claim 1.
`
`Because it does not disclose the “plurality of ordinary operation modes,”
`
`Ober also does not disclose several other limitations of claim 1. Even when
`
`combined with Nakazato, the combination does not disclose any limitation that
`
`requires clock frequency transitions between ordinary operation modes:
`
` a first memory that stores a clock control library for controlling a clock
`
`frequency transition between said ordinary operation modes;
`
` a system control circuit which has a register, wherein said system control
`
`circuit carries out the clock frequency transition between said ordinary
`
`operation modes and said special modes in response to a change of a value
`
`in said register, and also carries out the clock frequency transition among
`
`said ordinary operation modes in response to said clock control library;
`
`Ex. 1001, claim 1.
`
`-18-
`
`
`
`
`
`5.
`
`The Petition Does Not Establish That The Combination of
`Ober and Nakazato Discloses “A First Memory Storing A
`Clock Control Library For Controlling Clock Frequency
`Transitions Between Said Ordinary Operation Modes.”
`
`Petitioner argues that a person of ordinary skill would have been motivated
`
`to install Nakazato’s drivers and utility into Ober’s memory banks to be executed
`
`by Ober’s system, and thus seeks to overcome the failure of Ober to disclose “a
`
`first memory storing a clock control library for controlling clock frequency
`
`transitions between said ordinary operation modes.”
`
`As discussed in section III.2, Ober does not disclose “a plurality of ordinary
`
`operation modes.” Nakazato’s drivers and utilities thus would not “control clock
`
`frequency transitions between said ordinary operation modes” when installed on
`
`Ober’s system.
`
`The Petition asserts that a person of skill in the art would be motivated to use
`
`Nakazato’s drivers and utilities to change a value in a register to allow the CPU to
`
`run on lower clock frequencies. This argument improperly ignores Ober’s teaching
`
`that the low speed clocks are only distributed when the core CPU is stopped. Ober
`
`defines the RUN mode to require the state variable “Low Speed Clocks” to be
`
`“False,” precluding any state in which the CPU is powered on and running on low
`
`speed clocks.
`
`-19-
`
`
`
`
`
`
`
`The Petition attempts to mask this shortcoming by mischaracterizing Ober’s
`
`teachings: “Ober confirms that by adjusting [the bits of register 62 (“SLPCLK”)],
`
`the speed of the CPU is changed.” Petition at 27. See also Petition at 31 (“Ober
`
`only requires the change of a register to adjust CPU clock frequency.”). Ober
`
`teaches that “[a] sleep clock signal SLPCLK is used to program the frequency of
`
`the system clock during a sleep mode of operation.” Ex. 1004 at 11:31-33
`
`(emphasis added). Adjusting the SLPCLK bits of the register 62 does not adjust the
`
`speed of the CPU because the CPU is turned off during SLEEP mode. Ex. 1004 at
`
`13:55 (“The CPU core clock is disabled” in IDLE mode); 13:61 (“The CPU core,
`
`is IDLE” in SLEEP mode). Each of the possible values for the SLPCLK bits
`
`corresponds to a different frequency “during Sleep.” See Ex. 1004 at 11:1-13:
`
`-20-
`
`
`
`
`
`
`
`Ober also teaches that setting the SLPCLK bits is only possible when the CPU is in
`
`RUN mode. Ex. 1004 at 5:31-37 (“The CPU code 22 is coupled to …a multiplexed
`
`address/data FPI bus … to enable the operating system or application program to
`
`read and write the SFR register in the power management state machine as well as
`
`the SFRs in each of the FPI peripheral interfaces for each of the subsystems.”).
`
`Setting the SLPCLK bits determines the frequency of the system clock during the
`
`next SLEEP cycle, when the core CPU is idle, and does not change the frequency
`
`of the system clock during RUN mode. Ex. 1004 at 13:66; 14:48-50 (“Exact state
`
`of all the subsystems [during SLEEP (distributed clock) mode] in the device is
`
`configured by the operating system or application program prio
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