Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 1 of 11 PageID #: 6716
`
`AQUILA - Ex. 2003
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 2 of 11 PageID #: 6717
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 2 of 11 PagelD #: 6717
`
`b. The term "said comparator being in operation at a supply voltage above the
`
`second limit value" is construed to mean “said comparator is turned on at a supply
`
`voltage above the second iimit value, and is turned off at a supply voltage below the
`
`second limit value.” See col.4 1.62 - col.5 1.4; col.3 11. 36-43.
`
`c. The term "the oscillator being in Operation at a supply voltage above the
`
`second limit value" is construed to mean “the oscillator is turned on at a supply voltage
`
`above the second limit value, and is turned off at a supply voltage below the second limit
`
`value.” See col.3 11. 17-19; col.3 11.48-50; col.4 “5-7, 47-53; col.5 11.14-21.
`
`2. The term “activation signal” is construed to mean ”a signal, other than the reset signal,
`
`that turns on or resumes Operation of the processor unit.“ The intrinsic evidence provide sthat the
`
`processor unit “is not activated until the activation signal As appears,” to the exclusion of the
`
`reset signal Rs. Col.3 11.50—51; Fig.1.
`
`II. US. Patent No. 6,076,159
`
`1. The term “loop instructions” is construed to mean “a statement or expression
`
`consisting of an operation and its operands (if any), which can be interpreted by a computer in
`
`order to perform a loop function or operation.” There is no intrinsic evidence to support limiting
`
`this term to conditional jump instructions, which the patent distinguishes from loops. See col.7
`
`11.5.8.
`
`2. The term "a second pipeline for executing loop instructions" is construed to mean "a
`
`pipeline that only executes loop instructions.“ The claimed architecture requires a dedicated
`
`pipeline for 100p instructions. Col.2 1.67 - col.3 1.2; D]. 164 at 22, 28 (Off. Action dtd. July 12,
`
`1999 at 3; Resp. dtd. Oct. 8, 1999 at 5). Where there is one “main” pipeline as in Claim 5, the
`
`
`
`ammo-w-*4wWW—vmflmWWhfimw‘F-WW’W‘"W“WW1mm
`
`
`
`
`
`
`
`WWI-”Wm‘memwm-wlrmnr
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 3 of 11 PageID #: 6718
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 3 of 11 PagelD #: 6718
`
`dedicated pipeline is the “second pipeline,” and where there are two “main” pipelines, the
`
`dedicated pipeline is the “third pipeline.” E. g, Fig.3; col.2 1.67 - col.3 1.2.
`
`III. US. Patent No. 6,653,963
`
`1. The terms "in a channel-specific way as a function of a signal channel which is to be
`
`converted," "in a channel-specific way as a function of the signal channel to be converted," and
`
`“in a channel specific way .
`
`.
`
`. as a function of the signal channel to be converted" are given their
`
`plain and ordinary meaning. Atmel’s proposed construction does not limit or clarify the terms.
`
`2. The term "assigning certain settings for the operating parameters of the ND converter
`
`arrangement which are to be set, to individual requesting means" is given its plain and ordinary
`
`meaning. Atmel draws its proposed limitations from claim 18. (D.I. 154 at 35). Because these
`
`limitations are already explicitly claimed in independent claim 18, there is no reason to import
`
`them into this claim term, which appears in independent claim 1 and its dependent claims.
`
`3. The term “setting the operating parameters of the ND converter arrangement which
`
`are to be set, in agreement with the settings assigned to said requesting means making a request”
`
`is given its plain and ordinary meaning. Atmel‘s proposed limitation is not supported by the
`
`specification and does not clarify the term.
`
`1V. US. Patent No. 6,665,802
`
`1. The term “bus interface” is construed to mean “a bus interface that includes a software
`
`configuration register.” “Bus interface” has a plain and ordinary meaning. The intrinsic
`
`evidence indicates that to accomplish the goal of the invention (decentralized and independent
`
`power management for peripheral units), each peripheral unit’s bus interface (“FPI”) includes a
`
`software configuration register.
`
`‘802 Patent at [57]; col.2 1.62-col.3 1.6. Claim 7 includes the
`
`
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 4 of 11 PageID #: 6719
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 4 of 11 PagelD #: 6719
`
`additional element that each register “allow[s] a corresponding peripheral device to respond
`
`independently to the power management controls." Claim 5 already requires that the peripherals
`
`receive “power management controls” through their bus interface, so it is not proper to limit the
`
`term “bus interface” to require “storing power modes" as Atmel suggests.
`
`2. The term “each peripheral device including a bus interface” is construed to mean
`
`"each peripheral device has its own bus interface." To accomplish the goal of the invention
`
`(decentralized and independent power management for peripheral units), each peripheral unit has
`
`its own bus interface. Fig.1; c012, 11.62-65; 001.3, 11.1-6; D.I. 164 at 76-77, 83—85 (Resp. dtd.
`
`June 19, 2003 at 9-10, 16-18).
`
`3. The term "individually configuring a response of each of the one or more subsystems
`
`to the global power management command through a corresponding register in each of the one or
`
`more subsystems" is construed to mean "each subsystem is separately configured to respond to
`
`the global power management command through its own separate register." To accomplish the
`
`goal of the invention (decentralized and independent power management for peripheral units),
`
`each peripheral unit has its own bus interface (“FPI”) that includes a software configuration
`
`register.
`
`‘802 Patent at [5?]; Fig.1; col.2, 11.62—65; 001.3, 11.1-6; D1. 164 at T637, 33-85 (Resp.
`
`dtd. June 19, 2003 at 9—10, 16-18). V. U.S. Patent No. 6,769,065
`
`1. The term “access authorization monitoring device" (“AAMD”) is construed to mean "a
`
`security device that monitors and prevents any attempted access by a debugger device to
`
`protected on-chip components, unless the debugger device has verified authority.” The AAMD
`
`monitors for verified authority; neither the AAMD nor the debugger must verify or generate that
`
`
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 5 of 11 PageID #: 6720
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 5 of 11 PagelD #: 6720
`
`authority, and other appliances can produce the authority. Col.4 11.1-7, 55-57. “Permission” is
`
`too broad; the patent discloses the additional concept of verification. D.I. 171 at 14; col.4 11.1-7.
`
`2. The term “verified authorization” is construed to mean “access permitted only to
`
`authorized holders of a debugging device or other appliance but not to others.” The intrinsic
`
`evidence provides that authorization verification can be produced by “the debugger or other
`
`appliance” and authorizes holders of those devices to access the claimed programmable unit.
`
`Col.4 11.55-57.
`
`VI. U.S. Patent No. 6,788,235
`
`1. The term "synchronizing the analog-to—digital converter with at least one other
`
`analog-to-digital converter of the plurality of analog-to-digital converters" is construed to mean
`
`"using a bidirectional procedure to cause the analog-to-digital converter to start simultaneously
`
`with at least one other analog-to-digital converter of the plurality of analog-to-digital converters."
`
`The intrinsic evidence indicates that synchronizing is performed bidirectionally, with a preferred
`
`embodiment via handshaking. C015 11.13—19; D.1. 165 at 20 (Resp. dtd. July 30, 2002 at 3).
`
`During prosecution, the applicant disclaimed an unidirectional prooedure to overcome prior art.
`
`(D.I. 165 at 20). While the patent discloses analog-to-digital conversions implemented
`
`“absolutely simultaneously or time-synchronously,” or with “minimal time offset,” during
`
`prosecution synchronization was narrowed to modes with “an element of signaling at the
`
`beginning or at an impending beginning of an analog—to-digital conversion.” D.I. 165 at 10-11,
`
`21 (Resp. dtd. Feb. 1, 2002 at 4; Resp. dtd. July 30, 2002 at 4); see 001.3 11.20-24; col.5 11.13-19.
`
`Describing the conversions as “simultaneous” encompasses this element.
`
`
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 6 of 11 PageID #: 6721
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 6 of 11 PagelD #: 6721
`
`VII. US. Patent No. 7,000,148
`
`I. The term “peripheral units” is construed to mean "No or more on-chip units external
`
`to the CPU that can be used for non—debugging functions." No party objects to the language “two
`
`or more on-chip units external to the CPU.” (D1. 171 at 33). The patent’s goal is to perform
`
`debugging through peripheral units “that are provided in any case” and have functions other than
`
`debugging, therefore saving space on the chip that otherwise would be dedicated to debugging.
`
`C012 l.65-col.3 1.3; col.4,ll.21-26; col.6 11.28-41.
`
`2. The patent claims items “connected to” each other differently from items “connected
`
`to” each other “through" another item. Those two phrases must have different meanings. See
`
`Exxon Chem. Patents, Inc. v. .Laubrizoir Corp, 64 F.3d 1553, 1557 (Fed. Cir. 1995). Infineon‘s
`
`proposal, that all items connected to another item be “linked or capable of communicating,” fails
`
`to distinguish from the two claim types, and is meaningless in the context of a microcontroller on
`
`which nearly every component is “linked” or “capable of communicating” with nearly every
`
`other component. Accordingly:
`
`a. The term “peripheral units connected to said first internal bus” is construed to
`
`mean “peripheral units interfacing directly with the first internal bus.”
`
`b. The term “being transmitted through said second internal bus and at lease [sicl
`
`one of said peripheral units connected to said second internal bus" is construed to
`
`mean “being transmitted through the second internal bus and at least one of the
`
`peripheral units interfacing directly with the second internal bus.”
`
`
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 7 of 11 PageID #: 6722
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 7 of 11 PagelD #: 6722
`
`c. The term “said intelligent system is connected to said second internal bus” is
`
`construed to mean “the intelligent system interfaces directly with the second internal
`5‘!
`
`bus.
`
`(1. The term “peripheral units connected to said first internal bus and said CPU
`
`through said first internal bus" is construed to mean “peripheral units interfacing
`
`directly with the first internal bus and interfacing with the CPU via the first internal
`
`bus.”
`
`e. The term "said debug resources and said peripheral units .
`
`.
`
`. being connected to
`
`one another through said second internal bus" is construed to mean “the debug
`
`resources and peripheral units interface with one another via the second internal
`
`bus.”
`
`VIII. U.S. Patent No. 5,493,534
`
`1. The term "power conversion means to generate voltage levels necessary for clearing
`
`the electrically programmable and erasable read only memory cells and writing therein" is
`
`construed as a means plus function term, with the fimction being “to generate voltage levels
`
`necessary for clearing the electrically programmable and erasable read only memory cells and
`
`writing therein,” and the structure being “charge pump and Y~select transistors and equivalents.”
`
`The parties agree that the structure for this claim term is at least a charge pump and Y-select
`
`transistors. The patent discloses a generic charge pump as the structure, with a preferred
`
`embodiment indicated in Figs. 11a and 11b. Col.l 11.62-67; col. 4 11.16-18; 001.41.67 - col.5 1.1.
`
`Infineon’s additional proposed structure (c013 11.13-30) is unnecessary to the claimed voltage
`
`level generation function.
`
`r-w-.r1m-H*WWHm—mem
`
`
`
`..m...fiwhw...WW...”Wfl....._.._m,w~_..,.‘
`
`-...-.......n-...M-s...-......_.“.4...—
`
`
`
`
`.__...—_._........3..............3...”...
`
`..-.......wv>1~4-‘-.....,..._
`
`
`
`
`._........._.....—....__.._._.,.
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 8 of 11 PageID #: 6723
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 8 of 11 PagelD #: 6723
`
`2. The term "charge pump means for converting the low voltage supply to a voltage level
`
`which programs and erases the electrically programmable and erasable read only memory
`
`transistors" is construed as “a charge pump.” This recognized, sufficient structure rebuts the
`
`presumption that this claim is a means-plus—fimction claim. See Allen Eng’g v. Bartel! Indus,
`
`299 F.3d 1336, 1347—48 (Fed.Cir. 2002).
`
`3. The term “flash transistor array” does not require construction.
`
`IX. U.S. Patent No. 5,606,532
`
`1. The term "erasable and programmable sub-page sectors" is construed to mean "block of
`
`memory cells less than one memory page that can be individually selected for erasing and
`
`progranuning." This term does not have a plain and ordinary meaning. The intrinsic evidence
`
`indicates that the sub-page sectors can be erased selectively, tie. individually, as well as
`
`collectively. ‘532 Patent at [57]; col.3 11.1-6.
`
`2. The term “write cache” is construed to mean "single buffer connected to the main
`
`memory core for temporarily storing data bytes, not parity bits.“ During prosecution, the
`
`patentee disavowed storing parity information in the write cache. D]. 163 at
`
`IFXATML0002091-93 (Resp. dtd. July 1, 1996). The patentee also disavowed having more than
`
`one write cache.
`
`Id. at IFXATML0002090—92. Finally, the patentee indicated that the write
`
`cache communicates directly with the main memory.
`
`In". at IFXATML0002092; 2089-90; 2078-
`
`79. This intrinsic evidence is more useful and reliable than AtmeI’s proffered extrinsic expert
`
`interpretation of this prosecution history. See Phillips v. A WH Corp, 415 F.3d 1303, 1317-18
`
`(Fed. Cir. 2005) (“[E1xpert reports and testimony [are] generated at the time of and for the
`
`purpose of litigation and thus can suffer from bias that is not present in intrinsic evidence”).
`
`
`
`
`
`IAri-usumrlwHrlwsnM‘xwmmm-w—mr—wmvn-—wr-W
`
`......;m-..1_.,..—.
`...-..«,.rr-.-.Mu......
`~H-ihw—mwm.mm
`
`
`
`
`
`....._..._.fl...,......._....-........~—..__..._,...-.w.,.,_._....
`
`
`
`
`
`.-..w...m.-¢p......._..4..
`
`sum-
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 9 of 11 PageID #: 6724
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 9 of 11 PagelD #: 6724
`
`3. The term "a data bus for accessing a data word section of a memory unit" is construed
`
`to mean "set of conductors for carrying only the data word section of a memory unit separate
`
`from the parity bus," and the term “a parity bus for accessing a parity bit section of a memory
`
`unit" is construed to mean “set of conductors for carrying only the parity bit section of a memory
`
`unit separate from the data bus.” The data bus and parity bus are claimed as separate elements,
`
`and the specification indicates two separate routes. Col.10 1152-55; will 1129-31; col.8 11.52—
`
`55. As explained supra, the patentee disavowed transmitting parity bits through the write cache,
`
`necessitating separate parity and data routes and busses.
`
`X. US. Patent No. 5,732,017
`
`1. The parties informed the Court that they were working toward a stipulated
`
`construction for the term "address decoding and select means connected to said address lines to
`
`receive address signals therefrom for accessing a memory location in a selected one of said
`
`memory arrays, said addre3s decoding and select means including a shared row decoder that is
`
`common to both memory arrays for accessing in said selected memory array a word line
`
`corresponding to said address signals." (D1. 172 at 84). The Court will not construe this term
`
`unless it is notified that the parties could not reach agreement.
`
`2. The terms "control means responsive to input control signals for selecting One of said
`
`memory arrays and selecting a read or write operation for said selected memory array" ! "control
`
`means responsive to input control signals for controlling operation of at least said first and
`
`second column decode and select circuitry and said row address latch circuit to carry out a
`
`selected read or write operation in a selected memory array" are construed as means plus function
`
`terms, with the functions being “selecting one of said memory arrays and selecting a read or write
`
`
`
`-.y.mnun-um..a—werMu-v—w—n-«r-mw—h7-w.:w-.-WWI:‘a-‘w-A'W~.—
`
`
`
`
`
`.._...-.r».mw...__._....._....—..._.w..‘......,.
`
`
`
`--»-t-..-.m-w~—m¢-m----_.......»,._.~.——-na-\—-m...
`
`
`..—._......_.__..,..n.4-
`-F""-rPv——...—.u..-.w........-...
`
`

`

`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 10 of 11 PageID #: 6725
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 10 of 11 PagelD #: 6725
`
`operation for said selected memory array 2’ controlling operation of at least said first and second
`
`column decode and select circuitry and said row address latch circuit to carry out a selected read
`
`or write operation in a selected memory array,” and the structure being “control logic circuitry
`
`and equivalents.” See col.3 ll.5-2S; col.3 l.53-col.6 1.3; Figs. 1, 2A, ZB. This adoption of
`
`Atmel’s proposed construction is without prejudice to Infineon’s ability to argue the claims as
`
`construed are indefinite, with an expert witness who can aid the Court in understanding, inter
`
`alia, the claimed functions and what one of ordinary skill would require to implement them.
`
`X]. US. Patent No. 5,822,245
`
`1. The term “flash memory array” does not require construction.
`
`2. The term "input/output conductors" is construed to mean “electrical conductors
`
`between two components for two-way communication of data.” The patent discloses “HO” lines
`
`with two—way arrows, as distinguished from the claimed “output conductor” with a one-way
`
`arrow. Figs. 1, 2A; cls. 3, 4, 6, 7, 13, 14, 21, 22, 29, 30. The decision to claim both a one-way
`
`output conductor and inputfoutput conductors creates a presumption of a difference in meaning
`
`and scope. See Tendon Corp. v. US. In! ’3 Trade Comm ’n, 831 F.2d 1017, 1023 (Fed. Cir. 1987).
`
`The embodiment Atmel argues is excluded by this construction actually shows conductors D1-
`
`D8 as two-way conductors capable of being in a one-way write mode. Fig.2A; col.6 1156-65.
`
`3. The terms "while said first data is being written to said [flash memory
`
`arrayr’non-volatile memory array]“ and "while said first data is being transferred [out offinto] said
`
`flash memory buffer“ are construed to mean "during a write operation concurrently while said
`
`first data is being written to said [flash memory arrayi’non-volatile memory array]." The parties
`
`10
`
`
`
`
`
`
`
`.mmn.»..m":we..nwm-«Wmuw-._flwwm.hn_w,-v-1...”mmw..an...—-mfitnnawnquv-NHW.M$me"WWW4A4-;
`
`
`
`
`
`
`
`

`

` l
`
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 11 of 11 PageID #: 6726
`Case 1:11-cv-00307-RGA Document 174 Filed 12/04/12 Page 11 of 11 PagelD #: 6726
`
`agree that the write need not start or stop simultaneously, but rather need only overlap to some
`
`extent. (D.I. 172 at 103).
`
`XII. U.S. Patent No. 6,879,518
`
`1. The term “security bit” is construed to mean “a single memory bit located within a
`
`security row of the non—volatile memory. ” The parties agreed upon these limitations. The
`
`Summary of the Invention provides that “in one exemplary embodiment,” the security row
`
`elements can be programmed to an unlocked or locked state. C012 11.9-16. This cannot serve to
`
`additionally limit the term as Atmel proposes.
`
`2. The terms “lockbit / lock bit” are construed to mean "memory bits or elements within
`
`the non-volatile memory that enable and disable external access to the non-volatile memory" in
`
`accordance with the patent’s specific definition. See 001.1 1126—3 1. Infineon’s proposed
`
`limitation improperly relies on c012 11.5-8, which describes use of the Iockbits, but does not
`
`define them.
`
`XIII. U.S. Patent No. 7,428,610
`
`1. The term “write command” does not require construction.
`
`2. The term “address” is construed to mean “a series of usually alphanumeric characters
`
`that specifies the storage location of particular information,” which is the dictionary definition
`
`Atmel proffered and Infineon adopted.
`
`(D.I. 153 at 99-100).
`
`vie
`Entered this fl: day of December, 2012.
`.W
`
`
`United States D strict Judge
`
`ll
`
`